Amplifier with a Converting Circuit with Reduced Intrinsic Time Constant

Abstract

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

Claims

1. An amplifier, comprising: a converting circuit configured to convert a differential input signal into a single ended output signal, the converting circuit comprising: an input section configured to receive the differential input signal; and an output section comprising an output port configured to provide the single ended output signal, wherein the output section comprises a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

2. The amplifier according to claim 1, wherein the input section is connected to the output section through a first node and the output port, and wherein the capacitive element is connected to the first node.

3. The amplifier according to claim 2, wherein the capacitance of the capacitive element is larger than an output parasitic capacitance of the input section.

4. The amplifier according to claim 3, wherein the capacitance of the capacitive element is larger than 4/3 times of the output parasitic capacitance of the input section.

5. The amplifier according to claim 4, wherein the capacitive element is connected to a closed output path of the converting circuit.

6. The amplifier according to claim 1, wherein the input section comprises a first input port, a second input port, a first transistor, a second transistor and a current supply port, wherein the first transistor is connected to the output section, to the first input port and to the current supply port, and wherein the second transistor is connected to the output section, to the second input port, and to the current supply port.

7. The amplifier according to claim 6, wherein an output parasitic capacitance of the input section is based on the related to an output parasitic capacitance of at least one of the first transistor the second transistor.

8. The amplifier according to claim 6, wherein the output section further comprises a first resistor, a second resistor, and a voltage supply port, wherein the first resistor of the output section is connected to the input section, to the voltage supply port and to the second resistor, and wherein the second resistor of the output section is connected to the input section.

9. The amplifier according to claim 8, wherein the first resistor of the output section is connected to the first transistor of the input section, and wherein the second resistor of the output section is connected to the second transistor of the input section.

10. The amplifier according to claim 8, wherein the output port is connected to the second resistor of the output section, and wherein the capacitive element is connected to the first resistor of the output section.

11. The amplifier according to claim 8, wherein the output port is connected to the first resistor of the output section, and wherein the capacitive element is connected to the second resistor of the output section.

12. The amplifier according to claim 8, wherein the capacitive element is further connected to the voltage supply port.

13. The amplifier according to claim 1 wherein the capacitive element comprises at least one of a distributed stub or an interdigital capacitor.

14. The amplifier according to claim 1, wherein the capacitive element is further connected to a ground potential.

15. A method for operating an amplifier, comprising: receiving, by an input section of a converting circuit of the amplifier, a differential input signal; converting, by the converting circuit, the differential input signal into a single ended output signal; reducing, by a capacitive element of an output section of the converting circuit, an intrinsic time constant of the converting circuit; and providing, by the output section of the converting circuit, the single ended output signal.

16. An amplifier, comprising: an input section comprising: a differential pair connected between a first node and differential input ports; and an output section connected to a voltage supply port and the first node, the output section comprising: a capacitive element connected to the first node.

17. The amplifier of claim 16, wherein the differential input ports comprises a first input port and a second input port; and wherein the differential pair comprises a first transistor connected between a current supply port and the first node, and having a first gate connected to the first input port, and wherein the differential pair further comprises a second transistor connected between an output port and the current supply port the having a second gate connected to the second input port.

18. The amplifier of claim 17, wherein the capacitive element is connected between the first node and a ground.

19. The amplifier of claim 17, wherein the capacitive element is one of a distributed stub or an interdigital capacitor, wherein the capacitive element is associated with an intrinsic time constant of the amplifier, and wherein the capacitance of the capacitive element is larger than an output parasitic capacitance of the input section.

20. The amplifier of claim 17, further comprising: a bias voltage element connected to the voltage supply port; a first resistor connected between the first node and the voltage supply port; and a second resistor connected between the output port and the voltage supply port

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

[0059] FIG. 1 shows an amplifier according to an embodiment of the present invention

[0060] FIG. 2 shows an amplifier according to an embodiment of the present invention in more detail

[0061] FIG. 3 shows an example of a voltage gain comparison between the solution according to an embodiment of the present invention and a prior-art solution

[0062] FIG. 4 shows a schematic view of another amplifier according to an embodiment of the present invention

[0063] FIG. 5 shows a schematic view of another amplifier according to an embodiment of the present invention

[0064] FIG. 6 shows a schematic view of another amplifier according to an embodiment of the present invention

[0065] FIG. 7 shows a schematic view of another amplifier according to an embodiment of the present invention

[0066] FIG. 8 shows a schematic view of another amplifier according to an embodiment of the present invention

[0067] FIG. 9 shows a schematic view of a method according to an embodiment of the present invention

[0068] FIG. 10 shows a schematic view of an amplifier according to the prior art

[0069] FIG. 11 shows an example of voltage gain versus frequency of a differential input to single-ended output driver amplifier according to the prior art.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0070] FIG. 1 shows an amplifier 100 according to an embodiment of the present invention. The amplifier 100 comprises a converting circuit 101 for converting a differential input signal iota, 102b into a single ended output signal 103. Thus, the converting circuit 101 includes an input section 104 for receiving the differential input signal 102a, 102b, and an output section 105 with an output port 106 for providing the single ended output signal 103. The output section 105 comprises a capacitive element 107 which is configured to reduce an intrinsic time constant of the converting circuit 101.

[0071] FIG. 2 shows an amplifier 100 according to an embodiment of the present invention in more detail. The amplifier 100 as shown in FIG. 2 comprises the same features and functionality of the amplifier described in view of FIG. 1.

[0072] As shown in FIG. 2, in the differential input to single-ended output differential pair (which comprises a first node 201, a first 202 and second input port 203, a first transistor Q1 and a second transistor Q2, a first RD1 and second resistor RD2, an output port 106, a current supply port 204 and a voltage supply port 205) of the amplifier 100, a further capacitive element 107 (e.g. a capacitor C1) is added to an output closed path of the differential input to single-ended output differential pair. The output closed path comprises resistor RD1, drain-source terminals of transistor Q1, source-drain terminals of transistor Q2 and resistor RD2.

[0073] The differential input to single-ended output voltage gain of the differential pair according to an embodiment the present invention can be formulated according to the following equation.

[00003]$\begin{array}{cc}{A}_V=g_m.Math.\frac{R_D.Math.\left(1+j\omega .Math.R_D.Math.C_1\right)}{2.Math.\left(1+j\omega .Math.R_D.Math.\left(C_{DS}+C_1\right)\right)-{\omega }^2.Math.R_D^2.Math.C_{DS}.Math.C_1}& \left(3\right)\end{array}$

[0074] wherein R.sub.D=R.sub.D1=R.sub.D2, and C.sub.DS=C.sub.DS1=C.sub.DS2. That is, equation (3) can also be formulated as follows.

[00004]$A_V=g_m.Math.\frac{\left(\frac{R_{D1}+R_{D2}}{2}\right).Math.\left(1+j\omega .Math.\left(\frac{R_{D1}+R_{D2}}{2}\right).Math.C_1\right)}{\begin{array}{c}2.Math.\left(1+j\omega .Math.\left(\frac{R_{D1}+R_{D2}}{2}\right).Math.\left(\left(\frac{C_{DS1}+C_{DS2}}{2}\right)+C_1\right)\right)-\\ {\omega }^2.Math.{\left(\frac{R_{D1}+R_{D2}}{2}\right)}^2.Math.\left(\frac{C_{DS1}+C_{DS2}}{2}\right).Math.C_1\end{array}}$

[0075] By comparing the voltage gain of the proposed solution (equation 3) and the prior-art solution (equation 1) it can be noted that, if C1>4/3.Math.C.sub.Ds, the 3 dB bandwidth of the proposed solution is wider than the prior-art solution.

[0076] The two capacitors CDS1 and CDS2 in FIG. 2 are not components of the differential pair. They refer to an intrinsic output parasitic capacity of the two transistors Q1, respectively Q2.

[0077] In order to better show the benefit of embodiments of the present invention, in view of FIG. 3 a differential input to single-ended output differential pair designed according an embodiment to the present invention is compared with a differential pair designed according to a prior-art solution. For the comparison the same transistors (Q1 and Q2), same load resistors (RD1, RD2), same current source (IS) and same bias voltage (VD) are used in both cases. Moreover, the capacitor C1 used for the comparison is selected to be 2.8 times of CDS (which is an optional feature of embodiments of the present invention, that is the beneficial effect is also achieved with other ratios). The comparison between the resulting voltage gain of the two cases is reported in FIG. 3, where a solid line is the voltage gain of the solution according to embodiments of the present invention and a dashed line is the voltage gain of the prior-art solution. As it is possible to note, the solution of embodiments of the present invention allows to reach a much wider bandwidth with respect to the prior-art solution considering the same transistors, load resistors and biasing current and voltage, i.e. the same DC gain, linearity and power consumption.

[0078] FIG. 4 shows a schematic view of an amplifier 100 according to an embodiment of the present invention. The amplifier 100 of FIG. 4 includes the same features and functionality as the amplifiers 100 of FIG. 1 and FIG. 2 above.

[0079] The embodiment of the amplifier 100 as shown in FIG. 4 comprises a differential pair (transistor Q1, transistor Q2, first resistor RD1, second resistor RD2, voltage source VD and current source IS), a capacitor C1 107, a differential input (Vin+ and Vin− at the first input port 202, respectively the second input port 203) and a single a single-ended output 106 (providing Vout).

[0080] The size of the transistors Q1 and Q2 can be the same. They however can also be of different size. The value of the resistors RD1 and RD2 can be the same. They however can also be of different values. The value of the capacitor C1 is selected to optimize the bandwidth the driver amplifier. The embodiment shown in FIG. 4 is the easiest way to fully integrate the present invention, e.g. in Monolithic Microwave Integrated Circuit technologies.

[0081] An alternative embodiment of the present invention is shown in FIG. 5, in which the output voltage Vout and the capacitor C1 107 nodes are inverted.

[0082] A further alternative embodiment of the present invention is shown in FIG. 6, in which the capacitor C1 107 is implemented by means of a distributed stub.

[0083] A further alternative embodiment of the present invention is shown in FIG. 7, where the capacitor C1 107 is implemented by means of an interdigital capacitor.

[0084] A further alternative embodiment of the present invention is shown in FIG. 8, where the capacitor C1 107 is connected to the bias voltage supplier VD instead of ground.

[0085] FIG. 9 shows a schematic view of a method 900 for operating an amplifier boo, e.g. for an optical communication device. The method 900 comprises a first step of receiving 901, by an input section 104 of a converting circuit 101 of the amplifier 100, a differential input signal 102a, 102b. The method 900 comprises a further step of converting 902, by the converting circuit 101, the differential input signal 102a, 102b into a single ended output signal 103. The method 900 comprises a further step of reducing 903, by a capacitive element 107 of the output section 105, an intrinsic time constant of the converting circuit 101. The method 900 also comprises a step of providing 904, by an output section 105 of the converting circuit 101, the single ended output signal 103.

[0086] Embodiments of the present invention have been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.