Bandwidth Enhanced Gain Stage with Improved Common Mode Rejection Ratio

Abstract

The present disclosure relates to a gain stage for an amplifier and to the amplifier. The amplifier may be a broad-band amplifier, trans-impedance amplifier and/or driver amplifier. The gain stage includes a differential input transconductor, a loading network and a differential output terminal. Further, the gain stage includes at least one pair of inductances connected within the loading network or between the differential input transconductor and the differential output terminal.

Claims

1.-14. (canceled)

15. A gain stage for an amplifier, wherein the gain stage comprises: a differential input transconductor; a loading network; a differential output terminal; and at least one pair of inductors connected within the loading network, or connected between the differential input transconductor and the differential output terminal, wherein inductors of the at least one pair of inductors are coupled.

16. The gain stage according to claim 15, further comprising: a pair of load resistors connected to the differential input transconductor; and wherein a first pair of inductors of the at least one pair of inductors is connected in series to the pair of load resistors, and inductors of the first pair of inductors are coupled.

17. The gain stage according to claim 16, wherein: a second pair of inductors of the at least one pair of inductors is connected between the differential input transconductor and the differential output terminal, wherein inductors of the second pair of inductors are coupled.

18. The gain stage according to claim 17, wherein: a first coupling factor between the inductors of the first pair of inductors is the same as a second coupling factor between the inductors of the second pair of inductors.

19. The gain stage according to claim 17, wherein: a first coupling factor between the inductors of the first pair of inductors is different from a second coupling factor between the inductors of the second pair of inductors.

20. The gain stage according to claim 17, wherein: the first pair of inductors is coupled to the second pair of inductors.

21. The gain stage according to claim 15, wherein: a coupling factor between the inductors of at least one pair of inductors is larger than 0.25.

22. The gain stage according to claim 15, wherein: a coupling factor between the inductors of at least one pair of inductors is in a range of 0.4-0.6.

23. The gain stage according to claim 15, wherein: the differential input transconductor comprises control terminals of two first transistors, and the differential output terminal comprises control terminals of two second transistors.

24. The gain stage according to claim 23, further comprising: a tail current generator connected to the differential input transconductor.

25. The gain stage according to claim 15, wherein the gain stage is based on a Shunt Peaking topology, an Inductive Interstage Network topology, or a Triple Resonant Network topology.

26. The gain stage according to claim 15, wherein: the inductors of the at least one pair of inductors are implemented in Complementary Metal-Oxide-Semiconductor (CMOS) technology, in SiGe Bipolar-CMOS technology, or in GaAs technology.

27. The gain stage according to claim 15, wherein: the inductors of the at least one pair of inductors are distributed over at least two separated metal layers.

28. An amplifier, comprising a gain stage, wherein the gain stage comprises: a differential input transconductor; a loading network; a differential output terminal; and at least one pair of inductors connected within the loading network, or connected between the differential input transconductor and the differential output terminal, wherein inductors of the at least one pair of inductors are coupled.

29. The amplifier according to claim 28, wherein the amplifier is a broad-band amplifier, a trans-impedance amplifier, or driver amplifier.

30. The amplifier according to claim 28, wherein the gain stage further comprises: a pair of load resistors connected to the differential input transconductor; and wherein a first pair of inductors of the at least one pair of inductors is connected in series to the pair of load resistors, wherein inductors of the first pair of inductors are coupled.

31. The amplifier according to claim 30, wherein: a second pair of inductors of the at least one pair of inductors is connected between the differential input transconductor and the differential output terminal, wherein inductors of the second pair of inductors are coupled.

32. The amplifier according to claim 31, wherein: a first coupling factor between the inductors of the first pair of inductors is the same as a second coupling factor between the inductors of the second pair of inductors.

33. The gain stage according to claim 31, wherein: a first coupling factor between the inductors of the first pair of inductors is different from a second coupling factor between the inductors of the second pair of inductors.

34. The gain stage according to claim 31, wherein: the first pair of inductors is coupled to the second pair of inductors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

[0046] FIG. 1 shows a gain stage according to an embodiment of the invention.

[0047] FIG. 2 shows a gain stage according to an embodiment of the invention, which is based on a TRN topology.

[0048] FIG. 3 shows normalized common mode gain versus frequency for different coupling factors k.

[0049] FIG. 4 shows CMRR improvement versus frequency for different coupling factors k. For increasing coupling factor k, the CMRR is improved in the high frequency range.

[0050] FIG. 5 shows a gain stage according to an embodiment of the invention including a tail current generator.

[0051] FIG. 6 shows CMRR versus frequency for a gain stage including a tail current generator, as shown in FIG. 5.

[0052] FIG. 7 shows CMRR versus frequency for different gain stages according to embodiments of the invention, namely (a) a gain stage based on an Inductive Interstage Network topology, and (b) a gain stage based on a Shunt Peaking topology.

[0053] FIG. 8 shows a possible layout for realizing the coupled inductances of a gain stage according to an embodiment of the invention.

[0054] FIG. 9 shows a gain stage according to an embodiment of the invention, which is based on a TRN topology, and shows a possible layout for its coupled inductances.

[0055] FIG. 10 shows CMRR versus frequency for a gain stage having the inductances layout shown in FIG. 9.

[0056] FIG. 11 shows an example of a gain stage for an amplifier.

[0057] FIG. 12 shows an example of a gain stage, which is based on a Shunt Peaking topology.

[0058] FIG. 13 shows an example of a gain stage, which is based on an Inductive Interstage Network topology

[0059] FIG. 14 shows an example of a gain stage, which is based on a TRN topology.

[0060] FIG. 15 shows normalized differential gain versus frequency for example gain stages of different topologies.

[0061] FIG. 16 shows an example of a gain stage including a tail current generator.

[0062] FIG. 17 shows CMRR versus frequency for an example gain stage including a tail current generator, as shown in FIG. 16.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0063] FIG. 1 shows a gain stage 100 according to an embodiment of the invention. The gain stage 100 is configured to be used in an amplifier, particularly in a broad-band amplifier, a TIA and/or a driver amplifier. The amplifier comprises at least one gain stage 100, and in particular it may comprise multiple gain stages 100. The gain stage 100 may be a differential gain stage.

[0064] The gain stage 100 comprises a differential input transconductor 101, a loading network 102, and a differential output terminal 103. Further, the gain stage 100 comprises at least one pair 104a and/or 104b of inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T, which are pairwise connected within the loading network 102 and/or are connected between the differential input transconductor 101 and the differential output terminal 103. Thus, the gain stage 100 can be based on a Shunt Peaking topology (with a first inductance pair 104 within the loading network 102), based on an Inductive Interstage Network topology (with a second inductance pair 104b between the transconductor 101 and the output terminal 103), or based on a Triple Resonant Network topology (with both the first inductance pair 104a and the second inductance pair 104b).

[0065] In order to enhance the CMRR of the gain stage 100, the inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T of at least one pair 104a, 104b of inductances are coupled. That means, the inductances L1.sub.T and L2.sub.T of the inductance pair 104a may be coupled, and/or the inductances L3.sub.T and L4.sub.T of the inductance pair 104b may be coupled. In particular, the inductances in each pair 104a and 104b may be coupled to another. Furthermore, the inductance pair 104a may also be coupled to the inductance pair 104b.

[0066] Thus, a main feature of the gain stage 100 is the introduction of the coupling between the inductances of at least one pair 104a and 104b (i.e. transformers). This creates an unbalance between the differential and common mode frequency responses of the gain stage 100 at high frequencies. Further, this leads to an improved CMRR, especially at the high frequencies.

[0067] To understand this effect better, the gain stage 100 shown in FIG. 2 can be considered. The gain stage 100 shown in FIG. 2 builds on the gain stage 100 shown in FIG. 1, i.e. it is a more specific implementation thereof. Same elements in FIG. 1 and FIG. 2 share the same reference signs and function likewise.

[0068] The gain stage 100 of FIG. 2 is in the TRN configuration, i.e. it is based on a TRN topology with both inductance pairs 104a and 104b included. In particular, the gain stage 100 of FIG. 2 includes a pair of load resistors R1 and R2 connected to the differential input transconductor 101, and the first pair 104a of coupled inductances L1.sub.T and L2.sub.T is connected in series to the pair of load resistors R1 and R2. The gain stage 100 further includes capacitor pairs C1/C2 and C3/C4 taking into account the parasitic capacitance at the output node related to gain stage 100 and the next gain stage. The second pair 104b, of inductances L3.sub.T and L4.sub.T is connected between the differential input transconductor 101 and the differential output terminal 103, in particular between the capacitor pair C1/C2 and the capacitor pair C3/C4.

[0069] In the gain stage 100 of FIG. 2, the differential input transconductor 101 includes control terminals of two first transistors Q1 and Q2, and the differential output terminal 103 includes control terminals of two second transistors Q3 and Q4. The two second transistors Q3/Q4 may form also a differential input transconductor of a next gain stage.

[0070] As also shown in FIG. 2, coupling factor k.sub.1 and k.sub.2 are introduced between the loading inductances L1.sub.T and L2.sub.T of the first pair 104a, and the series inductances L3.sub.T and L4.sub.T of the second pair 104b, respectively. That is, the inductances L1.sub.T and L2.sub.T of the first pair 104a are coupled, and the inductances L3.sub.T and L4.sub.T of the second pair 104b are also coupled amongst each other. Moreover, to focus on the improvement given by the gain stage 100, a pseudo-differential input pair (Q1 and Q2 emitters toward ground) may be considered, thus removing any CMR coming from them (no tail current generator). The mutual inductance between L1.sub.T and L2.sub.T—exemplarily in the first pair 104—can be expressed as:

[00003]$M_{1-2}=k_1.Math.\sqrt{L{1}_T.Math.L{2}_T}=k_1.Math.L{1}_T$

[0071] L1.sub.T=L2.sub.T may thereby be assumed, since the gain stage 100 is differential and 0<k.sub.1<1. This leads to the conclusion that the inductance seen in differential mode can be expressed as:

[00004]$L{1}_{DM}=L{1}_T+M_{1-2}=L{1}_T.Math.\left(1+k_1\right).$

[0072] To obtain the same differential frequency response in the uncoupled scenario, each inductance in the transformer (L1.sub.T and L2.sub.T) would have to be designed as L1.sub.T=L1/(1+k.sub.1). Notice that, for increasing k, the value of each inductance in the first pair 104a (transformer) is reduced (down to ½ of the single ended value for k=1), thus minimizing area occupation. While boosting the inductance value in differential mode, the coupling reduces the value of the common mode inductance, following the equation:

[00005]$L{1}_{CM}=L{1}_T-M_{1-2}=L{1}_T.Math.\left(1-k_1\right).$

[0073] The same concept can be applied to the second pair 104b of inductances L3.sub.T and L4.sub.T. In conclusion, for increasing k values (increasing coupling factors k), the differential transfer function can be kept constant, scaling down the inductances in the transformers, while the decrease of their common mode value reduces the bandwidth of the common mode frequency response, thus improving CMRR at high frequencies. This is illustrated in FIG. 3, in which the normalized common mode transfer functions versus frequency are shown for different coupling factors, assuming as an example k=k.sub.1=k.sub.2. Further, FIG. 4 depicts the CMRR in the same conditions. It can be seen that the higher the coupling factor k (here values k=0, k=0.25, k=0.5, k=0.75 and k=1 are compared), the stronger the CMRR of the gain stage 100 is improved, especially in the high frequency range. Generally, in the gain stage 100 of each described embodiment, either coupling factor k may be larger than 0.1, particularly larger than 0.25. More specifically, the coupling factor(s) k may be in a range of 0.3-0.7, in particular in a range of 0.4-0.6. The coupling factors of the two pairs 104a and 104b may be the same or may be different.

[0074] In the following, it is explained in detail how a gain stage 100 according to an embodiment of the invention can be implemented based on the TRN topology. FIG. 5 shows such a gain stage 100, which builds on the gain stages 100 shown in FIG. 1 and FIG. 2, i.e. it is a more specific implementation thereof. Same elements in FIG. 1, FIG. 2 and FIG. 5 share the same reference signs and function likewise. The gain stage 100 shown in FIG. 5 comprises a tail current generator 500 connected to the differential input transconductor 101 terminal. The tail current generator 500 can be like the one shown in FIG. 16, and described in detail above.

[0075] FIG. 6 shows the simulation results for the gain stage 100 of FIG. 5, wherein a fully differential input pair is used. Compared to the example gain stage of FIG. 16 (black curve in the plot of FIG. 6) without any inductance coupling, the CMRR of the gain stage 100 is improved, particularly in the high frequency range (regardless of how high the coupling factor k is). The example gain stage fails to achieve the required CMRR value.

[0076] In the same way, the coupling in the inductance pair 104a or 104b can be applied to a gain stage 100, which is based on a Shunt Peaking topology (i.e. only the first inductance pair 104a is included in the loading network 102) or to a gain stage 100, which is based on an Inductive Interstage Network topology (i.e. only the second inductance pair 104b is included between the input transconductor 101 and the output terminal 103). Simulation results for such gain stages 100 are shown in FIG. 7, demonstrating that the CMRR improves in both cases for an increasing coupling factor k, compared to example gain stages without any coupling.

[0077] For the gain stages 100 according to the embodiments of the invention, SiGe BiCMOS technology may be used, as it is currently the technology of choice for very high frequency applications (several tens of GHz). However, the same gain stages 100 can be fabricated with other IC technologies, such as (but not limited to) CMOS or GaAs. In particular, in the gain stages 100 according to embodiments of the invention, the inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T of at least one pair 104a, 104b of inductances may be implemented in CMOS technology, in SiGe BiCMOS technology, or in GaAs technology.

[0078] A layout example of an inductance pair (transformer), which can be used in all presented gain stages 100 either as the first inductance pair 104a or the second inductance pair 104b (or both), is shown in FIG. 8. For this layout, two metal layers are used, one (“upper metal layer”) for the core of the inductances, and one (“lower metal layer”) for the crossings. That is the inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T of the at least one pair 104a, 104b of inductances may be distributed over at least two separated metal layers.

[0079] For the gain stage 100 based on the TRN topology, in which as shown in FIG. 9 two pairs 104a and 104b, of coupled inductances are provided, the compact layout concept of FIG. 8 can be used. That is, the inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T of both pairs 104a, 104b of inductances may be distributed over at least two separated metal layers. With this layout, another coupling (k.sub.cross in FIG. 9) may also be exploited, namely between the inductance pairs 104a, 105b. Its effect is to give an additional boost to the inductance value in the two inductance pairs 104a and 104b, without degrading the CMRR. In other words, the first pair 104a of inductances L1.sub.T and L2.sub.T may be coupled to the second pair 104b of inductances L3.sub.T and L4.sub.T. The simulated CMRR of the gain stage 100 shown in FIG. 9 is shown in FIG. 10, again in comparison to a similar gain stage 100 without coupling.

[0080] The gain stages 100 according to embodiments of the invention as described above, are suitable to be implemented in a monolithic integrated circuit. Integrated inductances L1.sub.T, L2.sub.T, L3.sub.T, L4.sub.T for high frequency applications may thereby be made of top metal layers or lower metal layers.

[0081] Embodiments of the present invention have been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.