An Infrared-transmitting High-sensitivity Visible Light Detector and Preparation Method Thereof

Abstract

The invention relates to an infrared-transmitting high-sensitivity visible light detector and its preparation method. The detector is composed of passivation layer (14), upper electrode (13), heterojunction (15), lower electrode (3), and intrinsic monocrystalline silicon substrate (2). The upper electrode (13) is the material that is electrically conductive and transparent to visible light and infrared light. The heterojunction (15) is divided into heterojunction upper layer (5) and heterojunction lower layer (4), wherein the upper heterojunction layer (5) is a nano film sensitive to visible light and capable of transmitting infrared ray, and the lower heterojunction layer (4) is intrinsic monocrystalline silicon. When visible light and infrared light pass through the upper electrode (13) and the heterojunction upper layer (5), the visible light excites electron-hole pairs in the heterojunction (15), which are collected by the upper and lower electrodes and flow out through longitudinally arranged metal columns, while infrared light passes through the whole detection structure, so that visible light can be detected without affecting infrared transmission. The distance between the electrode and the junction zone is very small, which can reduce the recombination rate of electron-hole pairs before reaching the electrode and improve the collection efficiency of photo-generated carriers. The structural design of longitudinal metal reduces light shielding and improves sensitivity.

Claims

1. An infrared-transmitting high-sensitivity visible light detector, characterized in that it comprises an intrinsic monocrystalline silicon substrate (2), a lower electrode (3), a heterojunction (15) for detecting visible light, a metal frame (12), an upper electrode (13) and a passivation layer (14) from bottom to top; wherein the heterojunction (15) comprises a heterojunction lower layer (4) and a heterojunction upper layer (5); the upper electrode (13) is made of conductive and transparent material to visible light and infrared, which is a grid composed of one-dimensional conductive nanowires; the heterojunction upper layer (5) is a nano-film sensitive to visible light and transparent to infrared; the heterojunction lower layer (4) is intrinsic monocrystalline silicon; the lower electrode (3) is a conductive layer formed by heavily doped ions of intrinsic monocrystalline silicon; below the lower electrode (3) is an intrinsic monocrystalline silicon substrate (2).

2. An infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the thickness of the lower electrode (3) is 2-20 μm; wherein the heavily doped ions are phosphorus ions, boron ions or arsenic ions.

3. An infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the thickness of the heterojunction lower layer (4) is 1-10 μm.

4. An infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the thickness of the heterojunction upper layer (5) is ≤5 nm, which is a nano film composed of two-dimensional materials sensitive to visible light; the two-dimensional material is graphene or two-dimensional transition metal sulfide, and the two-dimensional transition metal sulfide is molybdenum disulfide (MoS.sub.2), tungsten disulfide (WS.sub.2), molybdenum diselenide (MoSe.sub.2) or tungsten diselenide (WSe.sub.2).

5. The infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the metal frame (12) is square and annular and surrounds the upper electrode (13) from all sides; the upper electrode (13) is step-shaped and comprises peripheral step, a middle bottom and side walls connecting the peripheral steps and the middle bottom, wherein the peripheral step of the upper electrode (13) is higher than the middle bottom; the upper surface of the metal frame (12) is in contact with the lower surface of the peripheral step of the upper electrode (13), the inside of the metal frame (12) is in contact with the side walls of the upper electrode (13), and the lower surface of the metal frame (12) is in contact with the heterojunction upper layer (5). The lower surface of the middle bottom of the upper electrode (13) is in contact with the upper surface of the heterojunction upper layer (5).

6. The infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the one-dimensional conductive nanowires are carbon nanotubes or silver nanowires.

7. The infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that the passivation layer (14) is any one of zinc sulfide, zinc selenide or magnesium fluoride.

8. The infrared-transmitting high-sensitivity visible light detector according to claim 1, characterized in that a through hole (6) is opened at one corner of the detection unit from the lower surface of the intrinsic monocrystalline silicon substrate (2) up to the upper surface of the heterojunction upper layer (5); at the opposite corner of the detection unit, an opening (7) is set from the lower surface of the intrinsic monocrystalline silicon substrate (2) up to the inside of the lower electrode (3); on the lower surface of the intrinsic monocrystalline silicon substrate (2), the opening positions of the through hole (6) and the opening (7) are located at two corners on the same diagonal of the bottom surface of the detection unit; after the side walls of the through hole (6) and the hole (7) are passivated, the holes are filled with conductive metal, and the conductive metal is any one of gold, silver, copper or aluminum.

9. The infrared-transmitting high-sensitivity visible light detector according to claim 8, characterized in that the upper end opening of the through hole (6) is located at a corner below the metal frame (12) and is in contact with the metal frame (12). The conductive metal in the through hole (6) and the opening (7) protrudes from the lower surface of the intrinsic monocrystalline silicon substrate (2).

10. A preparation method of the infrared-transmitting high-sensitivity visible light detector according to claim 9, characterized in that it comprises the following steps: Step 1, inject heavily doped ions into an area below 1-10 μm from the upper surface of the intrinsic monocrystalline silicon chip (1) as a lower electrode (3); the heavily doped ions are phosphorus ions, boron ions or arsenic ions; the thickness of the lower electrode (3) is 2-20 μm; intrinsic monocrystalline silicon above the lower electrode (3) is heterojunction lower layer (4), and intrinsic monocrystalline silicon below the lower electrode (3) is intrinsic monocrystalline silicon substrate (2); Step 2, deposit a nano film sensitive to visible light and transparent to infrared on the upper surface of the heterojunction lower layer (4) by a chemical vapor deposition method to form a heterojunction upper layer (5); the nano film material is either graphene or two-dimensional transition metal sulfide; the heterojunction upper layer (5) and the heterojunction lower layer (4) together form a heterojunction (15); Step 3, etch a through hole (6) from the lower surface of the intrinsic monocrystalline silicon substrate (2) up to the upper surface of the heterojunction upper layer (5) at one corner of the detection unit; etch opening (7) from the lower surface of the intrinsic monocrystalline silicon substrate (2) up to the inside of the lower electrode (3) at the opposite corner of the detection unit; passivate and insulate the side walls of the through hole (6) and opening (7), and then deposit conductive metals so that the conductive metals of the through hole (6) and opening (7) will protrude from the lower surface of the intrinsic monocrystalline silicon substrate (2); prepare a square annular metal frame (12) on the upper surface of the heterojunction upper layer (5), and contact and conduct the metal in the through hole (6); Step 4, manufacture an upper electrode (13) on the heterojunction upper layer (5) and the upper surface of the metal frame (12); Step 5, deposit a passivation layer (14) on the upper electrode (13), pattern the passivation layer (14) into a probe unit shape by photoetching and etching, and etch the upper electrode (12), the heterojunction upper layer (5), the heterojunction lower layer (4) and the lower electrode (3) by using the patterned passivation layer (14) as a masking layer; thus to form an infrared-transmitting high-sensitivity visible light detector.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0034] FIG. 1 is a structural diagram of a visible light detector according to the present invention;

[0035] Wherein: (a) is a main view, and (b) is a top view;

[0036] FIG. 2 is a sectional view of the visible light detector of the present invention in direction A-A in FIG. 1 (b);

[0037] FIG. 3 is a manufacturing flow chart of the visible light detector of the present invention, each of which is a sectional view in direction A-A in FIG. 1 (b);

[0038] Wherein: (a) is the device structure diagram of part of the process in step 1;

[0039] (b) is the device structure diagram of part of the process in step 1;

[0040] (c) is the device structure diagram in step 2;

[0041] (d) is the device structure diagram from step 3 to step 5;

[0042] (e) is the device structure diagram of part of the process in step 6;

[0043] (f) is the device structure diagram of part of the process in step 6;

[0044] (g) is the device structural diagram in step 7;

[0045] (h) is the device structure diagram in step 8;

[0046] (i) is the device structure diagram in step 9;

[0047] Wherein: 1—intrinsic monocrystalline silicon chip; 2—intrinsic monocrystalline silicon substrate; 3—lower electrode; 4—heterojunction lower layer; 5—heterojunction upper layer; 6—through hole; 7—opening; 8—insulating layer of through hole; 9—insulating layer of opening; 10—first conductive metal column; 11—second conductive metal column; 12—metal frame; 13—upper electrode; 14—passivation layer;

DETAILED DESCRIPTION

[0048] The invention will be further described in detail as follows with reference to the drawings:

[0049] As is shown in FIG. 1, the invention discloses an infrared-transmitting high-sensitivity visible light detector and preparation method. The infrared-transparent high-sensitivity visible light detector comprises a passivation layer 14, an upper electrode 13, a heterojunction 15, a lower electrode 3 and an intrinsic monocrystalline silicon substrate 2 from top to bottom; The heterojunction 15 includes a heterojunction upper layer 5 and a heterojunction lower layer 4;

[0050] The lower electrode 3 is silicon with conductivity formed by heavily doped phosphorus, boron, and beryllium plasma below the area 1-10 μm away from the upper surface of the intrinsic monocrystalline silicon chip, and the thickness of the lower electrode 3 is 2-20 μm. The heterojunction lower layer 4 and the intrinsic monocrystalline silicon substrate 2 are both intrinsic monocrystalline silicon.

[0051] In the manufacturing process of heterojunction lower layer 4, lower electrode 3 and intrinsic monocrystalline silicon substrate 2, the intrinsic monocrystalline chip 1 is divided into three layers by heavily doped silicon, the upper and lower layers are intrinsic monocrystalline silicon and the middle layer is heavily doped silicon. Heavily doped silicon is used as the lower electrode 3, intrinsic monocrystalline silicon above the heavily doped silicon is used as the heterojunction lower layer 4, and intrinsic monocrystalline silicon below the heavily doped silicon is used as the intrinsic monocrystalline silicon substrate 2. Since silicon can transmit infrared, the lower electrode 3 can transmit infrared while conducting electricity.

[0052] As is shown in FIG. 2 and FIG. 3 (b), the heterojunction 15 includes two layers: a heterojunction upper layer 5 and a heterojunction lower layer 4, wherein the heterojunction upper layer 5 is a nano film made of two-dimensional materials capable of detecting visible light and transmitting infrared light, and the thickness of the nano film material is ≤5 nm. The nano-film material is graphene or two-dimensional transition metal sulfide, which includes MoS.sub.2, WS.sub.2, MoSe.sub.2, WSe.sub.2. Because of its thin thickness, it transmits infrared while detecting visible light. The heterojunction lower layer 4 is intrinsic monocrystalline silicon on the surface layer of the intrinsic monocrystalline silicon chip 1, and has a thickness of 1-10 μm.

[0053] As is shown in FIG. 2, the detector structure of the invention is divided into passivation layer 14, upper electrode 13, metal frame 12, heterojunction upper layer 5, heterojunction lower layer 4, lower electrode 3 and intrinsic monocrystalline silicon substrate 2 from top to bottom. The passivation layer 14 is made of an insulating material that transmits visible light and infrared, such as zinc sulfide, zinc selenide and magnesium fluoride. The upper electrode 13 is a conductive material that can transmit visible light and infrared, and has good conductivity, including grids formed by one-dimensional conductive nanowires in various forms, such as carbon nanotube grids and silver nanowire grids. The mesh wires of the conductive nanowire grids are conductive, and the meshes are light-transmitting (visible light and infrared). The metal frame 12 is square and annular, and surrounds the upper electrode 13 from all sides. The upper electrode 13 is stepped, including peripheral steps, a middle bottom, and side walls connecting the peripheral steps and the middle bottom. The upper surface of metal frame 12 is in contact with the lower surface of the peripheral steps of the upper electrode 13, the inside of metal frame 12 is in contact with the side wall of upper electrode 13, the lower surface of metal frame 12 is in contact with heterojunction upper layer 5, the middle bottom of upper electrode 13 is in contact with the upper surface of heterojunction upper layer 5; with the above structure, the upper electrode 13 continuously covers the upper surface of the heterojunction upper layer 5, the side wall of the metal frame 12, and the upper surface. The heterojunction lower layer 4 is intrinsic monocrystalline silicon, and the heterojunction upper layer 5 is a nanometer thin film sensitive to visible light and transparent to infrared, and the heterojunction lower layer 4 and the heterojunction upper layer 5 together form heterojunction 15. The lower part of the heterojunction lower layer 4 is a lower electrode 3, and below of the lower electrode 3 is an intrinsic monocrystalline silicon substrate 2.

[0054] It can be seen from the above analysis that the upper electrode 13 is a one-dimensional nano-wire grid and the heterojunction upper layer 5 is a two-dimensional nano-film, so the upper electrode 13 and the heterojunction upper layer 5 can transmit visible light and infrared, while the heterojunction lower layer 4, the lower electrode 3 and the intrinsic monocrystalline silicon substrate 2 are essentially silicon and transparent to infrared, so the whole detector structure can detect visible light without affecting infrared transmission.

[0055] As is shown in FIG. 2, at one corner of that detection unit, from the lower surface of the intrinsic monocrystalline silicon substrate 2 up to the upper surface of the heterojunction upper layer 5, the detector is provided with a through hole 6; on the opposite side of the through hole 6 in the detection unit, an opening 7 is formed from the lower surface of the intrinsic monocrystalline silicon substrate 2 up to the inside of the lower electrode 3. The lower end openings of the through hole 6 and the opening 7 are respectively at two ends of a diagonal line of the detection unit on the lower surface of the intrinsic monocrystalline silicon substrate 2. The through hole 6 and the opening 7 are filled with conductive metals, such as gold, silver, copper, aluminum, etc., and the filled conductive metals protrude from the lower surface of the intrinsic monocrystalline silicon substrate 2, wherein the conductive metal in the through hole 6 is the first conductive metal column 10, and the conductive metal in the opening 7 is the second conductive metal column 11. Photo-generated carriers generated by the heterojunction 15 can be led out along the conductive metal column in the through hole 6 and the opening 7 under the effect of the electric field generated by the upper electrode 13 and the lower electrode 3. The conductive metal columns in the through hole 6 are in contact with the metal frame 12, and the conductive metal columns in the through hole 6 and the opening 7 protrude from the lower surface of the intrinsic monocrystalline silicon substrate 2, which are used to interconnect the detector signal with other chips by reverse chip bonding. The electrons generated by heterojunction 15 flow out under the effect of electric field generated by upper electrode 13 and lower electrode 3 and are collected by metal frame 12. The signals collected by metal frame 12 flow out through first conductive metal column 10 in through hole 6, the holes generated by heterojunction 15 are collected by lower electrode 3 and flow out through second conductive metal column 11 in opening 7. In this way, the signals extracted by the conductive metal are distributed along the longitudinal direction of the detector, which can prevent the visible light from reaching the heterojunction interface and the infrared from passing through the whole multilayer detection structure in the sensitive area.

[0056] Working Process:

[0057] As is shown in FIG. 2, when visible light and infrared enter the detection structure, they pass through the upper electrode 13 which is conductive and transparent to visible light and infrared, and then pass through the heterojunction upper layer 5 which is made of two-dimensional transition metal sulfide, graphene and other nano film materials which can detect visible light and transmit infrared, and reach the heterojunction area near the interface between the heterojunction upper layer 5 and the heterojunction lower layer 4, and the heterojunction 15 generates photo-generated carriers under the excitation of visible light. In the electric field generated by the upper and lower electrodes, the electrons in the photo-generated carriers pass through the heterojunction upper layer 5 and the upper electrode 13, and are collected by the metal frame 12 in contact with the lower surface of the upper electrode 13. The electrons collected by the metal frame 12 flow out through the first conductive metal column 10 in the longitudinally distributed through hole 6, while the holes in the photo-generated carriers are collected by the lower electrode and flow out through the second conductive metal column 11 in the opening 7. The number of photo-generated carriers represents the intensity of incident light, and realizes its photoelectric detection function, while infrared light continues to pass through the whole detection structure, that is, the whole visible light detector can transmit infrared light.

[0058] The preparation method of the detector comprises the following steps:

[0059] Step 1: Prepare the lower electrode 3

[0060] As is shown in FIG. 3 (a), a double-sided polished intrinsic monocrystalline silicon chip 1 with a thickness of 100 μm is taken, phosphorus ions are implanted into the area below 5 μm of the surface layer of the silicon chip, and then rapid thermal annealing (RTA) is performed after implantation, and the implanted ions are activated to form a heavily doped area with a thickness of 10 μm, which is the lower electrode 3, while intrinsic monocrystalline silicon remains above the heavily doped region as the heterojunction lower layer 4, as shown in FIG. 3 (b); at this time, intrinsic monocrystalline silicon chip 1 is divided into heterojunction lower layer 4, lower electrode 3 and intrinsic monocrystalline silicon substrate 2.

[0061] Step 2: Prepare the heterojunction upper layer 5

[0062] As is shown in FIG. 3 (c), molybdenum disulfide of nano film material is prepared on the surface of the heterojunction lower layer 4 by chemical vapor deposition to form the heterojunction upper layer 5, and the heterojunction upper layer 5 and the heterojunction lower layer 4 form the heterojunction 15. Specific steps: Preparation of substrate cleaning solution; place the silicon chip with conductive deep buried layer prepared in step 1 (including heterojunction lower layer 4, lower electrode 3 and intrinsic monocrystalline silicon substrate 2) in the cleaning solution, heat the cleaning solution to 80° C., hold the temperature for 10 min, take the silicon chip out, immerse it with conductive deep buried layer in acetone solution, ultrasonically clean it for 20 min, flush with deionized water and dry the silicon chip. Take and fill 20 mL of type-C vulcanizing agent into an empty bottle. Put the cleaned silicon chip with deep conductive layer in the bottle for 72 h, take it out and flush with deionized water and dry it. Put the vulcanized silicon chip with conductive deep buried layer as a substrate in a two-zone tubular vacuum atmosphere furnace, and hold the temperature at 400° C. for 1 h under the protection of Ar atmosphere, so as to volatilize excess vulcanizing agent. Then, take and put sulfur powder, MoO3 powder and substrate in three quartz containers respectively. Put the sulfur powder in the radiation zone outside the heating zone in the two-zone tubular vacuum atmosphere furnace, and sublimate it into the heating zone in the furnace after radiant heating. Put the key trioxide and substrate both in the heating zone, and keep the distance between the key trioxide and the substrate at 7 cm. Vacuumize two-zone tubular atmosphere furnace to 8.2 Pa, and feed Ar gas for protection, with flow rate of 800 sccm. The heating zone is divided into a first temperature zone and a second temperature zone. Set first temperature zone to 650° C., raise temperature for 1 h and hold temperature for 20 min, and set second temperature zone to 600° C., raise temperature for 1 h and hold temperature for 20 min. After that, naturally cool to room temperature to form molybdenum disulfide with an average thickness of 3 nm as the heterojunction upper layer 5. At this time, the heterojunction upper layer 5 and the heterojunction lower layer 4 together form the heterojunction 15.

[0063] Step 3: Etch the upper half of the through hole 6 on the heterojunction upper layer 5

[0064] As is shown in FIG. 3 (d), use AZ5214E photoresist and KW-4A mesa spin coater. Drop one or two drops of photoresist to the center of the silicon chip with the heterojunction upper layer 5, and then set rotating speed to 500/15 (rpm/s) at low speed and 4500/50 (rpm/s) at high speed, so that the photoresist is uniformly coated on the heterojunction upper layer 5. Adopt MIRAKTMT The molyne heating plate for pre-drying at 100° C. for 60 s. Expose the photoresist on Q4000 lithography machine. Use KMPPD238-II developing solution to develop the substrate. Etch silicon by reactive ions, set the reaction chamber pressure at 12 mTorr, ICP power at 500 W, oxygen flow rate at 5 sccm, and etching depth at 10 μm, that is, stop etching to the inside of the lower electrode 3, and use acetone to remove photoresist. At this time, a substrate with partial through hole 6 is formed.

[0065] Step 4: Preparing metal masking layer for deep silicon etching

[0066] Drop three to four drops of photoresist to the back center of the intrinsic monocrystalline silicon substrate 2, and set the rotating speed to coat photoresist uniformly on the silicon chip as a substrate. Adopt MIRAKTMT The molyne heating plate for pre-drying at 100° C. for 60 s. Put the substrate in SUSSMA6 double-sided exposure lithography machine, and expose the photoresist after alignment with the alignment mark of the pattern layer of through hole 6 on the front side. Perform reverse drying for the exposed photoresist, so that the photoresist in the exposure area is under crosslinking reaction and is insoluble in the developing solution. Put the substrate after reverse drying in flood exposure after removing the mask plate in the lithography machine, so that the photoresist in the unexposed area is under photosensitive reaction and can be dissolved in the developing solution. Set the time of flood exposure to 11 s. Use KMPPD238-II developing solution to develop the substrate. Put the developed substrate on a heating plate, set the temperature of the heating plate to 120° C., dry it for 20 min, take it out and cool it naturally to serve as the substrate in the next step. Use JPG560BV magnetron sputtering coating machine, select aluminum target with diameter of 100 mm, thickness of 7 mm and purity of 99.999%, set working gas of 99.99% chlorine gas and vacuum of 5.0×10.sup.−3 Pa. Place the substrate on the substrate holder, close the vacuum chamber door, and vacuumize, when the vacuum degree reaches 10.sup.−3 Pa, the background pressure of the vacuum chamber will reach 5.0×10.sup.−3 Pa. Introduce chlorine gas to make vacuum chamber pressure in working state. Turn on the power supply, and when the glow is stable, begin to deposit aluminum film on the back of the substrate (detector multilayer structure). After deposition for 20 min, turn off chlorine gas, wait for the vacuum chamber to cool to room temperature, then open the vacuum chamber, take out the plated sample, immerse it in acetone solution, and use stripping process to pattern the metal layer.

[0067] Step 5: Deeply etch the lower half of the through hole 6 and the opening 7

[0068] Etch the lower half of the through hole 6 and the opening 7 by low-temperature reactive ions. Set the substrate temperature at −110° C., when the reaction chamber pressure is 12 Torr, the ICP power is 500 W, and the oxygen flow rate is 5 sccm, start the deep etching of silicon with etching depth of 90 μm, that is, etch into the lower electrode 3 to connect the through hole 6 and etch the opening 7. The etching depth is the same for the two holes, and the opening 7 is a hole from the lower surface of the intrinsic monocrystalline silicon substrate 2 to the inside of the lower electrode 3. Finally, use acetone to remove photoresist and use phosphoric acid to remove aluminum.

[0069] Step 6: Prepare metal in the through hole 6 and the opening 7

[0070] As is shown in FIG. 3 (e), use PECVD is on the lower surface of intrinsic monocrystalline silicon substrate 2, and deposit silicon dioxide in through holes 6 as insulating layer 8 of the through hole, and deposit silicon dioxide in the opening 7 as hole insulating layer 9. And then repeat step 4 and pattern the metal layer by stripping process. That is, coat photoresist, perform exposing and developing, magnetron sputtering for any one of metal aluminum, gold, silver or copper, perform magnetron sputtering of aluminum film in the through hole 6 to form the first conductive metal column 10, and perform magnetron sputtering of aluminum film in the opening 7 to form the second conductive metal column 11. The first conductive metal column 10 and the second conductive metal column 11 are made of the same metal material. When magnetron sputtering aluminum, protrude the aluminum film from the surface of the intrinsic monocrystalline silicon substrate 2 to forming metal column from which the upper and lower electrode signals are led out to interconnect the detector signals with other chips by reverse chip bonding, as shown in FIG. 3 (f).

[0071] Step 7: Prepare metal frame at the upper end of the through hole 7

[0072] As is shown in FIG. 3 (g), repeat step 4 on the heterojunction upper layer 5 to pattern the metal layer by stripping process, that is, coat photoresist, perform exposure and developing, perform magnetron sputtering of metal aluminum film, deposit and form a metal frame 12 with a width of 3 μmλ3 μm and a thickness of 200 nm on the heterojunction upper layer 5, and then remove the photoresist to form a metal frame 12 connected with the metal 10 in the through hole.

[0073] Step 8: Prepare the upper electrode 13 of carbon nanotube grid

[0074] As is shown in FIG. 3 (h), mix carbon nanotubes and ethanol uniformly in ultrasonic manner to form a suspension, and pour the suspension onto the heterojunction upper layer 5, and after ethanol is volatilized, a carbon nanotube grid is formed to serve as the upper electrode 13.

[0075] Step 9: As is shown in FIG. 3 (i), prepare a 50 nm zinc sulfide passivation layer 14 by chemical vapor deposition.

[0076] Step 10: Etch the upper electrode, heterojunction and lower electrode

[0077] Pattern the passivation layer into a detection unit shape by photolithography and etching, use the patterned passivation layer 14 as a masking layer, etch the upper electrode 13, the heterojunction upper layer 5, the heterojunction lower layer 4 and the lower electrode 3 to form an infrared-transmitting high-sensitivity visible light detection unit array isolated from each other in the horizontal direction. Through the above steps, the infrared visible light detector structure is finally formed.

[0078] Although the present invention has been illustrated and described herein with reference to preferred embodiments, it should not be construed as limiting the scope of the invention. Any modifications, equivalent substitutions or improvements that are within the spirit and principle of the invention are intended to be covered by the protection scope of the invention.