DYNAMIC D FLIP-FLOP, DATA OPERATION UNIT, CHIP, HASH BOARD AND COMPUTING DEVICE

Abstract

The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Claims

1. A dynamic latch cell, comprising: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; the latch unit and the output driving unit being sequentially connected in series between the input terminal and the output terminal; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal.

2. The dynamic latch cell according to claim 1, wherein the latch unit is a three-state inverter.

3. The dynamic latch cell according to claim 2, wherein the three-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor sequentially connected in series between a power supply and ground.

4. The dynamic latch cell according to claim 3, wherein the first PMOS transistor and the second NMOS transistor perform switch control according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

5. The dynamic latch cell according to claim 3, wherein the second PMOS transistor and the first NMOS transistor perform switch control according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

6. The dynamic latch cell according to claim 1, wherein the latch unit uses low leakage devices and/or the output driving unit uses high threshold voltage devices.

7. The dynamic latch cell according to claim 3, wherein the first NMOS transistor and the second NMOS transistor use low leakage current transistors.

8. The dynamic latch cell according to claim 1, further comprising a positive feedback unit for inverting data of the output terminal and feeding the data to the output driving unit.

9. The dynamic latch cell according to claim 8, wherein the positive feedback unit is an inverter connected in antiparallel to both ends of the output driving unit.

10. A dynamic D flip-flop, comprising two dynamic latch cells according to claim 1, wherein the two dynamic latch cells are connected in series.

11. A data operation unit, comprising a control circuit, an operational circuit and a plurality of dynamic D flip-flops interconnected with each other, the plurality of dynamic D flip-flops being connected in series and/or in parallel, wherein the plurality of dynamic D flip-flops are the dynamic D flip-flop according to claim 10.

12. A chip, comprising the data operation unit according to claim 11.

13. A hash board for a computing device, comprising the chip according to claim 12.

14. A computing device, comprising a power supply board, a control board, a connection board, a radiator and a plurality of hash boards, the control board connected to the hash boards through the connection board, the radiator provided around the hash boards, and the power supply board configured to supply a power supply for the connection board, the control board, the radiator and the hash boards, wherein the hash board is the hash board according to claim 13.

15. A dynamic D flip-flop, comprising: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and the first latch unit, the second latch unit being sequentially connected in series between the input terminal and the output terminal; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal; the data output by the output terminal is inverse to the data input from the input terminal.

16. The dynamic D flip-flop according to claim 15, wherein the second latch unit is a three-state inverter.

17. The dynamic D flip-flop according to claim 16, wherein the three-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor sequentially connected in series between a power supply and ground.

18. The dynamic D flip-flop according to claim 17, wherein the first PMOS transistor and the second NMOS transistor perform switch control according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

19. The dynamic D flip-flop according to claim 17, wherein the second PMOS transistor and the first NMOS transistor perform switch control according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

20. The dynamic D flip-flop according to claim 17, wherein the first NMOS transistor and the second NMOS transistor use low leakage current transistors.

21. The dynamic D flip-flop according to claim 15, wherein the first latch unit uses a delay unit.

22. The dynamic D flip-flop according to claim 21, wherein the clock signal terminal is connected with a clock buffer using low threshold units.

23. The dynamic D flip-flop according to claim 15, wherein a plurality of dynamic D flip-flops are connected in parallel.

24. A data operation unit, comprising a control circuit, an operational circuit and a plurality of dynamic D flip-flops interconnected with each other, the plurality of dynamic D flip-flops being connected in series and/or in parallel, wherein the plurality of dynamic D flip-flops are the dynamic D flip-flop according to claim 15.

25. A chip, comprising the data operation unit according to claim 24.

26. A hash board for a computing device, comprising the chip according to claim 25.

27. A computing device, comprising a power supply board, a control board, a connection board, a radiator and a plurality of hash boards, the control board connected to the hash boards through the connection board, the radiator provided around the hash boards, and the power supply board configured to supply a power supply for the connection board, the control board, the radiator and the hash boards, wherein the hash board is the hash board according to claim 26.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 is a schematic diagram of a positive feedback D flip-flop in the prior art.

[0042] FIG. 2 is a schematic diagram of a dynamic D flip-flop in the prior art.

[0043] FIG. 3 is a schematic diagram of a dynamic D flip-flop according to the invention.

[0044] FIG. 4A is a circuit diagram of a dynamic D flip-flop in one embodiment of the invention.

[0045] FIG. 4B is a circuit diagram of a dynamic D flip-flop in another embodiment of the invention.

[0046] FIG. 4C is a circuit diagram of a variable embodiment of the dynamic D flip-flop of FIG. 4A.

[0047] FIG. 4D is a circuit diagram of a variable embodiment of the dynamic D flip-flop of FIG. 4B.

[0048] FIG. 5A is an equivalent circuit diagram when the dynamic D flip-flop of the invention writes data.

[0049] FIG. 5B is an equivalent circuit diagram when data of the dynamic D flip-flop of the invention are in a holding state.

[0050] FIG. 6 is a timing diagram of the dynamic D flip-flop according to the invention.

[0051] FIG. 7 is a schematic diagram of a data operation unit according to the invention.

[0052] FIG. 8 is a schematic diagram of a chip according to the invention.

[0053] FIG. 9 is a schematic diagram of a hash board according to the invention.

[0054] FIG. 10 is a schematic diagram of a computing device according to the invention.

PREFERABLE EMBODIMENTS OF THE INVENTION

[0055] Hereinafter structure principle and working principle of the invention are described in detail with reference to the accompanying drawings.

[0056] FIG. 3 is a schematic diagram of a dynamic D flip-flop according to the invention. Referring to FIG. 3, the dynamic D flip-flop 400 is formed of a first latch unit 401, a second latch unit 402 and an output driving unit 403. The first latch unit 401, the second latch unit 402 and the output driving unit 403 are sequentially connected in series between an input terminal 404 and an output terminal 405 of the dynamic D flip-flop 400.

Embodiment One

[0057] FIG. 4A is a circuit diagram of a dynamic D flip-flop in one embodiment of the invention.

[0058] Referring to FIG. 3, as shown in FIG. 4A, a first latch unit 401 of the dynamic D flip-flop 500 is a transmission gate 501, and the transmission gate 501 forms an analog switch under control of clock signals using parallel connection of a PMOS transistor 506 and a NMOS transistor 507. One end of the transmission gate 501 is connected to an input terminal 504 of the dynamic D flip-flop 500, a gate terminal 508 of the PMOS transistor 506 is controlled by a clock signal CLKP, and a gate terminal 509 of the NMOS transistor 507 is controlled by a clock signal CLKN in opposite phase with CLKP. When CLKP is a high level, CLKN is a low level, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are turned off, the transmission gate 501 is closed, and data of the input terminal 504 cannot be transmitted to the other end of the transmission gate 501, such that data at a first node 550 of the other end of the transmission gate 501 are latched to hold an original state. When CLKP is a low level, CLKN is a high level, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are turned on, the transmission gate 501 is open, and data of the input terminal 504 can be transmitted to the other end of the transmission gate 501 through the transmission gate 501, such that data at the first node 550 are rewritten to the same data as that of the input terminal 504.

[0059] Referring to FIG. 3, as shown in FIG. 4A, a second latch unit 402 of the dynamic D flip-flop 500 is a three-state inverter 502, and the three-state inverter 502 comprises PMOS transistors 510, 511 and NMOS transistors 512, 513. The NMOS transistors 512, 513 are low leakage devices. Gate electrodes of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form an input terminal of the three-state inverter 502. A source electrode of the PMOS transistor 510 is connected to a power supply VDD, and a source electrode of the NMOS transistor 513 is connected to ground GND. Drain electrodes of the PMOS transistor 511 and the NMOS transistor 512 are connected together to form an output terminal of the three-state inverter 502. A source electrode of the PMOS transistor 511 is connected to a drain electrode of the PMOS transistor 510, and a source electrode of the NMOS transistor 512 is connected to a drain electrode of the NMOS transistor 513.

[0060] A gate terminal 514 of the PMOS transistor 510 is controlled by the clock signal CLKN, and a gate terminal 515 of the NMOS transistor 513 is controlled by the clock signal CLKP as clock control terminals of the three-state inverter 502.

[0061] When CLKP is a low level, CLKN is a high level, the PMOS transistor 510 and the NMOS transistor 513 are both in a turn-off state, and the three-state inverter 502 is in a high impedance state, such that data at the first node 550 cannot pass through the three-state inverter 502, and data at a second node 551 are latched to hold the original state, thereby functioning as a data register.

[0062] When CLKP is a high level, CLKN is a low level, the PMOS transistor 510 and the NMOS transistor 513 are both in a turn-on state, the three-state inverter 502 functions to invert data of the input terminal, such that data at the first node 550 are inverted and outputted to the second node 551 to rewrite the data at the second node 551.

[0063] Referring to FIG. 3, as shown in FIG. 4A, an output driving unit 403 is an inverter 503 for inverting the data received from the three-state inverter 502 again, so as to form data in the same phase with the data of the input terminal 504 of the dynamic D flip-flop, and output the data through an output terminal 505. Meanwhile, the output driving unit 403 also can improve driving capability of data, and the inverter 503 uses high threshold voltage devices.

Embodiment Two

[0064] Referring to FIG. 3, as shown in FIG. 4B, a first latch unit 401 of a dynamic D flip-flop 600 is a transmission gate 601, and the transmission gate 601 forms an analog switch under control of clock signals using parallel connection of a PMOS transistor 606 and a NMOS transistor 607. One end of the transmission gate 601 is connected to an input terminal 604 of the dynamic D flip-flop 600, a gate terminal 608 of the PMOS transistor 606 is controlled by a clock signal CLKP, and a gate terminal 609 of the NMOS transistor 607 is controlled by a clock signal CLKN in opposite phase with CLKP. When CLKP is a high level, CLKN is a low level, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are turned off, the transmission gate is closed, and data of the input terminal 604 cannot be transmitted to the other end of the transmission gate 601, such that data at a first node 650 are latched to hold an original state. When CLKP is a low level, CLKN is a high level, the PMOS transistor 606 and the NMOS transistor 607 of the transmission gate 601 are turned on, the transmission gate 601 is open, and data of the input terminal 604 are outputted to the other end through the transmission gate 601, such that data at the first node 650 are rewritten to the same data as that of the input terminal 604.

[0065] Referring to FIG. 3, as shown in FIG. 4B, a second latch unit 402 of the dynamic D flip-flop 600 is a three-state inverter 602, and the three-state inverter 602 comprises PMOS transistors 610, 611 and NMOS transistors 612, 613. The NMOS transistors 612, 613 are low leakage devices. Gate electrodes of the PMOS transistor 611 and the NMOS transistor 613 are connected together to form an input terminal of the three-state inverter 602. A source electrode of the PMOS transistor 610 is connected to a power supply VDD, and a source electrode of the NMOS transistor 613 is connected to ground GND. Drain electrodes of the PMOS transistor 611 and the NMOS transistor 612 are connected together to form an output terminal of the three-state inverter 602. A source electrode of the PMOS transistor 611 is connected to a drain electrode of the PMOS transistor 610, and a source electrode of the NMOS transistor 612 is connected to a drain electrode of the NMOS transistor 613.

[0066] A gate terminal 614 of the PMOS transistor 611 is controlled by the clock signal CLKN, and a gate terminal 615 of the NMOS transistor 612 is controlled by the clock signal CLKP as clock control terminals of the three-state inverter 602.

[0067] When CLKP is a low level, CLKN is a high level, the PMOS transistor 611 and the NMOS transistor 612 are both in a turn-off state, and the three-state inverter 602 is in a high impedance state, such that data at the first node 650 cannot pass through the three-state inverter 602, and data at a second node 651 are latched to hold the original state, thereby functioning as a data register.

[0068] When CLKP is a high level, CLKN is a low level, the PMOS transistor 611 and the NMOS transistor 612 are both in a turn-on state, the three-state inverter 602 functions to invert data of the input terminal, such that data at the first node 650 are inverted and outputted to the second node 651 to rewrite the data at the second node 651.

[0069] Referring to FIG. 3, as shown in FIG. 4B, an output driving unit 403 is an inverter 603 for inverting the data received from the three-state inverter 602 again, so as to form data in the same phase with the data of the input terminal 604 of the dynamic D flip-flop, and output the data through an output terminal 605. Meanwhile, the output driving unit 403 also can improve driving capability of data, and the inverter 603 uses high threshold voltage devices.

Variable Embodiment One

[0070] FIG. 4C is a circuit diagram of a variable embodiment of the dynamic D flip-flop of FIG. 4A. Referring to FIG. 3, FIG. 4C differs from the embodiment of FIG. 4A in that the dynamic D flip-flop of FIG. 4C further comprises a positive feedback unit connected in parallel to both ends of the output driving unit 403. In this variable embodiment, the positive feedback unit is, such as, an inverter 518 consisting of a PMOS transistor 516 and a NMOS transistor 517, an input terminal of the inverter 518 is connected to an output terminal of the inverter 503, i.e., the output terminal 505 of the positive feedback dynamic D flip-flop 500, and an output terminal of the inverter 518 is connected to an input terminal of the inverter 503. When data at the second node 551 are “1”, an output of the inverter 503 is “0”, the PMOS transistor 516 is turned on to form a pull-up path to hold the data at the second node 551 to be “1”. When the data at the second node 551 are “0”, an output of the inverter 503 is “1”, the NMOS transistor 517 is turned on to form a pull-down path to hold the data at the second node 551 to be “0”. As can be seen, the inverters 518 and 503 form a data latch loop for better latching data of the output terminal 505 of the positive feedback dynamic D flip-flop at the second node 551. In addition, a feedback loop consisting of the PMOS transistor 516 and the NMOS transistor 517 shall have a worse current capacity than a normal reading and writing path, such that new data can be written correctly.

Variable Embodiment Two

[0071] FIG. 4D is a circuit diagram of a variable embodiment of the dynamic D flip-flop of FIG. 4B. Referring to FIG. 3, FIG. 4D differs from the embodiment of FIG. 4B in that the dynamic D flip-flop of FIG. 4D further comprises a positive feedback unit connected in parallel to both ends of the output driving unit 403. In this variable embodiment, the positive feedback unit is, such as, an inverter 618 consisting of a PMOS transistor 616 and a NMOS transistor 617, an input terminal of the inverter 618 is connected to an output terminal of the inverter 603, i.e., the output terminal 605 of the positive feedback dynamic D flip-flop 600, and an output terminal of the inverter 618 is connected to an input terminal of the inverter 603. When data at the second node 651 are “1”, an output of the inverter 603 is “0”, the PMOS transistor 616 is turned on to form a pull-up path to hold the data at the second node 651 to be “1”. When the data at the second node 651 are “0”, an output of the inverter 603 is “1”, the NMOS transistor 617 is turned on to form a pull-down path to hold the data at the second node 651 to be “0”. As can be seen, the inverters 618 and 603 form a data latch loop for better latching data of the output terminal 605 of the positive feedback dynamic D flip-flop at the second node 651. In addition, a feedback loop consisting of the PMOS transistor 616 and the NMOS transistor 617 shall have a worse current capacity than a normal reading and writing path, such that new data can be written correctly.

[0072] In addition, as for the dynamic D flip-flops shown in FIGS. 4A-4D, the clock signals CLKP and CLKN can be directly connected to the clock signals, and also can be supplied by a clock buffer. When the clock signals CLKP and CLKN are supplied by a clock buffer, the first latch units 401 of the dynamic D flip-flops, i.e., the transmission gates 501 and 601, are designed by a delay unit. Speed is reduced by using high threshold devices, electric leakage and transmission speed are reduced by using a small size, and transmission speed is slowed by using layout of parasitic resistor and capacitor, such that holding time of the dynamic D flip-flops can be reduced. Alternatively, the clock buffer of the dynamic D flip-flops is designed by a high speed unit, and comprises at least one cascaded clock buffer unit. Driving capability is strengthened by using low threshold voltage devices and increasing size of the devices. Driving balance between loads is balanced, and an overall driving speed is improved using the scheme of reasonably distributing clock delay, thereby reducing holding time of the dynamic D flip-flops.

[0073] It shall be noted that the dynamic D flip-flops shown in FIGS. 4A-4D also can be applied in multi-parallel connection. Each of the dynamic D flip-flops comprises an input terminal and an output terminal, and receives external clock signals through the clock buffer, and the clock signals CLKP and CLKN are supplied to each dynamic D flip-flop after the clock signals are buffered.

[0074] Hereinafter working principle of the dynamic D flip-flop according to the invention is explained in details.

[0075] FIG. 5A is an equivalent circuit diagram when the dynamic D flip-flop of the invention writes data, and FIG. 5B is an equivalent circuit diagram when data of the dynamic D flip-flop of the invention are in a holding state.

[0076] As shown in FIGS. 4A, 4B, 4C, 4D and 5A, when CLKP is a high level and CLKN is a low level, the transistors controlled by the clock in the three-state inverters 502 and 602 are turned on, and data transmitted from the transmission gates 501 and 601 are written into a parasitic capacitor 100. When input data are “0”, the PMOS transistors 510, 511, 610 and 611 of the three-state inverters 502 and 602 are in a turn-on state to form pull-up paths to charge the parasitic capacitor 100, the second nodes 551 and 651 become a high level, and data are changed to “1”. When input data are “1”, the NMOS transistors 512, 513, 612 and 613 of the three-state inverters 502 and 602 are in a turn-on state to form pull-down paths to discharge the parasitic capacitor 100, the second nodes 551 and 651 become a low level, and data are changed to “0”.

[0077] As shown in FIG. 5B, when the parasitic capacitor 100 is charged, if the three-state inverters 502 and 602 are in a high impedance state under control of the clock signals, the parasitic capacitor 100 is not further charged, and data at the second nodes 551 and 651 are in a holding state. On the other hand, due to influence of a leakage current of the NMOS transistors 512, 513, 612 and 613, electric charge on the parasitic capacitor 100 is gradually leaked, the high level on the second nodes 551 and 651 is inverted to a low level after a certain time length, and data registered in the parasitic capacitor 100 are changed from “1” to “0”, finally causing data error.

[0078] Assuming that the electric charge produced on the parasitic capacitor 100 is Q, a capacitance of the parasitic capacitor 100 is C, and a voltage at both ends of a polar plate of the parasitic capacitor is V,

[00001]$Q=C*V.$

[0079] If the leakage current is Ileakage, a leakage time t is:

[00002]$t=Q\text{/}\mathrm{Ileakage}=C*V\text{/}\mathrm{Ile}\mathrm{akage}.$

[0080] In current production process, data stored in the parasitic capacitor 100 can be held for about 5 ns. In other words, if the data stored in the parasitic capacitor are updated periodically during data holding, the circumstance of data error won't occur. A working frequency of the current computing device is often above 500 MHz which far exceeds a desired data update frequency, such that the dynamic D flip-flop of the invention can be applied in the computing device, thereby reducing an error rate of an operation result of the computing device, and improving processing performance of a virtual currency operation device.

[0081] On the other hand, due to influence of leakage current, the electric charge stored on the parasitic capacitor 100 is gradually decreased, such that voltages at the second nodes 551 and 651 that shall be originally a high level are gradually reduced, and the voltages at the second nodes 551 and 651, serving as inputs of the inverters 503 and 603, cause the inverters 503 and 603 in a subthreshold turn-on state. The inverters 503 and 603 in the subthreshold turn-on state form a direct current discharge path directly from the power supply VDD to the ground GND, causing a sharp increase in power consumption.

[0082] Since the NMOS transistors 512, 513, 612 and 613 of the three-state inverters 502, 602 use the low leakage devices, and the inverters 503 and 603 use the high threshold voltage devices, the dynamic D flip-flops 500 and 600 of the invention can effectively reduce the leakage current on the NMOS transistors 512, 513, 612 and 613, and possibility of the inverters 503 and 603 working in a subthreshold interval, thereby reducing power consumption of the dynamic D flip-flops. The manners of low leakage devices and high threshold voltage devices can be used separately, and also can be used simultaneously.

[0083] In addition, as for the dynamic D flip-flops having the positive feedback unit, due to positive feedback function of the inverters 518 and 618, data stored on the parasitic capacitor 100 can be held normally till the data are rewritten by new data. Therefore, it is unnecessary to periodically update the data stored on the parasitic capacitor during data holding, and the circumstance of data error also won't occur.

[0084] FIG. 6 is a timing diagram of the dynamic D flip-flop according to the invention. As shown in FIG. 6, when CLKP is a low level, and CLKN is a high level, the first latch unit is turned on, such that data of an input terminal D pass through the first latch unit, and the second latch unit is turned off to hold an output of the dynamic D flip-flop in the original state. When a rising edge of CLKP comes, CLKP is jumped to a high level, and CLKN is jumped to a low level, the first latch unit is turned off to cut off data input of the input terminal D, and the second latch unit is turned on to output the held data of the input terminal D through an output terminal Q. As can be seen, when variation of states of the output terminal of the dynamic D flip-flop in the invention occurs as the rising edge of the clock signal CLKP comes, CLKP is a high level, and CLKN is a low level, and an output state is held unchanged.

[0085] The invention further provides a data operation unit, and FIG. 7 is a schematic diagram of a data operation unit according to the invention. As shown in FIG. 7, the data operation unit 700 comprises a control circuit 701, an operational circuit 702 and a plurality of dynamic D flip-flops 500, 600. The control circuit 701 refreshes data in the dynamic D flip-flops 500, 600, and reads data from the dynamic D flip-flops 500, 600. The operational circuit 702 performs operation on the read data, and then the operation result is outputted by the control circuit 701.

[0086] The invention further provides a chip, and FIG. 8 is a schematic diagram of a chip according to the invention. As shown in FIG. 8, the chip 800 comprises a control unit 801 and one or more data operation units 700. The control unit 801 inputs data into the data operation units 700, and processes data outputted from the data operation units 700.

[0087] The invention further provides a hash board, and FIG. 9 is a schematic diagram of a hash board according to the invention. As shown in FIG. 9, each of the hash boards 900 comprises one or more chips 800 to perform hash operation on working data sent downstream from a mining pool.

[0088] The invention further provides a computing device, and the computing device is preferably configured to operation of mining virtual digital currency. Of course, the computing device also can be configured to any other massive operations, and FIG. 10 is a schematic diagram of a computing device according to the invention. As shown in FIG. 10, each of the computing devices 1000 comprises a connection board 1001, a control board 1002, a radiator 1003, a power supply plate 1004 and one or more hash boards 900. The control board 1002 is connected to the hash boards 900 through the connection board 1001, and the radiator 1003 is provided around the hash boards 900. The power supply plate 1004 is configured to supply a power supply to the connection board 1001, the control board 1002, the radiator 1003 and the hash boards 900.

[0089] It shall be noted that in the invention, orientation or positional relationship indicated by the terms “transverse”, “longitudinal”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “in”, “out”, and the like is the orientation or positional relationship illustrated by the drawings, and is only for the purpose of describing the invention and simplifying the explanation, rather than indicating or suggesting that the referred device or element must have specific orientation, and be constructed and operated in specific orientation, so it shall not be understood as limits to the invention.

[0090] Although the embodiments of the invention have been disclosed above, they can be fully applied to various fields suitable for the invention but not as limits to those listed in the specification and the embodiments. For those skilled in the art, additional modifications can be easily implemented, so without departing from general concepts defined by the appended claims and equivalent scopes, the invention is not limited to specific details and figures illustrated and described here.

[0091] In other words, the invention also may have various other embodiments, and those skilled in the art shall make various corresponding modifications and variations according to the invention without departing from spirit and essence of the invention, but these corresponding modifications and variations shall belong to the scope protected by the appended claims of the invention.

INDUSTRIAL APPLICABILITY

[0092] Application of the dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same of the invention has the following advantageous effects:

[0093] can reduce approximately 30% of the chip area, power consumption and logic delay, thereby reducing production cost of the chip, and increasing product competitiveness. In terms of expanding, such dynamic D flip-flop can replace a D flip-flop in digital logic to simplify wiring process of the back-end layout, reduce design difficulty, and improve performance, thereby obtaining an advantage of area, and increasing practicability.