Power MOSFET and JBSFET cell topologies with superior high frequency figure of merit

Abstract

A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

Claims

1. A vertical insulated-gate field effect transistor, comprising: a semiconductor substrate; a gate electrode on a first surface of said semiconductor substrate, said gate electrode having an at least eight-sided opening extending therethrough, which defines at least eight sidewalls thereof, said at least eight sidewalls comprising a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening; and a source electrode extending into the opening in said gate electrode.

2. The transistor of claim 1, wherein said semiconductor substrate comprises a base region therein extending opposite said gate electrode; and wherein said source electrode is electrically connected to the base region.

3. The transistor of claim 1, further comprising a drain electrode on a second surface of said semiconductor substrate, which extends opposite the first surface.

4. The transistor of claim 1, wherein all of the at least eight sidewalls are flat relative to the center of the opening.

5. The transistor of claim 4, wherein the at least eight-sided opening is in the shape of an octagon.

6. The transistor of claim 1, wherein said gate electrode comprises a quad-arrangement of four generally octagon-shaped gate electrode regions electrically coupled together by four generally rectangular-shaped gate electrode regions.

7. The transistor of claim 6, wherein the at least eight-sided opening is in the shape of an octagon.

8. The transistor of claim 6, wherein the at least eight-sided opening includes four flat sidewalls having a first length and four flat sidewalls having a second length unequal to the first length.

9. The transistor of claim 1, wherein the insulated-gate field effect transistor is a JBSFET.

10. The transistor of claim 9, wherein the JBSFET comprises a Schottky rectifying contact within the at least eight-sided opening.

11. A vertical insulated-gate field effect transistor, comprising: a semiconductor substrate; a gate electrode on a first surface of said semiconductor substrate, said gate electrode having an at least eight-sided opening extending therethrough, which defines at least eight sidewalls thereof that are flat or concave relative to a center of the opening; and a source electrode extending into the opening in said gate electrode.

12. The transistor of claim 11, wherein the at least eight sidewalls includes a plurality of arcuate-shaped sidewalls, which are concave relative to the center of the opening.

13. The transistor of claim 12, wherein centers of the plurality of arcuate-shaped sidewalls are spaced-apart from the center of the opening.

14. The transistor of claim 12, wherein the at least eight sidewalls includes a plurality of flat sidewalls.

15. The transistor of claim 11, wherein the at least eight sidewalls have equivalent lengths.

16. The transistor of claim 11, wherein the at least eight-sided opening is an octagonal-shaped opening.

17. The transistor of claim 16, wherein the insulated-gate field effect transistor is a JBSFET having a four-sided Schottky rectifying contact within the octagonal-shaped opening.

18. The transistor of claim 11, wherein the insulated-gate field effect transistor is a JBSFET having a Schottky rectifying contact within the at least eight-sided opening.

19. The transistor of claim 11, wherein said semiconductor substrate comprises a source region of first conductivity type extending adjacent the first surface thereof; and wherein a portion of said source electrode in the opening forms an ohmic contact with the source region.

20. The transistor of claim 19, wherein said semiconductor substrate comprises a base region of second conductivity type therein, which extends opposite said gate electrode and forms a P—N rectifying junction with the source region; and wherein said source electrode is electrically connected to the base region.

21. The transistor of claim 11, further comprising a drain electrode on a second surface of said semiconductor substrate, which extends opposite the first surface.

22. A silicon carbide power device, comprising: a semiconductor substrate; a two-dimensional (2D) array of vertical insulated-gate field effect transistor unit cells (IGFETs) in said semiconductor substrate, said 2D array of IGFETs having a contiguous gate electrode that spans the IGFETs therein, with each of said IGFETs having: (i) a lateral rectangular dimension of L×W, and (ii) a corresponding at least eight-sided opening extending through the contiguous gate electrode, where L is a length of an IGFET and W is a width of an IGFET as measured along a surface of said semiconductor substrate, and where each sidewall of each at least eight-sided opening is flat or concave relative to a center of its corresponding opening; and a source electrode extending into the openings in the contiguous gate electrode.

23. The power device of claim 22, wherein an area (A) of each of the openings in the contiguous gate electrodes is equivalent to: 0.1(L×W)≤A≤0.3(L×W).

24. The power device of claim 23, wherein the IGFETs are configured as JBSFETs; and wherein an area (A) of each of the openings in the contiguous gate electrodes is equivalent to: 0.1(L×W)≤A≤0.3(L×W).

25. A monolithically-integrated AC switch, comprising: a semiconductor substrate having first and second insulated-gate field effect transistors therein, which comprise: first and second spaced-apart and independently-controllable source terminals extending adjacent a first surface of said semiconductor substrate; a common drain electrode extending adjacent a second surface of said semiconductor substrate; and first and second gate electrodes on the first surface of said semiconductor substrate, said first gate electrode having an at least eight-sided first opening extending therethrough, which receives a portion of said first source terminal therein, said at least eight-sided first opening defined by at least eight sidewalls that are flat or concave relative to a center of the first opening.

26. The AC switch of claim 25, wherein said second gate electrode has an at least eight-sided second opening extending therethrough, which receives a portion of said second source terminal therein; and wherein the second opening in said second gate electrode is defined by at least eight sidewalls that are flat or concave relative to a center of the second opening.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having a linear window in linear array topology, according to the prior art.

(2) FIG. 1B is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having a square window in square array topology, according to the prior art.

(3) FIG. 1C is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having a circular window in square array topology, according to the prior art.

(4) FIG. 1D is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having a hexagonal window in square array topology, according to the prior art.

(5) FIG. 1E is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having a hexagonal window in hexagonal array topology, according to the prior art.

(6) FIG. 1F is a plan view of a portion of a planar-gate silicon carbide (SiC) MOSFET having an atomic lattice layout (ALL) topology, according to the prior art.

(7) FIG. 2A is a plan view of a portion of a planar-gate field effect transistor according to an embodiment of the invention.

(8) FIG. 2B is a plan view of highlighted portion of the planar-gate field effect transistor of FIG. 2A, including a unit cell therein.

(9) FIG. 2C is a cross-sectional view of the planar-gate field effect transistor of FIG. 2B, taken along line 2C-2C′.

(10) FIG. 2D is a cross-sectional view of the planar-gate field effect transistor of FIG. 2B, taken along line 2D-2D′.

(11) FIG. 3A is a plan view of planar-gate JBSFET, according to an embodiment of the present invention.

(12) FIG. 3B is a cross-sectional view of the planar-gate JBSFET of FIG. 3A, taken along line 3B-3B′.

(13) FIG. 3C is a cross-sectional view of the planar-gate JBSFET of FIG. 3A, taken along line 3C-3C′.

DETAILED DESCRIPTION OF EMBODIMENTS

(14) The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

(15) It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

(16) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.

(17) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(18) Referring now to FIGS. 2A-2B, a plan view of a “corner” portion of a planar-gate field effect transistor 20 (e.g., SiC power MOSFET) for high current/power applications is illustrated as including a two-dimensional array of unit cells 20′ therein having a shared planar gate electrode 22 (e.g., polysilicon) on a primary surface (e.g., top surface) of an underlying semiconductor substrate (e.g., semiconductor chip). This two-dimensional array of unit cells 20′ is surrounded by an edge termination region 28 (e.g., P+ surface termination diffusion region), which typically extends adjacent a four-sided outer periphery of the semiconductor substrate.

(19) As highlighted, each unit cell 20′ has a rectangular shape (width=W, length=L) and includes a corresponding gate electrode “cell” region having a single centrally-located opening 21 therein. Each opening 21 may be an eight (or more) sided opening 21 defined by a corresponding eight (or more) gate electrode sidewalls 25 (e.g., polysilicon sidewalls). Each of these sidewalls 25 may be flat in plan view, as shown, or possibly concave relative to a corresponding center of an opening 21 as shown by dotted line arcs in FIGS. 2B and 3A. Accordingly, one or more of the sidewalls 25 of the opening 21 may be a flat/planar sidewall and one or more of the sidewalls may be a concave-shaped arc, with each concave-shaped arc having a respective radius of curvature about a respective center, which is offset relative to a center of the opening 21. Thus, the sidewalls 25 may include exclusively flat or exclusively concave sidewalls, or various combinations of eight or more flat and concave sidewalls of varying lengths. In addition, when viewed from a plan perspective (i.e., top-down layout perspective), each sidewall of an opening 21 intersects two adjacent sidewalls at respective vertices, such that two immediately adjacent flat sidewalls, if present, are not collinear, and two immediately adjacent concave sidewalls, if present, do not lie within a continuous arc extending through a connecting vertex. Thus, as illustrated and described herein, each sidewall of an opening 21 (21′), whether flat or concave, intersects two immediately adjacent sidewalls at respective vertices when the sidewalls are viewed from a plan perspective.

(20) As further shown by FIGS. 2A-2B, each opening 21 within the shared planar gate electrode 22 includes a corresponding contact window 26 (e.g., source metal contact window), which is spaced from the sidewalls 25 of each opening 21 by a distance corresponding to a thickness of each sidewall insulating spacer (e.g., dielectric sidewall spacer), as illustrated more fully hereinbelow by FIG. 2D. In addition, within each contact window 26, reference numeral 24 specifies the rectangular dimensions of a boundary between a P+ plug and a surrounding N+ source, as shown by FIG. 2D. The lateral dimensions of the N+ source regions and P-base regions are also identified by reference numerals 27 and 23, respectively, as shown by the transistor unit cell cross-sections of FIGS. 2C-2D. As will be understood by those skilled in the art, reference numeral 23 identifies a masking boundary for ion implantation of the P-base and P+ shielding regions and reference numeral 27 identifies the masking boundary for the ion implantation of the N+ source region.

(21) In particular, FIG. 2C is a cross-sectional view 20″ of the transistor unit cell 20′ taken along line 2C-2C′ and FIG. 2D is a cross-sectional view 20′″ of the transistor unit cell 20′ taken along line 2D-2D′. As shown by these figures, a semiconductor substrate is illustrated as including a conventional arrangement of a relatively lightly-doped (e.g., N−) semiconductor drift region on a relatively highly doped (e.g., N+) substrate layer. This substrate has an upper surface on which an insulated gate electrode and source electrode (i.e., source metal) are provided and a lower surface on which a drain electrode is provided. Multiple regions of N-type and P-type conductivity are formed in the drift region, adjacent the upper surface of the substrate. As illustrated, these regions include an JFET “neck” region (N-type), a highly doped P-type shielding region, and a P-base, N+ source and P+ plug on the shielding region. As will be understood by those skilled in the art, the vertical P+ plug provides a low resistance electrical connection between the shielding region and the source electrode.

(22) Referring now to FIGS. 3A-3C, a plan view of a planar-gate junction barrier Schottky field effect transistor (JBSFET) is illustrated as including a unit cell 30 having a planar gate electrode 22′ (e.g., polysilicon) on a primary surface (e.g., top surface) of an underlying semiconductor substrate (e.g., semiconductor chip). This planar gate electrode 22′ is illustrated as including four generally octagon-shaped gate electrode regions, which are electrically connected together by four generally rectangular-shaped gate electrode “connecting” regions. As will be understood by those skilled in the art, this unit cell 30 may be substituted for the unit cell 20′ illustrated by FIG. 2A to thereby define a two-dimensional array of unit cells 30 within a planar-gate JBSFET for high current/power applications.

(23) As highlighted, each unit cell 30 has a rectangular shape (width=W, length=L) and includes a corresponding gate electrode “cell” region having a single centrally-located opening 21′ therein. Each opening 21′ may be an eight (or more) sided opening 21′ defined by a corresponding eight (or more) gate electrode sidewalls 25 (e.g., polysilicon sidewalls). Each of these sidewalls 25 may be flat in plan view, as shown in FIG. 3A, or concave relative to a corresponding center of an opening 21′. Accordingly, one or more of the sidewalls 25 of the opening 21′ may be a flat/planar sidewall and one or more of the sidewalls may be a concave-shaped arc, with each concave-shaped arc having a respective radius of curvature about a respective center, which is offset relative to a center of the opening 21′. Thus, the sidewalls 25 may include exclusively flat or exclusively concave sidewalls, or various combinations of eight or more flat and concave sidewalls of varying lengths.

(24) As further shown by FIGS. 3A-3C, each opening 21′ within the shared planar gate electrode 22′ includes a corresponding contact window 26 (e.g., source metal contact window), which is spaced from the sidewalls 25 of each opening 21′ by a distance corresponding to a thickness of each sidewall insulating spacer (e.g., dielectric sidewall spacer), as illustrated more fully hereinbelow by FIG. 3C. In addition, within each contact window 26, reference numeral 24′ specifies the rectangular dimensions of a boundary between a P+ plug and a surrounding N+ source, whereas reference numeral 31 defines the lateral dimensions of a Schottky rectifying contact between the source metal and the underlying N-type drift region, as shown by FIGS. 3A and 3C. These lateral dimensions of the Schottky rectifying contact can be varied to obtain a desired on-state voltage drop and low leakage current. The lateral dimensions of the N+ source regions and P-base regions are also identified by reference numerals 27 and 23, respectively, as shown by the transistor unit cell cross-sections of FIGS. 3B-3C.

(25) In particular, FIG. 3B is a cross-sectional view 30′ of the transistor unit cell 30 taken along line 3B-3B′ and FIG. 3C is a cross-sectional view 30″ of the transistor unit cell 30 taken along line 3C-3C′. As shown by these figures, a semiconductor substrate is illustrated as including a conventional arrangement of a relatively lightly-doped (e.g., N−) semiconductor drift region on a relatively highly doped (e.g., N+) substrate layer. This substrate has an upper surface on which an insulated gate electrode and source electrode are provided and a lower surface on which a drain electrode is provided. Multiple regions of N-type and P-type conductivity are formed in the drift region, adjacent the upper surface of the substrate. As illustrated, these regions include an JFET “neck” region (N-type), a highly doped P-type shielding region, and a P-base, N+ source and P+ plug on the shielding region. As will be understood by those skilled in the art, the vertical P+ plug provides a low resistance electrical connection between the shielding region and the source electrode.

(26) In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.