Multi-mode envelope tracking amplifier circuit

Abstract

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

Claims

1. A multi-mode envelope tracking (ET) amplifier circuit comprising: a first output node; a second output node; at least one power amplifier circuit configured to amplify a radio frequency (RF) signal, the at least one power amplifier circuit comprising: a driver stage power amplifier; and an output stage differential power amplifier comprising a plus power amplifier and a minus power amplifier; first ET tracker circuitry configured to provide a first ET modulated voltage to the first output node; second ET tracker circuitry configured to provide a second ET modulated voltage to the second output node; first fast switcher circuitry configured to provide a first alternate current (AC) current to the first output node; second fast switcher circuitry configured to provide a second AC current to the second output node; and a control circuit configured to selectively activate or deactivate one or more of the first fast switcher circuitry and the second fast switcher circuitry based on modulation bandwidth of the RF signal.

2. The multi-mode ET amplifier circuit of claim 1 wherein the control circuit is further configured to deactivate the first fast switcher circuitry and the second fast switcher circuitry in a low-resource block (RB) mode.

3. The multi-mode ET amplifier circuit of claim 2 wherein the control circuit is further configured to: activate the first fast switcher circuitry to provide the first AC current to the first output node in a mid-RB mode and a high-RB mode in which the RF signal comprises more RBs than in the low-RB mode; and activate the second fast switcher circuitry to provide the second AC current to the second output node in the mid-RB mode and the high-RB mode in which the RF signal comprises more RBs than in the mid-RB mode.

4. The multi-mode ET amplifier circuit of claim 3 wherein: in the low-RB mode, the RF signal corresponds to a low modulation bandwidth having less than or equal to one hundred RBs; in the mid-RB mode, the RF signal corresponds to a mid modulation bandwidth having more than one hundred RBs and less than three hundred RBs; and in the high-RB mode, the RF signal corresponds to a high modulation bandwidth having greater than or equal to three hundred RBs.

5. The multi-mode ET amplifier circuit of claim 3 further comprising: first slow switcher circuitry configured to generate a first direct current (DC) current; and second slow switcher circuitry configured to generate a second DC current; wherein the control circuit is further configured to: activate the first slow switcher circuitry to provide the first DC current to the first output node in the low-RB mode, the mid-RB mode, and the high-RB mode; and activate the second slow switcher circuitry to provide the second DC current to the second output node in the low-RB mode, the mid-RB mode, and the high-RB mode.

6. The multi-mode ET amplifier circuit of claim 5 wherein the control circuit comprises: a fast switcher controller configured to selectively activate or deactivate the one or more of the first fast switcher circuitry and the second fast switcher circuitry; and a slow switcher controller configured to activate the first slow switcher circuitry and the second slow switcher circuitry.

7. The multi-mode ET amplifier circuit of claim 1 wherein: the plus power amplifier is coupled directly to the first output node; and the minus power amplifier is coupled directly to the second output node.

8. The multi-mode ET amplifier circuit of claim 1 wherein the plus power amplifier and the minus power amplifier are coupled to the first output node and the second output node via a common node.

9. The multi-mode ET amplifier circuit of claim 8 further comprising switching circuitry coupled between the common node, the first output node, and the second output node.

10. The multi-mode ET amplifier circuit of claim 9 wherein the control circuit is further configured to control the switching circuitry to couple the common node to both the first output node and the second output node.

11. The multi-mode ET amplifier circuit of claim 10 wherein: the first fast switcher circuitry provides one-half of the first AC current to the first output node; and the second fast switcher circuitry provides one-half of the second AC current to the second output node.

12. The multi-mode ET amplifier circuit of claim 9 wherein the control circuit is further configured to control the switching circuitry to couple the common node to one of the first output node and the second output node.

13. The multi-mode ET amplifier circuit of claim 1 wherein each of the first fast switcher circuitry and the second fast switcher circuitry comprises: a respective direct current (DC)-DC converter; a respective inductor; and a respective switch coupled between the respective DC-DC converter and the respective inductor.

14. The multi-mode ET amplifier circuit of claim 1 wherein: the first ET tracker circuitry is coupled to the first output node via a first offset capacitor; and the second ET tracker circuitry is coupled to the second output node via a second offset capacitor.

15. The multi-mode ET amplifier circuit of claim 1 wherein: the first ET tracker circuitry is further configured to generate the first ET modulated voltage at the first output node based on a first ET modulated target voltage and a first supply voltage; and the second ET tracker circuitry is further configured to generate the second ET modulated voltage at the second output node based on a second ET modulated target voltage and a second supply voltage.

16. The multi-mode ET amplifier circuit of claim 15 further comprising: a first inductor-based buck-boost circuit configured to provide the first supply voltage to the first ET tracker circuitry; and a second inductor-based buck-boost circuit configured to provide the second supply voltage to the second ET tracker circuitry.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid illustrating at least one resource block (RB);

(3) FIG. 2 is a schematic diagram of an exemplary conventional envelope tracking (ET) amplifier circuit including ET tracker circuitry configured to provide an ET modulated voltage to at least one power amplifier circuit for amplifying the RF signal of FIG. 1;

(4) FIG. 3 is a schematic diagram of an exemplary multi-mode ET amplifier circuit that can operate with an improved efficiency greater than the conventional ET amplifier circuit of FIG. 2 in low-resource block (RB) mode, mid-RB mode, and high-RB mode;

(5) FIG. 4 is a schematic diagram of an exemplary multi-mode ET amplifier circuit configured to support at least one power amplifier circuit operating in low-RB mode, mid-RB mode, and high-RB mode based on first ET tracker circuitry and second ET tracker circuitry; and

(6) FIG. 5 is a schematic diagram of an exemplary multi-mode ET amplifier circuit configured to support at least one power amplifier circuit operating in low-RB mode, mid-RB mode, and high-RB mode according to an alternative embodiment.

DETAILED DESCRIPTION

(7) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(8) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(9) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(10) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(11) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(12) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(13) Aspects disclosed in the detailed description include a multi-mode envelope tracking (ET) amplifier circuit. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes ET tracker circuitry to provide an ET modulated voltage to an output node and fast switcher circuitry to generate an alternating current (AC) current. The fast switcher circuitry includes a first switcher path and a second switcher path. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit activates the fast switcher circuitry to provide the AC current to the output node via one of the first switcher path and the second switcher path in the mid-RB mode, while activating the fast switcher circuitry to provide the AC current to the output node via both the first switcher path and the second switcher path in the high-RB mode. Accordingly, a power amplifier circuit(s) coupled to the output node can amplify a radio frequency (RF) signal based on the ET modulated voltage and the AC current. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

(14) Before discussing the multi-mode ET amplifier circuit of the present disclosure, a brief overview of an RB-based resource allocation scheme is first provided with reference FIG. 1 to help understand the relationship between bandwidth of an RF signal and the number of RBs allocated to the RF signal. A brief discussion of a conventional ET amplifier circuit for amplifying an RF signal is then provided with reference to FIG. 2. The discussion of specific exemplary aspects of a multi-mode ET amplifier circuit starts below with reference to FIG. 3.

(15) In this regard, FIG. 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid 10 illustrating at least one RB 12. The OFDM time-frequency grid 10 includes a frequency axis 14 and a time axis 16. Along the frequency axis 14, there is a plurality of subcarriers 18(1)-18(M). The subcarriers 18(1)-18(M) are orthogonally separated from each other by a frequency spacing Δf of 15 KHz. Along the time axis 16, there is a plurality of OFDM symbols 20(1)-20(N). Each intersection of the subcarriers 18(1)-18M) and the OFDM symbols 20(1)-20(N) defines a resource element (RE) 21.

(16) In one example, the RB 12 includes twelve (12) consecutive subcarriers among the subcarriers 18(1)-18(M), and seven (7) consecutive OFDM symbols among the OFDM symbols 20(1)-20(N). In this regard, the RB 12 includes eighty-four (84) of the REs 21 (12 subcarriers×7 OFDM symbols). The RB 12 has an RB duration 22, which equals a one-half millisecond (0.5 ms), along the time axis 16. Accordingly, the RB 12 has a bandwidth 24, which equals 180 KHz (15 KHz/subcarrier×12 subcarriers), along the frequency axis 14. In OFDM-based communication systems such as long-term evolution (LTE) and fifth-generation new radio (5G-NR), the RB 12 is the minimum unit for allocating resources to users.

(17) In an LTE system, an RF signal 26 can occupy multiple subcarriers among the subcarriers 18(1)-18(N). In this regard, a signal bandwidth 28 of the RF signal 26 is a function of the number of RBs 12 contained in the RF signal 26 along the frequency axis 14. In this regard, if the RF signal 26 contains ten (10) RBs 12, then the signal bandwidth 28 will be 1.8 MHz (180 KHz/RB×10 RBs). If the RF signal 26 contains twenty-five (25) RBs 12, then the signal bandwidth 28 will be 4.5 MHz (180 KHz/RB×25 RBs). If the RF signal 26 contains two hundred (200) RBs 12, then the signal bandwidth 28 will be 36 MHz (180 KHz/RB×200 RBs). In this regard, the more RBs 12 the RF signal 26 contains, the wider the signal bandwidth 28 will be, and the more subcarriers among the subcarriers 18(1)-18(M) are modulated within the RB duration 22. As such, the RF signal 26 can exhibit more and faster amplitude variations within the RB duration 22 when the RF signal 26 is modulated according to a selected modulation and coding scheme (MCS). As a result, when the RF signal 26 is amplified for transmission over a wireless medium, a power amplifier circuit would need to operate fast enough to keep up with the faster amplitude variations of the RF signal 26 across the signal bandwidth 28 within the RB duration 22. Accordingly, a circuit providing ET modulated voltage to the power amplifier circuit needs to provide the ET modulation at a faster frequency (e.g., 250 MHz or above) to keep up with the fast operation of the power amplifier circuit.

(18) In this regard, FIG. 2 is a schematic diagram of an exemplary conventional ET amplifier circuit 30 including ET tracker circuitry 32 configured to provide an ET modulated voltage V.sub.CC to at least one power amplifier circuit 34 for amplifying the RF signal 26 of FIG. 1. Elements of FIG. 1 are referenced in conjunction with FIG. 2 and will not be re-described herein.

(19) The ET tracker circuitry 32 includes a tracker input 36 and a tracker output 38. The ET tracker circuitry 32 receives an ET modulated target voltage V.sub.TARGET at the tracker input 36 and generates an ET modulated output voltage V.sub.OUT, which tracks the ET modulated target voltage V.sub.TARGET, at the tracker output 38. The tracker output 38 is coupled to an output node 40 via an offset capacitor 42. The offset capacitor 42 is configured to convert the ET modulated output voltage V.sub.OUT into the ET modulated voltage V.sub.CC at the output node 40. In a non-limiting example, the ET modulated voltage V.sub.CC is one volt (1V) higher than the ET modulated output voltage V.sub.OUT.

(20) In the conventional ET amplifier circuit 30, the ET modulated target voltage V.sub.TARGET provides a target voltage envelope for the ET modulated voltage V.sub.CC, which serves as a supply voltage to the power amplifier circuit 34 for amplifying the RF signal 26. As previously discussed in FIG. 1, the RF signal 26 may have faster amplitude variations within the RB duration 22 when the RF signal 26 contains a higher number of RBs 12 (e.g., more than 100 RBs). As such, the ET modulated voltage V.sub.cc needs to change at a faster frequency within the RB duration 22 (dV.sub.OUT/dt) to keep up with the faster amplitude variations of the RF signal 26.

(21) The power amplifier circuit 34 is coupled to the output node 40 to receive the ET modulated voltage VCC. The power amplifier circuit 34 has a load line R.sub.LOAD, which induces a load current I.sub.LOAD based on the ET modulated voltage V.sub.CC (e.g., I.sub.LOAD=V.sub.CC÷R.sub.LOAD). The load current I.sub.LOAD includes a DC current I.sub.DC and an AC current I.sub.AC. The AC current I.sub.AC has an AC current frequency that tracks the variations of the ET modulated voltage V.sub.CC. In this regard, the AC current frequency is higher when the RF signal 26 contains more than 100 RBs, and is lower when the RF signal 26 contains less than or equal to 100 RBs.

(22) The conventional ET amplifier circuit 30 includes switcher circuitry 44 and a control circuit 46 configured to control the switcher circuitry 44. The switcher circuitry 44 includes a DC-DC converter 48 and an inductor 50. The DC-DC converter 48 is configured to generate a DC voltage V.sub.DC. The inductor 50, which can have an inductance L between 1.1 microHenry (1.1 μH) and 2.2 μH for example, induces a switcher current I.sub.SW. The switcher current I.sub.SW has a switcher current frequency dI.sub.SW/dt that can be determined based on the equation (Eq. 1) below.
dI.sub.SW/dt=(V.sub.DC−V.sub.CC)/L  (Eq. 1)

(23) As can be seen from the equation (Eq. 1) above, the switcher current frequency dI.sub.SW/dt is inversely related to the inductance L of the inductor 50. Given that the inductance L of the inductor 50 needs to be large enough to help reduce noise degradation, the switcher current frequency dI.sub.SW/dt may not be fast enough to keep up with modulation changes of the ET modulated voltage V.sub.CC when the RF signal 26 contains more than 100 RBs. As such, the switcher circuitry 44 would only be able to provide the switcher current I.sub.SW as the DC current I.sub.DC in the load current I.sub.LOAD. Consequently, the ET tracker circuitry 32 will be forced to supply the AC current I.sub.AC in the load current I.sub.LOAD, thus compromising efficiency of the ET tracker circuitry 32.

(24) The ET tracker circuitry 32 provides a sense current I.sub.SENSE, which is proportional to the AC current I.sub.AC, to the control circuit 46. The control circuit 46 relies on the sense current I.sub.SENSE to detect the AC current I.sub.AC generated by the ET tracker circuitry 32, and controls the switcher circuitry 44 to adjust the switcher current I.sub.SW in an effort to minimize the AC current I.sub.AC. In this regard, when the ET tracker circuitry 32 increases the AC current I.sub.AC, the sense current I.sub.SENSE would also increase proportionally. The increased sense current I.sub.SENSE can cause parasitic capacitance to increase in field-effect transistors (FETs) contained in the switcher circuitry 44, thus further reducing the efficiency of the switcher circuitry 44. In this regard, it may be desired to minimize the AC current I.sub.AC generated by the ET tracker circuitry 32 under all operating conditions, especially when the RF signal 26 contains more than 100 RBs.

(25) In this regard, FIG. 3 is a schematic diagram of an exemplary multi-mode ET amplifier circuit 52 including ET tracker circuitry 54 that can operate with improved efficiency greater than the ET tracker circuitry 32 in the conventional ET amplifier circuit 30 of FIG. 2 in a low-RB mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit 52 includes an output node 56 coupled to at least one power amplifier circuit 58. In a non-limiting example, the power amplifier circuit 58 can be a serial amplifier circuit, which includes a driver stage amplifier and an output stage amplifier coupled in tendon, or a differential amplifier circuit, which includes a driver stage amplifier and an output stage differential amplifier coupled in tendon. The power amplifier circuit 58 is configured to amplify an RF signal 60 to a determined power.

(26) In examples discussed herein, the multi-mode ET amplifier circuit 52 operates in the low-RB mode when the RF signal 60 includes less than or equal to 100 RBs (≤100 RBs). The multi-mode ET amplifier circuit 52 operates in the mid-RB mode when the RF signal 60 includes more than 100 RBs but less than 300 RBs (>100 RBs and <300 RBs). The multi-mode ET amplifier circuit 52 operates in the high-RB mode when the RF signal 60 includes greater than or equal to 300 RBs (≥300 RBs).

(27) The multi-mode ET amplifier circuit 52 includes slow switcher circuitry 62, which is functionally equivalent to the switcher circuitry 44 in FIG. 2 and typically operates in the low-RB mode. The multi-mode ET amplifier circuit 52 also includes fast switcher circuitry 64 configured to operate only in the mid-RB mode and the high-RB mode. As is further discussed below, the fast switcher circuitry 64 can be activated in the mid-RB mode and the high-RB mode to help minimize AC current supplied by the ET tracker circuitry 54, thus improving operating efficiency of the ET tracker circuitry 54 and the multi-mode ET amplifier circuit 52 as a whole.

(28) The ET tracker circuitry 54, which can be functionally equivalent to the ET tracker circuitry 32 of FIG. 2, includes a tracker input 66 and a tracker output 68. The ET tracker circuitry 54 receives an ET modulated target voltage V.sub.TARGET at the tracker input 66 and generates an ET modulated output voltage V.sub.OUT, which tracks the ET modulated target voltage V.sub.TARGET, at the tracker output 68. The tracker output 68 is coupled to the output node 56 via an offset capacitor 70. The offset capacitor 70 is configured to convert the ET modulated output voltage V.sub.OUT into the ET modulated voltage V.sub.CC at the output node 56. In a non-limiting example, the ET modulated voltage V.sub.CC is one volt (1 V) higher than the ET modulated output voltage V.sub.OUT.

(29) In the multi-mode ET amplifier circuit 52, the ET modulated target voltage V.sub.TARGET provides a target voltage envelope for the ET modulated voltage V.sub.CC, which serves as a supply voltage to the power amplifier circuit 58 for amplifying the RF signal 60. The power amplifier circuit 58 has a load line R.sub.LOAD, which induces a load current I.sub.LOAD based on the ET modulated voltage V.sub.CC (e.g., I.sub.LOAD=V.sub.CC÷R.sub.LOAD). As previously discussed in FIG. 2, the load current I.sub.LOAD includes the DC current I.sub.DC and the AC current I.sub.AC.

(30) The slow switcher circuitry 62 includes a first DC-DC converter 72 and a first inductor 74. The first DC-DC converter 72 is configured to generate a first DC voltage V.sub.DC_L. The first inductor 74, which can have a first inductance L.sub.1 between 1.1 μH and 2.2 μH for example, induces a DC current I.sub.SW_L.

(31) The fast switcher circuitry 64 includes a second DC-DC converter 76, a second inductor 78, and a third inductor 80. The second DC-DC converter 76 and the second inductor 78 form a first switcher path 82. The second DC-DC converter 76 and the third inductor 80 form a second switcher path 84. The second DC-DC converter 76 is configured to generate a second DC voltage V.sub.DC_S based on a supply voltage V.sub.BATAMP supplied by an inductor-based buck-boost circuit 86. The second inductor 78, which has a second inductance L.sub.2 between 100 nanoHenry (nH) and 200 nH and the third inductor 80, which has a third inductance L.sub.3 between 100 nH and 200 nH, induces an AC current I.sub.SW_S. The second inductance L.sub.2 and the third inductance L.sub.3 can be equal or different. In a non-limiting example, the second inductor 78 and the third inductor 80 are disposed in parallel between the second DC-DC converter 76 and the tracker output 68 to form an inductor pair 88. When activated, the fast switcher circuitry 64 can provide the AC current I.sub.SW_S to the tracker output 68 and subsequently to the output node 56 via the offset capacitor 70. Thus, the fast switcher circuitry 64 can supply the AC current I.sub.AC in the load current I.sub.LOAD. As a result, it is possible to minimize the AC current supplied by the ET tracker circuitry 54, thus helping to improve the operating efficiency of the ET tracker circuitry 54.

(32) The multi-mode ET amplifier circuit 52 includes a control circuit 90. The control circuit 90 includes a slow switcher controller 92 coupled to the slow switcher circuitry 62 and a fast switcher controller 94 coupled to the fast switcher circuitry 64. In a non-limiting example, the slow switcher controller 92 and the fast switcher controller 94 are both provided as bang-band controllers (BBCs).

(33) The slow switcher controller 92 is configured to activate the slow switcher circuitry 62 in the low-RB mode, the mid-RB mode, and the high-RB mode to provide the DC current I.sub.SW_L to the output node 56 as the DC current I.sub.DC in the load current I.sub.LOAD.

(34) The fast switcher controller 94 is configured to activate the fast switcher circuitry 64 to provide the AC current I.sub.SW_S to the tracker output 68 and subsequently to the output node 56 as the AC current I.sub.AC in the load current I.sub.LOAD. More specifically, in the mid-RB mode, the fast switcher controller 94 controls the fast switcher circuitry 64 to provide the AC current I.sub.SW_S through a selected switcher path between the first switcher path 82 and the second switcher path 84. For example, the fast switcher controller 94 can select the first switcher path 82 by closing switch S.sub.1 and opening switch S.sub.2 or select the second switcher path 84 by opening switch S.sub.1 and closing switch S.sub.2.

(35) In the high-RB mode, the fast switcher controller 94 controls the fast switcher circuitry 64 to provide the AC current I.sub.SW_S through both the first switcher path 82 and the second switcher path 84 by concurrently closing switch S.sub.1 and switch S.sub.2. Given that the second inductor 78 and the third inductor 80 are disposed in parallel, inductance of the inductor pair 88 would be smaller than the second inductance L.sub.2 and the third inductance L.sub.3. As such, the fast switcher circuitry 64 can support higher switcher current frequency dI.sub.SW_S/dt compared to providing the AC current I.sub.SW_S through the selected switcher path between the first switcher path 82 and the second switcher path 84. When the multi-mode ET amplifier circuit 52 is operating in the low-RB mode, the fast switcher controller 94 deactivates the fast switcher circuitry 64.

(36) The fast switcher controller 94 can be configured to activate or deactivate the fast switcher circuitry 64 based on whether the ET tracker circuitry 54 is forced to generate the AC current I.sub.AC Specifically, the fast switcher controller 94 may activate the fast switcher circuitry 64 in response to determining that the ET tracker circuitry 54 is sourcing the AC current I.sub.AC to the output node 56. The control circuit 90 may deactivate the fast switcher circuitry 64 in response to determining that the ET tracker circuitry 54 is sinking the AC current I.sub.AC from the output node 56.

(37) Given that the amplitude variations of the RF signal 60 can be slower in the low-RB mode as opposed to being faster in the mid-RB mode and the high-RB mode, the slow switcher circuitry 62 may be able to supply the AC current I.sub.AC in the low-RB mode in addition to supplying the DC current I.sub.DC. As such, the slow switcher controller 92 may control the slow switcher circuitry 62 to provide the AC current I.sub.AC to the output node 56, thus helping to minimize the AC current I.sub.AC supplied by the ET tracker circuitry 54, which further helps to improve the operating efficiency of the ET tracker circuitry 54 in the low-RB mode.

(38) The fast switcher circuitry 64 can be configured to generate a switcher sense current 96 that is in proportion to the AC current I.sub.SW_S generated by the fast switcher circuitry 64. Likewise, the ET tracker circuitry 54 can be configured to generate a tracker sense current 98 that is in proportion to the AC current I.sub.AC sourced or sank by the ET tracker circuitry 54. The tracker sense current 98 is a positive current when the ET tracker circuitry 54 is sourcing the AC current I.sub.AC. In contrast, the tracker sense current 98 is a negative current when the ET tracker circuitry 54 is sinking the AC current I.sub.AC.

(39) In a non-limiting example, the fast switcher controller 94 receives the tracker sense current 98 from the ET tracker circuitry 54. The fast switcher controller 94 can control the fast switcher circuitry 64 to increase the AC current I.sub.SW_S in response to the tracker sense current 98 being the positive current. In contrast, the fast switcher controller 94 can control the fast switcher circuitry 64 to decrease the AC current I.sub.SW_S in response to the tracker sense current 98 being the negative current.

(40) More specifically, the fast switcher controller 94 can utilize a first positive current threshold and a second positive current threshold that is higher than the first positive current threshold to help determine whether the multi-mode ET amplifier circuit 52 is operating in the mid-RB mode or the high-RB mode. If the tracker sense current 98 is higher than the first positive current threshold but lower than the second positive current threshold, the fast switcher controller 94 can determine that the multi-mode ET amplifier circuit 52 is operating in the mid-RB mode. Accordingly, the fast switcher controller 94 can activate the selected switcher path between the first switcher path 82 and the second switcher path 84 to provide the AC current I.sub.SW_S to the output node 56 as the AC current I.sub.AC. If the tracker sense current 98 is higher than the second positive current threshold, the fast switcher controller 94 can determine that the multi-mode ET amplifier circuit 52 is operating in the high-RB mode. Accordingly, the fast switcher controller 94 actives both the first switcher path 82 and the second switcher path 84 to provide the AC current I.sub.SW_S to the output node 56 as the AC current I.sub.AC. In contrast, if the tracker sense current 98 is below the first positive current threshold, the fast switcher controller 94 can determine that the multi-mode ET amplifier circuit 52 is operating in the low-RB mode. Accordingly, the fast switcher controller 94 deactivates the first switcher path 82 and the second switcher path 84.

(41) The slow switcher controller 92 is configured to receive the switcher sense current 96 and the tracker sense current 98 from the fast switcher circuitry 64 and the ET tracker circuitry 54, respectively. The slow switcher controller 92 controls the slow switcher circuitry 62 to adjust the DC current I.sub.SW_L based on the switcher sense current 96 and the tracker sense current 98.

(42) The multi-mode ET amplifier circuit 52 includes a current combiner 100 configured to receive and combine the switcher sense current 96 and the tracker sense current 98 to generate a combined sense current 102. The multi-mode ET amplifier circuit 52 also includes a gain regulator 104 provided between the current combiner 100 and the slow switcher controller 92. The gain regulator 104 receives the combined sense current 102 from the current combiner 100 and scales the combined sense current 102 based on a scaling factor to generate a scaled sense current 106. The gain regulator 104 is further configured to provide the scaled sense current 106 to the slow switcher controller 92 for controlling the slow switcher circuitry 62.

(43) The gain regulator 104 is provided to keep the amount of the combined sense current 102 relatively stable between the low-RB mode and the mid-RB mode or the high-RB mode. In a non-limiting example, the scaling factor is set to one in the low-RB mode and less than one in the mid-RB mode or the high-RB mode. In a non-limiting example, the scaling factor can be greater than 1/30 and less than one in the mid-RB mode, and less than 1/30 in the high-RB mode. The scaling factor can be set to one in the low-RB mode, because the combined sense current 102 would be smaller as a result of the fast switcher circuitry 64 being deactivated and the switcher sense current 96 being eliminated. In contrast, in the mid-RB and the high-RB mode, the combined sense current 102 would be higher as a result of the fast switcher circuitry 64 being activated. Thus, by setting the scaling factor to be less than one, it is possible to scale down the amount of the combined sense current 102 in the mid-RB mode and the high-RB mode. As a result, the slow switcher circuitry 62 can include less and smaller FETs (e.g., with thinner dielectric layer), thus helping to reduce parasitic capacitance in the slow switcher circuitry 62. In addition, by scaling down the amount of the combined sense current 102 in the mid-RB mode and the high-RB mode, the slow switcher circuitry 62 can operate at a lowest possible switching frequency. The combination of reduced parasitic capacitance and lowered switching frequency allows the slow switcher circuitry 62 to operate at a higher efficiency.

(44) In a non-limiting example, the slow switcher controller 92 can determine the amount of the load current I.sub.LOAD at the output node 56 based on the scaled sense current 106 (e.g., based on a look-up table). As such, the slow switcher controller 92 can control the first DC-DC converter 72 to adjust the first DC voltage V.sub.DC_L to increase or decrease the DC current I.sub.SW_L.

(45) As previously discussed, the ET modulated target voltage V.sub.TARGET provides the target voltage envelope for the ET modulated voltage V.sub.CC, which serves as a supply voltage to the power amplifier circuit 58 for amplifying the RF signal 60. In this regard, the ET modulated voltage V.sub.CC is configured to vary according to the amplitude variations of the RF signal 60 at the output node 56. Accordingly, the AC current I.sub.SW_S also needs to vary according to the amplitude variations of the RF signal 60 to maximize operating efficiency of the multi-mode ET amplifier circuit 52.

(46) However, active components (e.g., FETs, switching drivers, switches, and inductors) in the fast switcher controller 94 and the fast switcher circuitry 64 can introduce delays in the AC current I.sub.SW_S. For example, in the high-RB mode where the RF signal 60 includes more than 300 RBs, the AC current I.sub.SW_S can be delayed by approximately one to two nanoseconds (1-2 ns), which can cause the multi-mode ET amplifier circuit 52 to lose two to three percent (2-3%) of efficiency. Hence, it may be desired to provide a timing advance in the AC current I.sub.SW_S to mitigate the delay resulting from the fast switcher controller 94 and the fast switcher circuitry 64.

(47) In this regard, the multi-mode ET amplifier circuit 52 further includes delay compensation circuitry 108 configured to mitigate a processing delay in the fast switcher controller 94 and the fast switcher circuitry 64. The delay compensation circuitry 108 is coupled to the ET tracker circuitry 54 and the fast switcher controller 94. The delay compensation circuitry 108 is configured to provide a timing advance in the AC current I.sub.SW_S by delaying the ET modulated target voltage V.sub.TARGET, thus compensating for the processing delay associated with the fast switcher circuitry 64 in the mid-RB mode and the high-RB mode. In a non-limiting example, the delay compensation circuitry 108 is configured to delay the ET modulated target voltage V.sub.TARGET by an estimated processing delay dT (e.g., 1-2 ns) associated with the fast switcher controller 94 and the fast switcher circuitry 64.

(48) At any determined time t, the delay compensation circuitry 108 receives an advanced ET modulated target voltage V′.sub.TARGET that represents the ET modulated target voltage E.sub.TARGET at time t+dT. In this regard, the advanced ET modulated target voltage V′.sub.TARGET is a forward-looking sample of the ET modulated target voltage V.sub.TARGET at the time t+dT. The delay compensation circuitry 108 includes first delay circuitry 110 configured to delay the advanced ET modulated target voltage V′.sub.TARGET by the estimated processing delay dT to generate the ET modulated target voltage V.sub.TARGET. The delay compensation circuitry 108 includes second delay circuitry 112 configured to delay the ET modulated target voltage V.sub.TARGET by the estimated processing delay dT to generate a delayed ET modulated target voltage V″.sub.TARGET. In this regard, the delayed ET modulated target voltage V″.sub.TARGET is a backward-looking sample of the ET modulated target voltage V.sub.TARGET at the time t-dT.

(49) The delay compensation circuitry 108 also includes current adjustment circuitry 114. The current adjustment circuitry 114 generates a differential current ΔI indicative of an estimated current change at the determined time t. In a non-limiting example, the current adjustment circuitry 114 determines the differential current ΔI based on the equations (Eq. 2.1, Eq. 2.2, and Eq. 2.3) below.
ΔI.sub.C=C/dT×[V.sub.CC(t−dT)−2V.sub.CC(t)+V.sub.CC(t+dT)]  (Eq. 2.1)
ΔI.sub.LOAD=1/R.sub.LOAD×[V.sub.CC(t+dT)−V.sub.CC(t)]  (Eq. 2.2)
ΔI=ΔI.sub.C+ΔI.sub.LOAD  (Eq. 2.3)

(50) In Eq. 2.1 ΔI.sub.C represents an estimated current change relative to a bypass capacitor 116, and C represents total load capacitance of the power amplifier circuit 58. V.sub.CC(t−dT), V.sub.CC(t), and V.sub.CC(t+dT) represent estimates of the ET modulated voltage V.sub.CC at times t−dT, t, and t+dT, respectively. In Eq. 2.2, ΔI.sub.LOAD represents an estimated current change relative to the load line R.sub.LOAD for the duration between t−dT and t+dT. In a non-limiting example, the total load capacitance C is typically known and does not change for a given design of the power amplifier circuit 58. The load line R.sub.LOAD, on the other hand, will change from time to time to adapt to voltage standing wave ratio (VSWR) changes of the ET tracker circuitry 54. In a non-limiting example, the load line R.sub.LOAD can be determined based on a look-up table (LUT) of the ET tracker circuitry 54.

(51) The multi-mode ET amplifier circuit 52 includes a second combiner 118. The second combiner 118 combines the differential current Δl with the tracker sense current 98 to generate a delay-compensated sense current 120, and provide the delay-compensated sense current 120 to the fast switcher controller 94. The fast switcher controller 94 is configured to control the fast switcher circuitry 64 based on the delay-compensated sense current 120 to minimize the processing delay in the AC current I.sub.SW_S, thus helping to further improve the efficiency of the multi-mode ET amplifier circuit 52.

(52) Notably, the multi-mode ET amplifier circuit 52 can include more than one of the ET tracker circuitry 54 for supporting concurrent RF signal transmissions such as uplink carrier aggregation (ULCA). In addition, the power amplifier circuit 58 can be provided as a differential power amplifier circuit including a driver stage amplifier and a differential output stage amplifier. In this regard, as described next in FIGS. 4 and 5, it may be possible to utilize the multiple ET tracker circuitries already existed in the multi-mode ET amplifier circuit 52 to provide the AC current I.sub.AC in the mid-RB mode and the high-RB mode using a single inductor, and thus a single switcher path, in the fast switcher circuitry 64. Understandably, eliminating a second switcher path from the fast switcher circuitry 64 can help reduce cost and implementation complexity.

(53) In this regard, FIG. 4 is a schematic diagram of an exemplary multi-mode ET amplifier circuit 122 configured to support at least one power amplifier circuit 124 operating in the low-RB mode, the mid-RB mode, and the high-RB mode based on first ET tracker circuitry 126 and second ET tracker circuitry 128. The multi-mode ET amplifier circuit 122 includes a first output node 130 and a second output node 132. In a non-limiting example, the power amplifier circuit 124 is a differential power amplifier circuit including a driver stage amplifier 134 and an output stage amplifier 136. The output stage amplifier 136 is a differential amplifier including a plus power amplifier 138P coupled to the first output node 130 and a minus power amplifier 138M coupled to the second output node 132. The power amplifier circuit 124 is configured to amplify an RF signal 140 based on a first ET modulated voltage V.sub.CC1 received at the first output node 130 and a second ET modulated voltage V.sub.CC2 received at the second output node 132. The first ET tracker circuitry 126 is coupled to the first output node 130 via a first offset capacitor C.sub.OFFSET1 and the second ET tracker circuitry 128 is coupled to the second output node 132 via a second offset capacitor C.sub.OFFSET2. The first ET tracker circuitry 126 is configured to provide the first ET modulated voltage V.sub.CC1 to the first output node 130 based on a first ET modulated target voltage V.sub.TARGET1 and a first supply voltage V.sub.BATAMP1. The second ET tracker circuitry 128 is configured to provide the second ET modulated voltage V.sub.CC2 to the second output node 132 based on a second ET modulated target voltage V.sub.TARGET2 and a second supply voltage V.sub.BATAMP2. The multi-mode ET amplifier circuit 122 includes a first inductor-based buck-boost circuit 142 to provide the first supply voltage V.sub.BATAMP1 to the first ET tracker circuitry 126 and a second inductor-based buck-boost circuit 144 to supply the second supply voltage V.sub.BATAMP2 to the second ET tracker circuitry 128.

(54) The multi-mode ET amplifier circuit 122 includes first fast switcher circuitry 146 and second fast switcher circuitry 148. The first fast switcher circuitry 146 and the second fast switcher circuitry 148 each include a respective DC-DC converter 150, a respective inductor 152, and a respective switch S.sub.1.

(55) The multi-mode ET amplifier circuit 122 includes a fast switcher controller 154 to control the first fast switcher circuitry 146 and the second fast switcher circuitry 148. The fast switcher controller 154 activates the first fast switcher circuitry 146 and the second fast switcher circuitry 148 to provide a first AC current I.sub.AC1 and a second AC current I.sub.AC2 to the first output node 130 and the second output node 132, respectively, in the mid-RB mode and the high-RB mode. The fast switcher controller 154 deactivates the first fast switcher circuitry 146 and the second fast switcher circuitry 148 in the low-RB mode.

(56) The multi-mode ET amplifier circuit 122 also includes first slow switcher circuitry 156 and second slow switcher circuitry 158. The first slow switcher circuitry 156 and the second slow switcher circuitry 158 each include a respective DC-DC converter 160 and a respective inductor 162. Notably, the respective inductor 162 has substantially higher inductance than the respective inductor 152. The multi-mode ET amplifier circuit 122 includes a slow switcher controller 164 to control the first slow switcher circuitry 156 and the second slow switcher circuitry 158. The slow switcher controller 164 activates the first slow switcher circuitry 156 and the second slow switcher circuitry 158 to provide a first DC current I.sub.DC1 and a second DC current I.sub.DC2 to the first output node 130 and the second output node 132, respectively, in the low-RB mode, the mid-RB mode, and the high-RB mode.

(57) Notably, the first ET tracker circuitry 126 and the second ET tracker circuitry 128 can support additional power amplifier circuits 166 in other modes of operation such as ULCA, multiple-input multiple output (MIMO), and RF beamforming. The additional power amplifier circuits 166 may be serial power amplifier circuits and/or differential power amplifier circuits.

(58) FIG. 5 is a schematic diagram of an exemplary multi-mode ET amplifier circuit 168 configured to support at least one power amplifier circuit 170 operating in the low-RB mode, the mid-RB mode, and the high-RB mode according to an alternative embodiment. Common elements between FIGS. 4 and 5 are shown therein with common element numbers and will not be re-described herein.

(59) The plus power amplifier 138P and the minus power amplifier 138M are coupled to a common node 172. The common node 172 is coupled to the first output node 130 and the second output node 132 via switching circuitry 174. In this regard, in the mid-RB mode and the high-RB mode, the fast switcher controller 154 may couple the first fast switcher circuitry 146, or the second fast switcher circuitry 148, or both the first fast switcher circuitry 146 and the second fast switcher circuitry 148 to the common node 172 by controlling the switching circuitry 174. When the fast switcher controller 154 couples the first fast switcher circuitry 146 to the common node 172, the first fast switcher circuitry 146 provides the first AC current I.sub.AC1 to the common node 172. When the fast switcher controller 154 couples the second fast switcher circuitry 148 to the common node 172, the second fast switcher circuitry 148 provides the second AC current I.sub.AC2 to the common node 172. When the fast switcher controller 154 couples both the first fast switcher circuitry 146 and the second fast switcher circuitry 148 to the common node 172, the first fast switcher circuitry 146 provides one-half (½) of the first AC current I.sub.AC1 to the common node 172 and the second fast switcher circuitry 148 provides ½ of the second AC current I.sub.AC2 to the common node 172. Notably, the switching circuitry 174 may already exist in the multi-mode ET amplifier circuit 168 for supporting other modes of operation (e.g., ULCA, MIMO, RF beamforming). In this regard, the switching circuitry 174 is reconfigured to support the mid-RB mode and the high-RB mode in addition to supporting the existing mode of operations.

(60) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.