DMS FILTER, ELECTROACOUSTIC FILTER AND MULTIPLEXER

Abstract

An improved DMS filter with electrode structures between a first port and a second port is provided. Wiring junctions are realized in multilayer crossing with dielectric material in between. There are insulating patches (L2) between crossing conductor layers (L1,L3). Signal wirings may be realized with multiple conductor layers (L1, L3) to reduce wiring resistance and the upper conductor layer (L3) of the signal wiring may partly overlap the insulating patches (L2). The insulating patches (L2) may extend over the acoustic path to achieve temperature compensation.

Claims

1. A DMS filter, comprising: a first port and a second port, a piezoelectric material, and an electrode structure arranged above or on the piezoelectric material and electrically connected between the first port and the second port, wherein: the electrode structure has a multi layer construction, the multi layer construction comprises metal and dielectric material.

2. The DMS filter of the claim 1, further comprising: a first acoustic reflector and a second acoustic reflector, first IDTs and second IDTs, wherein the first IDTs and the second IDTs are arranged between the first and the second acoustic reflector.

3. The DMS filter of claim 2, wherein the electrode structure comprises: a first inter IDT connection and a second inter IDT connection, wherein: each IDT has a first busbar and a first connection and a second busbar and a second connection, first busbars and connections of the first IDTs are electrically connected via the first inter IDT connection, and second busbars and connections of the second IDTs are electrically connected via the second inter IDT connection.

4. The DMS filter of claim 3, wherein the first and the second inter IDT connection comprise a lower metal strip and an upper metal strip.

5. The DMS filter of claim 3, wherein the electrode structure comprises: a third inter IDT connection and a fourth inter IDT connection, wherein each of the third inter IDT connection and the fourth inter IDT connection comprises an inner metal strip.

6. The DMS filter of the claim 5, wherein the dielectric material of the electrode structure comprises: insulating patches between the third inter IDT connection and the first connections of the first IDTs and insulating patches between the fourth inter IDT connection and the second connections of the second IDTs.

7. The DMS filter of claim 2, wherein the multi layer construction comprises: lower metal strips of the first and of the second inter IDT connections in a first layer, upper metal strips of the first and of the second inter IDT connections in a third layer, and insulating patches in a second layer between the first layer and the third layer.

8. The DMS filter of claim 7, wherein the third layer has a higher thickness than the first layer.

9. The DMS filter of claim 7, wherein the third layer has a higher electrical conductivity than the first layer.

10. The DMS filter of claim 5, wherein the third inter IDT connection and the fourth inter IDT connection are connected to a ground potential.

11. The DMS filter of claim 2, wherein the first IDTs are input IDTs and the second IDTs are output IDTs.

12. The DMS filter of claim 1, further comprising a TC layer.

13. The DMS filter of claim 12, where the TC layer is additionally used as insulator for line crossings.

14. The DMS filter of claim 1, being a TF-SAW DMS filter.

15. The DMS filter of claim 7, wherein the upper metal strips (UMS) of the first inter IDT connection (IIC1) and/or the second inter IDT connection (IIC2) overlap the isolating patches (IP) by an overlap width o1.

16. The DMS filter of claim 5, wherein inner metal strips (IMS) of the third inter IDT connection (IIC3) and/or the fourth inter IDT connection (IIC4) are with full width (w2) located on top of the isolating patches (IP).

17. The DMS filter of claim 7, wherein: the upper metal strip (UMS) of the first inter IDT connection (IIC1) fully covers the lower metal strip (LMS) of IIC1, and/or the upper metal strip (UMS) of the second inter IDT connection (IIC2) fully covers the lower metal strip (LMS) of IIC2.

18. The DMS filter of claim 17, wherein the insulating patches (IP) do not overlap the lower metal strip (LMS).

19. The DMS filter of claim 17, wherein the electrode structure is free from the lower metal strips (LMS).

20. The DMS filter of claim 2, wherein the isolating patches (IP) overlap the first connections (C1) of the first IDTs (IDT1) and the second connections (C2) of the second IDTs (IDT2).

21. The DMS filter of claim 3, wherein the isolating patches (IP) do not overlap the first busbars (B1) and/or the second busbars (B2).

22. The DMS filter of claim 1, wherein the DMS filter is included as part of an electroacoustic filter, the DMS filter being an 11-IDT DMS filter.

23. The DMS filter of claim 1, wherein the DMS filter is included as part of a multiplexer.

Description

[0085] In the figures:

[0086] FIG. 1 shows an 11-IDT DMS filter illustrating important elements in form of the first metal layer in a top view;

[0087] FIG. 2 illustrates a cross-section through an IDT;

[0088] FIG. 3 illustrates the orientation of the IDTs within the acoustic track with respect to the transversal direction y;

[0089] FIG. 4 illustrates the use of a dielectric material to create conductor path crossings;

[0090] FIG. 5 illustrates the positions of the elements of the first and of the second inter IDT connections and of the third and fourth inter IDT connections;

[0091] FIG. 6 illustrates the possibility of providing material of a TC layer above the acoustic track, which is also used for line crossings;

[0092] FIG. 7 illustrates a cross-section showing the position of the material of the TC layer;

[0093] FIG. 8 illustrates the multilayer construction of the electrode structure in an enlarged view of a cross-section;

[0094] FIGS. 9a, 9b illustrate distances along a transversal direction in a top view of an enlarged section; and

[0095] FIG. 10 illustrates the use of the DMS filter in a duplexer.

[0096] FIG. 1 illustrates a top view onto central elements of the DMS filter DMSF. The DMS filter DMSF has eleven IDTs. Six IDTs are first IDTs IDT1. Five IDTs are second IDTs IDT2. All IDTs are arranged between a first acoustic reflector R1 and a second acoustic reflector R2. The IDTs and the reflectors establish a linear arrangement defining the acoustic track of the DMS filter. It is possible that each of the second IDTs IDT2 is arranged between two first IDTs IDT1. The distal first IDTs IDT1 are arranged between an acoustic reflector and a second IDT IDT2.

[0097] Each of the first IDTs is electrically connected to the first port P1. Each of the second IDTs is electrically connected to the second port P2. Reference potential of both ports can be ground potential. The first IDTs are connected to the first port with their first busbar B1 and first connection C1 (compare FIG. 3). The second IDTs are connected to the second port with their second busbar B2 and second connection C2. The second connections of the first IDTs can be electrically connected to ground potential and the first connections C1 of the second IDTs can also be electrically connected to the ground potential. The two-dimensional footprint of the IDTs and/or of the conductor segments supplying the IDTs with RF signals can have a symmetry with a symmetry line SL extending along the direction of extension of the electrode fingers and penetrating the central second IDT.

[0098] When three-dimensional structures are concerned, then the symmetry line SL corresponds to a mirror plane being perpendicular to the direction of propagation of the acoustic waves x. The transversal direction is denoted by y.

[0099] FIG. 1 shows a possible metal structure of the DMS structure that is established in a first layer L1 of the multilayer construction of the electrode structure (compare FIGS. 5 and 8).

[0100] FIG. 2 shows a cross-section illustrating the multilayer construction of the electrode structure. Specifically, FIG. 2 illustrates a cross-section AA corresponding to position AA illustrated in FIG. 5. The electrode structure ES is arranged on a piezoelectric material PM. The piezoelectric material PM can be arranged on a carrier substrate CS. The electrode structure ES with its multilayer construction MLC comprises a first inter IDT connection IIC1 and a second inter IDT connection IIC2. The first inter IDT connection IIC1 can have a lower metal strip LMS and an upper metal strip UMS. The second inter IDT connection can have a lower metal strip LMS and an upper metal strip UMS. LMS can be from a first photolithographically created metal layer L1 and UMS can be from a third photolithographically created metal layer L3.

[0101] LMS can be omitted to further reduce the size of the MLC, if UMS is present with a sufficiently high electrical conductivity.

[0102] Further, the electrode structure ES can have a third inter IDT connection IIC3 and a fourth inter IDT connection IIC4. The first and the second inter IDT connections IIC1, IIC2 can be provided to conduct an RF signal from the first port to the DMS and from the DMS to the second port. The third inter IDT connection and the fourth inter IDT connection IIC3, IIC4 can be provided to enable the connection to the ground potential. To electrically separate the ground connection from the input port and the output port, the dielectric material DM in the form of insulating patches IP is provided in a second dielectric layer L2 between the lower metal conductors C1 and the inner metal strips of the third inter IDT connection IIC3.

[0103] To minimize the area consumption and therefore the size of the construction, while minimizing the risk of connection failures of the photolithographically created multilayer structure MLC with inherent misalignment tolerances between the layers, IIC1 UMS partially overlaps the insulating patches IP of the dielectric material DM.

[0104] FIG. 3 illustrates the orientation of the IDTs, i.e. the location of the first busbars B1 and first connections C1 and of the second busbars B2 and second connections C2 with respect to the locations of the first port and of the second port. The first connections C1 of the first IDTs IDT1 electrically connect the first port P1 and the first busbars B1 of the first IDTs. The second connections C2 of the second IDTs IDT2 electrically connect the second port P2 and the second busbars B2 of the second IDTs. The second connections C2 of the first IDTs IDT1 and the first connections C1 of the second IDTs IDT2 are electrically connected to ground potential.

[0105] FIG. 4 illustrates the positions of the insulating patches IP comprising or consisting of the dielectric material DM at the places of conductor crossings to prevent an electrical short circuit between conductors electrically connected to ground and conductors electrically connected to the first or second port, respectively. The insulating patches can be created from a second photolithographic process structuring a second dielectric layer L2. Favorably, for reducing the size, the insulating patches can only overlap the connections C1, C2, but not the busbars B1, B2 and lower metal strips LMS IIC1, IIC2.

[0106] Correspondingly, FIG. 5 illustrates the positions of the inner metal strips IMS of the third inter IDT connection IIC3 and of the fourth inter IDT connection IIC4. Further, the positions of the lower metal strips LMS and upper metal strips UMS of the first and of the second inter IDT connections IIC1, IIC2 are also shown.

[0107] IIC1 UMS, IIC2 UMS, IIC3 IMS and IIC4 IMS can be created in a third photolithographic process structuring a third metal layer L3. Typically, L3 comprises a thick, well conducting metal layer to minimize ohmic resistance losses.

[0108] The lateral positions (y) of the lower metal strips and of the upper metal strips of an inter IDT connection IIC essentially coincide. However, it is possible that the inner metal strips and the upper metal strips are arranged at the same vertical level and consist of material of the same layer L3, which simplifies the manufacturing steps.

[0109] Position AA illustrates the location of the cross-section shown in FIG. 2.

[0110] FIG. 6 illustrates the possibility of arranging material of a TC layer TCL above the acoustic track. The material of the TC layer can comprise a rectangular main patch RMP and one rectangular smaller patch RSP per IDT. The rectangular smaller patch RSP is additionally taking the role of the DM, IP of FIG. 4 and so enables the conductor crossing without the need for an additional dielectric layer.

[0111] FIG. 7 illustrates a cross-section of the material system at location BB shown in FIG. 6. The material of the TC layer TCL is arranged above the material of the electrode fingers EF.

[0112] FIG. 8 illustrates the layer construction of the electrode structure comprising the first layer L1 in which the electrode fingers can be structured, the second layer L2 which comprises the dielectric material of the insulating patches and advantageously at the same time the TC function and the third layer L3 comprising the upper metal strips and the inner metal strips. The first layer can be directly arranged on the piezoelectric material PM. The piezoelectric material can be arranged on a carrier substrate CS.

[0113] However, it is also possible that further material of a TC layer is arranged between the carrier substrate CS and the piezoelectric material and/or between the piezoelectric material PM and the first layer L1 or above the third layer or above the first layer.

[0114] FIG. 9a illustrates characteristic distances in the lateral direction y. d1 denotes the distance between the lateral outer position of the busbars of the IDTs and the third inter IDT connection IIC3. d3 denotes the transversal distance between the upper metal strip and the inner metal strip. w2 denotes the width of the inner metal strip. w4 denotes the width of the upper metal strip. o1 denotes the overlap between the upper metal strip and the insulating patches. The insulating patches IP of the dielectric material DM overlap at least partially with the upper metal strip UMS.

[0115] FIG. 9b illustrates characteristic distances in the lateral direction y. d1 denotes the distance between the lateral outer position of the bus bars of the IDTs and the third inter IDT connection IIC3. d3 denotes the transversal distance between the upper metal strip and the inner metal strip. w2 denotes the width of the inner metal strip. w4 denotes the width of the upper metal strip. o1 denotes the overlap between the upper metal strip and the insulating patches. The insulating patches IP of the dielectric material DM do not overlap with the lower metal strip LMS of the first inter IDT connection IIC1 but—at least partially—with the upper metal strip UMS.

[0116] Compared to the electrode structure shown in FIG. 9a the insulating patches IP of the dielectric material DM have a reduced extension in the transversal direction.

[0117] FIG. 10 illustrates a basic circuit topology of a duplexer DU. The duplexer DU comprises a transmission filter TXF and a reception filter RXF. The transmission filter TXF usually is connected between a transmission port and an antenna port connected to an antenna AN. The reception filter RXF is typically connected between a reception port and the antenna port. The transmission filter TXF and the reception filter RXF base on a ladder-type like circuit topology having a signal path with series resonators SR electrically connected in series between an input port and an output port. Further, parallel paths comprise parallel resonators PR electrically connecting the signal path to a ground potential.

[0118] In order to match the frequency-dependent impedances of the reception filter RXF, the transmission filter TXF and/or the antenna, an impedance matching circuit IMC can be connected between the transmission filter TXF and the reception filter RXF, e.g. at the antenna port.

[0119] Between the ladder-type like circuit topology of the reception filter RXF and the filters output port a DMS filter DMSF is arranged and electrically connected.

[0120] For the reception filter RXF the ladder-type like topology provides good power durability and the DMS Filter DMSF enhances the insulation and selection levels while reducing chip space requirements.

LIST OF REFERENCE SIGNS

[0121] AN: antenna

[0122] B1, B2: first, second busbar of an IDT

[0123] C1, C2: first, second connection of an IDT

[0124] CS: carrier substrate

[0125] d1, d3: distances

[0126] DM: dielectric material

[0127] DMSF: DMS filter

[0128] DU: duplexer

[0129] EF: electrode finger

[0130] ES: electrode structure

[0131] IDT: interdigital transducer

[0132] IDT1 first IDT

[0133] IDT2: second interdigital transducer

[0134] IIC1, IIC2: first, second inter IDT connection

[0135] IIC3, IIC4: third, fourth inter IDT connection

[0136] IMC: impedance matching circuit

[0137] IMP: inner metal strip

[0138] IP: insulating patch

[0139] L1, L2, L3: first, second, third layer

[0140] LMS: lower metal strip

[0141] R1: first acoustic reflector

[0142] R2: second acoustic reflector

[0143] MLC: multilayer construction

[0144] o1, o2: overlap widths

[0145] P1: first port

[0146] P2: second port

[0147] PM: piezoelectric material

[0148] PR: parallel resonator

[0149] RMP: rectangular major patch

[0150] RSP: rectangular small patch

[0151] RXF: reception filter

[0152] SL: symmetry line

[0153] SR: series resonator

[0154] TCL: TC layer (Temperature Compensation)

[0155] TXF: transmission filter

[0156] UMS: upper metal strip

[0157] w2, w4: strip widths

[0158] x: direction of propagation of the SAW

[0159] y: transversal direction

[0160] z: vertical direction