Temperature sensor

Abstract

A temperature sensor supplying a measurement signal varying linearly to within 10% as a function of the temperature at least over a temperature range, including an oscillator supplied by a supply voltage and supplying a first oscillating signal, said oscillator including first MOS transistors, the voltage at each internal node of the oscillator having a dynamic range equal to the supply voltage, the measuring signal corresponding to the supply voltage.

Claims

1. A temperature sensor supplying a measurement signal of the temperature, comprising a controllable current source, an oscillator and a circuit controlling the controllable current source configured to control the equivalent resistance of the oscillator to be equal to a reference resistance, the oscillator being supplied by the controllable current source at a first node having a supply voltage, the oscillator supplying a first oscillating voltage having a dynamic range equal to the supply voltage, the measuring signal corresponding to the supply voltage.

2. The temperature sensor according to claim 1, wherein the controllable current source comprises a first MOS transistor whose source is configured to be coupled to a source of a high reference potential, whose drain supplies the supply voltage to the first node, and whose gate is controlled by the control circuit.

3. The temperature sensor according to claim 1, comprising an analog-digital converter receiving the supply voltage and supplying a converted digital signal to the control circuit, the control circuit being configured to select a resistance among several resistances from the converted digital signal, said resistances being substantially equal to the reference resistance in different temperature subranges of a temperature range.

4. The temperature sensor according to claim 3, comprising a follower circuit receiving the supply voltage and outputting a copy of the supply voltage and wherein the analog-digital converter is coupled to the output of the follower circuit.

5. The temperature sensor according to claim 2, wherein the control circuit and the controllable current source comprise a current mirror comprising the first MOS transistor and a second MOS transistor, the control circuit further comprising an operational amplifier whose output is coupled to the gates of the first and second MOS transistors, and wherein the first node is coupled to a first input of the operational amplifier and wherein the control circuit comprises a circuit supplying a reference voltage to a second input of the operational amplifier, a current passing through the second MOS transistor, the supply circuit being configured to supply the reference voltage equal to the product of said current and the reference resistance.

6. The temperature sensor according to claim 5, wherein the circuit supplying the reference voltage is configured to couple the second input to one of said resistances from a selection signal.

7. The temperature sensor according to claim 6, wherein the control circuit comprises a digital circuit receiving the converted digital signal and determining the selection signal from the converted digital signal in order to select the resistance, among the resistances, substantially equal to the reference resistance.

8. The temperature sensor according to claim 6, wherein the circuit supplying the reference voltage comprises first resistors, the first resistors having resistances substantially equal to the reference resistance in different temperature subranges of a temperature range, and a demultiplexer configured to couple one of the first resistors to the second input from the selection signal.

9. The temperature sensor according to claim 6, wherein the circuit supplying the reference voltage comprises a second resistor having a resistance with a positive temperature coefficient coupled to a third resistor having a resistance with a negative temperature coefficient and a circuit configured to modify the ratio between the current circulating in the second resistor and the current circulating in the third resistor.

10. The temperature sensor according to claim 2, wherein the oscillator comprises third MOS transistors.

11. The temperature sensor according to claim 1, wherein the first oscillating signal oscillates at a first oscillation frequency, the temperature sensor comprising a frequency divider circuit receiving the first oscillating signal or a second signal oscillating at the first oscillation frequency and supplying a third signal oscillating at a second oscillation frequency that is a sub-multiple of the first oscillation frequency.

12. The temperature sensor according to claim 11, wherein the analog-digital converter is paced by the third oscillating signal.

13. The temperature sensor according to claim 1, wherein the oscillator is a ring oscillator.

14. The temperature sensor according to claim 13, wherein the voltage at each internal node of the oscillator has a dynamic equal to the supply voltage of the oscillator.

15. The temperature sensor according to claim 10, wherein the third MOS transistors are configured to have a current passing through them varying linearly to within 10% as a function of the temperature over a temperature range, the sensor being configured to supply the measuring signal varying linearly to within 10% as a function of the temperature at least over the temperature range.

16. The temperature sensor according to claim 14, wherein the temperature range varies from −40° C. to 250° C.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

(2) FIG. 1 partially and schematically shows one embodiment of a temperature sensor;

(3) FIG. 2 shows a more detailed embodiment of the temperature sensor of FIG. 1;

(4) FIG. 3 shows an embodiment of an oscillator;

(5) FIG. 4 shows variation curves of resistances as a function of the temperature;

(6) FIG. 5 shows a more detailed embodiment of the device shown in FIG. 3;

(7) FIG. 6 shows an evolution curve of the supply voltage of the oscillator of the device shown in FIG. 5 as a function of the temperature;

(8) FIG. 7 shows a variant of the oscillator of the device shown in FIG. 3; and

(9) FIG. 8 shows a variant of another part of the device shown in FIG. 3.

DESCRIPTION OF EMBODIMENTS

(10) Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%. Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements. Additionally, in the remainder of the description, the voltages are referenced with respect to a low reference potential, for example the ground potential, taken as being equal to 0 V. Furthermore, in the remainder of the description, the same reference is used to designate a resistor and the resistance of said resistor. Additionally, a “binary signal” refers to a signal that alternates between a first constant state, for example a low state, denoted “0”, and a second constant state level, for example a high state, denoted “1”. The high and low states of different binary signals of a same electronic circuit can be different. In practice, the binary signals can correspond to voltages or currents that may not be perfectly constant in the high or low state.

(11) FIG. 1 shows an embodiment of a temperature sensor 10. The temperature sensor 10 comprises a voltage-controlled oscillator 12 (VCO). The oscillator 12 is coupled, preferably connected, to a source GND of a low reference potential, for example the ground. The oscillator 12 is further coupled, preferably connected, to a node N.sub.1 receiving a supply voltage V.sub.ddosc of the oscillator 12. The oscillator 12 supplies an oscillating signal V.sub.osc at an oscillation frequency f, for example a binary voltage alternating between two levels at the frequency f. The sensor 10 further comprises a circuit 14 supplying the supply voltage V.sub.ddosc comprising a controllable current source supplying the oscillator. The controllable current source for example comprises an insulated-gate field-effect transistor T.sub.1, also called MOS transistor, for example P-channel, the drain of which is coupled to the node N.sub.1 and the source of which is coupled to a source V.sub.dd of a high reference potential. The circuit 14 further comprises a circuit 16 controlling the controllable current source, for example supplying a control signal COM to the gate of the transistor T.sub.1. The temperature sensor 10 further comprises an adaptation circuit 18 receiving the supply voltage V.sub.ddosc at the node N.sub.1 and supplying a signal ST.

(12) The oscillator 12 is configured to supply the oscillating signal V.sub.osc with a dynamic range equal to the supply voltage V.sub.ddosc. In an embodiment, the circuit 16 controlling the controllable current source is configured to control the equivalent resistance of the oscillator 12 to be equal to a reference resistance. The oscillator 12 is therefore controlled so that the oscillation frequency f remains substantially constant. With such an architecture, the inventors have shown that the variations of the supply voltage V.sub.ddosc are representative of the variations of the temperature.

(13) The oscillator 12 is an oscillator comprising MOS transistors, in particular P-channel MOS transistors and/or N-channel MOS transistors. The oscillator 12 is for example a ring oscillator. The oscillator 12 can further comprise other electronic components, for example capacitors. The electronic components of the oscillator 12 are connected to one another such that, for each internal node of the oscillator 12, that is to say, each node between two electronic components of the oscillator 12, the voltage at the node varies during operation over a voltage range substantially equal to the supply voltage V.sub.ddosc. For such an oscillator 12, the inventors have shown that the supply voltage V.sub.ddosc varies substantially linearly with the temperature over a wide temperature range, in particular at least over the range varying from −40° C. to 250° C.

(14) The signal ST, supplied by the adaptation circuit 18 and obtained from the supply voltage V.sub.ddosc, is an analog or digital signal that varies substantially linearly as a function of the temperature. According to one embodiment, the adaptation circuit 18 comprises an analog-digital converter. According to one embodiment, the adaptation circuit 18 comprises a follower circuit. The adaptation circuit 18 may not be present, the signal ST then being equal to the supply voltage V.sub.ddosc. The signal ST can be used by another electronic circuit and/or can be used by the temperature sensor 10 itself. The temperature sensor 10 therefore supplies both the signal ST, which varies substantially linearly with the temperature, and the signal V.sub.osc, which oscillates at the oscillation frequency f.

(15) FIG. 2 shows a more detailed embodiment of the device 10 shown in FIG. 1, in which the control circuit 16 comprises a circuit 20 for supplying a reference signal REF to a node N.sub.2. The circuit 20 further comprises an operational amplifier 24 receiving the signal V.sub.ddosc at the non-inverting input (+), and the signal REF at the inverting input (−), and supplying the control signal COM to the gate of the transistor T.sub.1 so that the signals V.sub.ddosc and REF become the same. The device 10 further comprises an active input current mirror 26 comprising the operational amplifier 24, the transistor T.sub.1 and a MOS transistor T.sub.2, in particular P-channel, the source of which is coupled to the source Vdd of the high reference potential, the drain of which is coupled to the node N.sub.2 and the gate of which is coupled to the gate of the transistor T1.

(16) The circuit 20 supplying the reference signal REF comprises temperature-compensated resistors R.sub.1 to R.sub.N, where N is an integer, for example between 1 and 6. The circuit 20 further comprises a demultiplexer 28 (DEMUX), each resistor R.sub.1 to R.sub.N comprising a first terminal coupled, preferably connected, to the source GND of the low reference potential and a second terminal coupled, preferably connected, to an input of the demultiplexer 28. The demultiplexer 28 is configured to connect one of the resistors R.sub.1 to R.sub.N to the node N.sub.2 as a function of a selection signal SEL.

(17) The adaptation circuit 18 comprises, in the present embodiment, a follower circuit 30 coupled to an analog-digital converter 32 (ADC), the input of the follower circuit 30 being coupled, preferably connected, to the node N1, the output of the follower circuit 30 being coupled, preferably connected, to the input of the analog-digital converter 32, and the analog-digital converter 32 supplying the signal ST.

(18) The control circuit 16 further comprises a digital selection circuit 34 for one of the resistances R.sub.1 to R.sub.N, receiving the signal ST and supplying a control signal SEL to the demultiplexer 28. The digital selection circuit 34 can be supplied by a source for supplying a high reference potential, not shown, different from the source V.sub.dd.

(19) Each resistor R.sub.1 to R.sub.N is a resistor whose resistance varies as a function of the temperature, for example successively having a growth phase as a function of the temperature, passing through a maximum and a decrease phase as a function of the temperature. According to one embodiment, the maximum resistances of the resistors R.sub.1 to R.sub.N are obtained for increasing temperatures, that is to say, for any pair i and j varying from 1 to N with i strictly less than j, the temperature at which the maximum resistance of the resistor R.sub.i is obtained is strictly less than the temperature at which the maximum resistance of the resistor R.sub.j is obtained. According to one embodiment, each resistor R.sub.1 to R.sub.N comprises a resistor with a negative temperature coefficient in series with a resistor with a positive temperature coefficient.

(20) FIG. 3 shows an embodiment of the oscillator 12 in which the oscillator 12 corresponds to a ring oscillator comprising a succession of stages E.sub.1 to E.sub.M, where M is an odd integer at least equal to 3, M being equal to 5 in the embodiment shown in FIG. 3. Each stage E.sub.j, j varying from 1 to M, comprises an inverter INV.sub.j and a capacitor C.sub.j. The input of the inverter INV.sub.j of the stage E.sub.j is coupled, preferably connected, to the output of the inverter INV.sub.k of the stage.

(21) E.sub.k, where k is greater than or equal to 1 and strictly less than j and j is less than or equal to N. The input of the inverter INV.sub.1 of the stage E.sub.1 is coupled, preferably connected, to the output of the inverter INV.sub.M of the stage E.sub.M. The capacitor C.sub.j of the stage E.sub.j comprises a first electrode coupled, preferably connected, to the output of the inverter INV.sub.j and a second electrode coupled, preferably connected, to the source BND of the low reference potential. According to one embodiment, the inverter INV.sub.j comprises a MOS transistor TUP.sub.j, for example P-channel, whose source is coupled, preferably connected, to the node N.sub.1, whose drain is coupled, preferably connected, to the output of the inverter INV.sub.j and whose gate is coupled, preferably connected, to the input of the inverter INV.sub.j. According to one embodiment, the inverter INV.sub.j comprises a MOS transistor TDOWN.sub.j, for example N-channel, whose source is coupled, preferably connected, to the source GND of the low reference potential, whose drain is coupled, preferably connected, to the output of the inverter INV.sub.j and whose gate is coupled, preferably connected, to the input of the inverter INV.sub.j. The capacitors C.sub.j can correspond to internal capacitances of the MOS transistors or to separate electronic components. The capacitances of the capacitors C.sub.j can be identical.

(22) FIG. 4 shows evolution curves C.sub.1 to C.sub.6 of the resistance R of resistors R.sub.1 to R.sub.6 of the circuit 20 as a function of the temperature T. Each curve C.sub.1 to C.sub.6 is bell-shaped, the maxima of the resistances R.sub.1 to R.sub.6 being substantially equal. The curves are offset in temperature relative to one another such that the maximums of the curves C.sub.1 to C.sub.6 are substantially evenly distributed over the temperature range from −50° C. to 250° C.

(23) The operation of the device 10 shown in FIG. 3 is as follows. The signal ST, supplied by the converter 32, corresponds to the analog/digital conversion of the voltage V.sub.ddosc. The voltage V.sub.ddosc varies substantially linearly with the temperature; the digital signal ST also varies substantially linearly with the temperature. The selection circuit 34 supplies the signal SEL for the selection of one of the resistances R.sub.1 to R.sub.N as a function of the temperature indicated by the signal ST. According to one embodiment, the selection circuit 34 comprises a memory in which thresholds are stored delimiting N temperature ranges RT.sub.1 to RT.sub.N, successive and adjacent, each temperature range RT.sub.i, for i varying from 1 to N, being the range in which the resistance R.sub.i passes through its maximum. Preferably, each temperature range RT.sub.i is substantially centered on the temperature corresponding to the maximum of the associated resistance R.sub.i. The selection circuit 34 is then configured to compare the signal ST to the thresholds and to supply a selection signal SEL of the resistance R.sub.i associated with the temperature range RT.sub.i to which the signal SEL belongs. The demultiplexer 28 then couples the selected resistance R.sub.i to the node N.sub.2. According to one embodiment, the number N of resistors R.sub.i and the expanse of each temperature range RT.sub.i are chosen such that the resistance R.sub.i associated with the temperature range RT.sub.i varies relative to the maximum resistance by less than 2%, preferably less than 0.5%, over the temperature range RT.sub.i. As a result, the resistance coupled to the node N.sub.2 is substantially constant to within 2%, preferably to within 0.5%, over a wide temperature range, in particular from −40° C. to 250° C.

(24) The equivalent resistance R.sub.dcosc of the oscillator 12 is given by the following relationship 1):
R.sub.dcosc=V.sub.ddoscI.sub.ddosc  [Math 1]

(25) The voltage at each internal node of the oscillator 12 varying during operation over a voltage range substantially equal to the supply voltage V.sub.ddosc, the power consumed by the oscillator 12 follows the following relationship 2), calling C.sub.osc the equivalent capacity of the oscillator 12:
P=C.sub.oscfV.sub.ddosc.sup.2  [Math 2]

(26) As an example, for the oscillator 12 shown in FIG. 3, the equivalent capacity C.sub.osc of the oscillator 12 is equal to M*C.sub.1. The frequency f of the oscillating signal supplied by the oscillator 12 can then be expressed as a function of the DC resistance R.sub.dcosc of the oscillator 12 according to the following relationship 3):

(27) $\begin{array}{cc}f=\frac{1}{R_{\mathrm{dcosc}}{C}_{\mathrm{osc}}}& \left[\mathrm{Math}3\right]\end{array}$

(28) The operational amplifier 24 tends to keep the voltage REF at the node N.sub.2 and the voltage V.sub.ddosc at the node N.sub.1 equal, and therefore to keep the current I.sub.ddosc and the current at the node N.sub.2 equal. Everything happens as if the current mirror at the active input 26 forces the resistance R.sub.dcosc to be equal to the resistance R.sub.i coupled to the node N.sub.2, selected among the resistances R.sub.1 to R.sub.N. As a result, since the resistance coupled to the node N.sub.2 is substantially constant irrespective of the temperature over an extended temperature range, in particular from −40° C. to 250° C., the resistance R.sub.ddosc and therefore the frequency f of the oscillator 12 remains substantially constant irrespective of the temperature over the extended temperature range, in particular from −40° C. to 250° C. This allows the use of the signal V.sub.osc at a stable frequency in applications in which the temperature can vary significantly, in particular in the fields of drilling, monitoring industrial processes or monitoring operating parameters of engines in aeronautic or automotive applications.

(29) Another advantage is that the number of calibration points necessary to calibrate the oscillator 12 is reduced. Indeed, a calibration with two points is sufficient to calibrate the oscillator 12. The duration of the tests of the oscillator 12 is therefore reduced. The production cost of the oscillator 12 is therefore reduced.

(30) FIG. 5 shows a more detailed embodiment of the device 10 of FIG. 3. In FIG. 5, each resistor R.sub.i, i varying from 1 to N, comprises a resistor RCTP.sub.i with a positive temperature coefficient in series with a resistor RCTN.sub.i with a negative temperature coefficient.

(31) In the present embodiment, the mirror current circuit 26 further makes it possible to calibrate the oscillation frequency of the oscillator 12. The mirror current circuit 26 comprises a number H of branches A, i varying form 1 to H, mounted in parallel between the inverter input (−) of the operational amplifier 24 and the source V.sub.dd of the high reference potential and H branches A′.sub.i, i varying from 1 to H, mounted in parallel between the node N.sub.2 and the source V.sub.dd of the high reference potential. The number H can vary from 1 to 2.sup.N with N being able to vary from 1 to 10, for example. Each branch A.sub.i can comprise a current source made for example by a MOS transistor T.sub.1,i, for example P-channel, still on, whose voltage value on the gate sets the value of the current passing through it in series with a MOS transistor T.sub.3,i, for example P-channel. Each branch A′.sub.i can comprise a current source for example made by a MOS transistor T.sub.2,i, for example P-channel, still on, whose voltage value on the gate sets the value of the current passing through it in series with a MOS transistor T.sub.4,i, for example P-channel. The output of the operational amplifier 24 is coupled, preferably connected, to the gates of the transistors T.sub.1,1 to T.sub.1,H and T.sub.2,1 to T.sub.2,H. The gates of the transistors T.sub.3,1 to T.sub.3,H are respectively controlled by binary controls a1 to a.sub.O and the gates of the transistors T.sub.4,1 to T.sub.4,H are respectively controlled by binary controls b.sub.1 to b.sub.O. The binary commands a.sub.1 to a.sub.O and b.sub.1 to b.sub.O make it possible to select some of the current sources among the transistors T.sub.1,1 to T.sub.1,H and some of the current sources among the transistors T.sub.2,1 to T.sub.2,H, which makes it possible to adjust the current ratio passing through the selected resistor R.sub.i and the oscillator 12. This makes it possible to calibrate the frequency of the oscillator. The control circuit 16 further comprises a capacitor C.sub.comp, one electrode of which is coupled, preferably connected, to the gates of the transistors T.sub.1,i and T.sub.2,i and the other electrode of which is coupled, preferably connected, to the inverting input (−) of the operational amplifier 24.

(32) Furthermore, FIG. 5 shows an embodiment of the follower circuit 30 in which the follower circuit 30 comprises an operational amplifier 36 coupled, for its power source, to the source V.sub.dd of the high reference potential, or to another source of a high reference potential, and to the source GND of the low reference potential, receiving the voltage V.sub.ddosc and supplying the voltage V′.sub.ddosc, which is a copy of the voltage V.sub.ddosc. The output of the operational amplifier 36 is coupled, preferably connected, to the inverting input (V−) of the operational amplifier 36. The follower circuit 30 further comprises a resistor R.sub.S, one terminal of which is coupled, preferably connected, to the node N.sub.1 and the other terminal of which is coupled, preferably connected, to the noninverting input (+) of the operational amplifier 36 and a capacitor C.sub.S whereof one electrode is coupled, preferably connected, to the source GND of the low reference potential and the other electrode of which is coupled, preferably connected, to the noninverting input (+) of the operational amplifier 36.

(33) According to one embodiment, the supply circuit 18 further comprises a level conversion circuit 38 coupled, for its power source, to the source V.sub.dd of the high reference potential, or to another source of a high reference potential, and to the source GND of the low reference potential, comprising an input receiving the oscillating signal V.sub.osc supplied by the oscillator 12 and an output supplying an oscillating signal V′.sub.osc. The level conversion circuit 38 further comprises an input coupled, preferably connected, to the output of the follower circuit 30 and receiving the signal V′.sub.ddosc. The level conversion circuit 38 supplies the signal V′.sub.osc at the same frequency f as the oscillating signal V.sub.osc but with a different dynamic range, which in particular depends on the signal V′.sub.ddosc. In particular, when the signal V.sub.osc is a binary signal, the signal V′.sub.osc is a binary signal follows [sic] the signal V.sub.osc with different levels “0” and “1”.

(34) The adaptation circuit 18 further comprises a frequency divider circuit 40 adapted to the case where the signal V′.sub.osc is binary. The circuit 18 comprises two inverters 42, 44 and three D flip-flops 46, 48, 50. The input of the first inverter 42 receives the signal V′.sub.osc. The output of the first inverter 42 is coupled, preferably connected, to the input of the second inverter 44. The output of the second inverter 44 is coupled, preferably connected, to the clock input of the first D flip-flop 46. The noninverted output of the first D flip-flop 46 is coupled, preferably connected, to the clock input of the second D flip-flop 48. The inverted output of the first D flip-flop 46 is coupled, preferably connected, to the data input of the first D flip-flop 46. The noninverted output of the second D flip-flop 48 is coupled, preferably connected, to the clock input of the third D flip-flop 50. The inverted output of the second D flip-flop 48 is coupled, preferably connected, to the data input of the second D flip-flop 48. The inverted output of the third D flip-flop 50 is coupled, preferably connected, to the data input of the third D flip-flop 50. The noninverted output of the third D flip-flop 50 supplies a signal Clk. The signal Clk is a binary signal that oscillates at a frequency equal to f divided by 2.sup.Q, where Q is the number of D flip-flops (Q being equal to three in FIG. 3).

(35) The analog-digital converter 32 receives the voltage V′.sub.ddosc on an input and is paced by the signal Clk. In the present embodiment, the analog-digital converter 32 supplies the digital signal ST, corresponding to the analog/digital conversion of the voltage V′.sub.ddosc, encoded for example on 5 bits ST<0>, ST<1>, ST<2>, ST<3> and ST<4>.

(36) According to one embodiment, the selection circuit 34 comprises a circuit 52 receiving the digital signal ST and supplying an update signal encoded on one bit. The circuit 52 is configured to supply a pulse of the update signal when the range of temperatures designated by the digital signal ST changes and optionally when one or several additional conditions is(are) met. To that end, the circuit 52 can compare the digital signal ST to thresholds. According to one embodiment, for each bound of a range of temperatures, two comparison thresholds can be used, a first comparison threshold when the digital signal ST is increasing and a second comparison threshold when the digital signal ST is decreasing. This makes it possible to obtain a hysteresis effect in order to avoid the unwanted emission of successive pulses of the update signal for small oscillations of the signal ST around a threshold. As a variant, the circuit 52 only supplies a pulse of the update signal when the digital signal continuously designates a new temperature range during a given duration.

(37) The selection circuit 34 further comprises a control circuit 54 receiving the digital signal ST and the update signal and supplying the selection signal SEL. According to one embodiment, the control circuit 52 is configured to determine a new value of the selection signal SEL from the last value of the signal ST received upon receiving a pulse from the update signal.

(38) According to the embodiment shown in FIG. 5, the device 10 further comprises resistors R′.sub.1 to R′.sub.N-1 and a demultiplexer 56. The N−1 resistors R′.sub.1 to R′.sub.N-1 are equal to N−1 of the N resistors R.sub.1 to R.sub.N. The resistors R′.sub.1 to R′.sub.N-1 and the oscillator 12 are coupled, preferably connected, to the demultiplexer 56. The demultiplexer 56 is controlled by a constant signal SEL′ so as to continuously couple the node N.sub.1 to the inverter input (−) of the operational amplifier 24, such that the resistors R′.sub.1 to R′.sub.N are never connected to the inverter input of the amplifier 24. The presence of the demultiplexer 56 makes it possible to ensure that the leak currents connected to the demultiplexers 28, 56 at the inverter and non-inverter inputs of the operational amplifier 24 are as close as possible.

(39) FIG. 6 shows a curve C, obtained by simulation, of the evolution of the voltage V.sub.ddosc of the temperature sensor 10 shown in FIG. 5 as a function of the temperature T. Curve C′ in dotted lines shows the curve that would be obtained if the voltage V.sub.ddosc were to vary perfectly linearly as a function of the temperature T. As shown in FIG. 6, curves C and C′ are practically combined from −50° C. to 250° C. such that the use of the voltage V.sub.ddosc as signal representative of the temperature over a wide range of temperatures is relevant.

(40) FIG. 7 shows another embodiment of the oscillator 12 in which the oscillator 12 comprises two branches B.sub.1 and B.sub.2, each branch B.sub.1, B.sub.2 comprising two inverters INV in series powered by the voltage V.sub.ddosc. The oscillator 12 further comprises a latch RS whose input R is coupled, preferably connected, to the output of the first branch B.sub.1, whose input S is coupled, preferably connected, to the output of the second inverter INV of the second branch B.sub.2, whose output Q is coupled, preferably connected, to the input of the first inverter INV of the branch B.sub.1 and whose output Qb is coupled, preferably connected, to the input of the first inverter INV of the branch B.sub.2. The signal V.sub.osc supplied to the outputs Q and the complementary signal supplied to the output Qb can be transmitted to amplifiers AMP. The oscillator 12 can comprise capacitors CO at the input and/or output of the inverters INV.

(41) FIG. 8 shows another embodiment of the circuit 20 for supplying the reference signal REF to the node N.sub.2 in which the circuit 20 comprises a resistor R.sub.TCN having a resistance with a negative temperature coefficient mounted between a node N.sub.3 and a node N.sub.4 and a resistor R.sub.TCP having a resistant with a positive temperature coefficient mounted between the node N.sub.4 and the source GND of the low reference potential. The circuit 20 further comprises P branches B′.sub.i, i varying from 1 to P, mounted in parallel between the node N.sub.2 and the node N.sub.4 and Q branches B″.sub.k, k varying from 1 to Q, mounted in parallel between the node N.sub.2 and the node N.sub.4. The branches B′.sub.1 to B′.sub.P and B″.sub.1 to B″.sub.Q make it possible to control the ratio between the current circulating in the resistor R.sub.TCN and the current circulating in the resistor R.sub.TCP. Each branch B′.sub.i can comprise a current source made for example by a MOS transistor T.sub.5,i, for example P-channel, still on, whose voltage value on the gate sets the value of the current passing through it in series with a MOS transistor T.sub.6,i, for example P-channel. Each branch B′.sub.i can comprise a MOS transistor T.sub.7,i, for example P-channel, still on, whose voltage value on the gate sets the value of the current passing through it in series with a MOS transistor T.sub.8,i, for example P-channel. The gates of the transistors T.sub.6,1 to T.sub.6,P and T.sub.8,1 to T.sub.8,Q are controlled from the signal SEL. When the transistor T.sub.6,i is placed in the on state, it is configured to allow a current to pass equal to a.sub.iI. When the transistor T.sub.8,k is placed in the on state, it is configured to allow a current to pass equal to b.sub.kI. As a result, the equivalent resistance R.sub.EQ of the circuit 20 is given by the following relationship 4):
R.sub.EQ=R.sub.TCNΣa.sub.i+R.sub.TCP(Σa.sub.i+Σb.sub.k)  [Math 4]

(42) The value of the resistance R.sub.EQ coupled to the node N.sub.2 can therefore be controlled by modifying the number of transistors T.sub.6,i that are in the on state among the P transistors T.sub.6,1 to T.sub.6,P and/or the number of transistors T.sub.8,k that are in the on state among the Q transistors T.sub.8,1 to T.sub.8,Q. The circuit 20 of FIG. 8 advantageously has reduced leak currents.

(43) Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. In particular, architectures of the circuit 16 controlling the controllable current source, controlling the equivalent resistance of the oscillator 12 to be equal to a reference resistance, other than the one shown in FIG. 2 can be implemented. Moreover, in the previously disclosed embodiments, the circuit 20 supplying the reference signal REF comprises several resistors. According to another embodiment, the circuit 20 supplying the reference signal REF comprises a signal resistor having a substantially constant resistance over the temperature range and the demultiplexer 28 and the selection circuit 34 may not be present. Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.