Circuit for detecting circuit defects and for preventing overvoltages in controllers

Abstract

An electrical circuit for detecting circuit defects and/or for preventing overvoltages in controllers. The electrical circuit including a power controller circuit, encompassing a first transistor, a control loop including an operation amplifier and a first reference voltage source, and feedback resistors, and an overvoltage suppression circuit, encompassing a second transistor, a control loop including an operation amplifier and a reference voltage source, and feedback resistors, the power controller circuit being provided to make a voltage available for the overvoltage suppression circuit and the overvoltage suppression circuit being provided to make a protected voltage available.

Claims

1. An electrical circuit for detecting circuit defects and/or for preventing overvoltages in controllers, comprising: a power controller circuit including a first transistor, a control loop including an operation amplifier and a first reference voltage source, and feedback resistors; an overvoltage suppression circuit including a second transistor, a control loop including a second operation amplifier and a second reference voltage source, and second feedback resistors; and an undervoltage detection comparator including a variable reference source for detecting a defect in the first and second reference voltage sources, wherein the power controller circuit is configured to make a voltage available for the overvoltage suppression circuit, and the overvoltage suppression circuit is configured to make a protected voltage available.

2. The electrical circuit as recited in claim 1, further comprising: a circuit for detecting an undervoltage of the power controller, including a second comparator configured to compare a voltage of the second reference voltage source to a voltage obtained via the protected voltage.

3. The electrical circuit as recited in claim 2, wherein the second comparator, which is configured to detecting the undervoltage, is configured to output a binary value representing the undervoltage.

4. The electrical circuit as recited in claim 1, further comprising: a circuit configured to detect an undervoltage of the power controller, including two comparators, a comparison of a voltage obtained via a voltage of the first reference voltage source or the second reference voltage source to a voltage obtained using the protected voltage being provided via the two comparators.

5. The electrical circuit as recited in claim 4, wherein the two comparators are configured to output a binary value representing the undervoltage.

6. The electrical circuit as recited in claim 5, further comprising: a logic AND-gate configured to link binary values reflecting the undervoltage.

7. The electrical circuit as recited in claim 1, further comprising: a digital portion at which a provision of the protected voltage is provided.

8. The electrical circuit as recited in claim 7, wherein the digital portion includes inputs for receiving binary values and outputs for transmitting binary values.

9. The electrical circuit as recited in claim 1, wherein a supply of the first reference voltage source, the second reference voltage source, the power controller circuit, and the overvoltage suppression circuit, is provided using an external battery voltage.

10. A electrical circuit for detecting circuit defects and/or for preventing overvoltages in controllers, comprising: a power controller circuit including a first transistor, a control loop including an operation amplifier and a first reference voltage source, and feedback resistors; an overvoltage suppression circuit including a second transistor, a control loop including a second operation amplifier and a second reference voltage source, and second feedback resistors; wherein the power controller circuit is configured to make a voltage available for the overvoltage suppression circuit, and the overvoltage suppression circuit is configured to make a protected voltage available; and a third transistor, a gate terminal of the third transitory being connected to a source terminal of the second transistor, the third transistor configured to limit an overvoltage at a source terminal of the third transistor.

11. The electrical circuit as recited in claim 10, wherein an input of a first comparator is connected at the source terminal of the third transistor, the first comparator configured to detecting an overvoltage by comparing a limited voltage to a voltage of the second reference voltage source.

12. The electrical circuit as recited in claim 11, wherein the first comparator, which is configured to detect the overvoltage, is configured to output a binary value representing the overvoltage.

13. A electrical circuit for detecting circuit defects and/or for preventing overvoltages in controllers, comprising: a power controller circuit including a first transistor, a control loop including an operation amplifier and a first reference voltage source, and feedback resistors; an overvoltage suppression circuit including a second transistor, a control loop including a second operation amplifier and a second reference voltage source, and second feedback resistors; wherein the power controller circuit is configured to make a voltage available for the overvoltage suppression circuit, and the overvoltage suppression circuit is configured to make a protected voltage available; and a circuit configured to detect a defect in the first and second reference sources, which causes an overvoltage of the power controller or an undervoltage of a protection controller, including an undervoltage detection comparator having a variable reference source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are described in greater detail with reference to the figures and the following description.

(2) FIG. 1 shows a circuit according to an example embodiment of the present invention for detecting defects and for overvoltage suppression.

(3) FIG. 2 shows, in a flow chart, the value changes during a BIST phase implemented according to the example circuit according to the present invention.

(4) FIG. 3 shows one further specific example embodiment of the circuit according to the present invention, which enables a considerable distinction to be made between an overvoltage with respect to V.sub.DD_PWR and an undervoltage with respect to V.sub.DD_PROT due to a defect in the references.

(5) FIG. 4 shows a specific example embodiment of the circuit according to the present invention, which, as compared to the exemplary embodiment shown in FIG. 3, requires only one undervoltage comparator.

(6) FIG. 5 shows an alternative specific example embodiment of the circuit according to the present invention allowing for a switch-off mode/stand-by mode.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(7) In FIG. 1, an example circuit according to the present invention for detecting defects and for overvoltage suppression for a high-voltage BCD (bipolar, CMOS and DMOS) semiconductor method is represented, which is suitable for applications in the automotive field. An adaptation of the circuit to other semiconductor processes is also possible.

(8) The controller is supplied by a battery having voltage V.sub.BATT. The power controller contains high-voltage transistor MOS.sub.PWR, a control loop including operation amplifier OTA.sub.PWR and undervoltage band gap reference V.sub.REF1 as the reference voltage source, and high-resistance feedback resistors R.sub.1, R.sub.2 and R.sub.3. The power controller delivers voltage V.sub.DD_PWR for the overvoltage suppression circuit.

(9) The overvoltage suppression circuit contains high-voltage protection transistor MOS.sub.PROT, the control loop including operation amplifier OTA.sub.PROT and undervoltage band gap reference V.sub.REF2 as the reference voltage source, and high-resistance feedback resistors R.sub.4, R.sub.5 and R.sub.6. The overvoltage suppression circuit delivers protected voltage V.sub.DD_PROT to digital logic, represented by digital portion DT, and load circuits LOAD, CP.

(10) Charge pump CP supplied by voltage V.sub.DD_PROT delivers, for operation amplifiers OTA.sub.PWR and OTA.sub.PROT, a higher voltage V.sub.CP at a lower V.sub.BATT voltage, so that the voltage at the drain and source terminals of transistors MOS.sub.PWR and MOS.sub.PROT is limited only by way of their start-up resistors and load currents, and not by way of their control voltage at the gate.

(11) For better clarity of the circuit according to the present invention, the following relationships are given:
R.sub.2=R.sub.1*2085/1215  (1)
R.sub.3=R.sub.1*300/1215  (2)
R.sub.5=R.sub.4*288/1215  (3)
R.sub.6=R.sub.4*1897/1215  (4)
R.sub.8=R.sub.7*4670/1215  (5)
R.sub.9=R.sub.7*55/1215  (6)
V.sub.DD_PWR=V.sub.REF1*(3300+(BIST.sub.PWR*300))/1215  (7)
V.sub.DD_PROT=V.sub.DD_PWR for V.sub.DD_PWR<3.4 V  (8a)
V.sub.DD_PROT=V.sub.REF2*3400/1215 for V.sub.DD_PWR≥3.4 V  (8b)
V.sub.UV=V.sub.DD_PROT*1503/3400  (9)
V.sub.OV=(V.sub.DD_PWR+V.sub.DD_PROT)/(2+(4670/(1215+(BIST.sub.OV*55))))  (10)
FLAG.sub.UV=1 for V.sub.UV<V.sub.REF2  (11a)
FLAG.sub.UV=0 for V.sub.UV≥V.sub.REF2  (11b)
FLAG.sub.OV=0 for V.sub.OV<V.sub.REF2  (12a)
FLAG.sub.OV=1 for V.sub.OV≥V.sub.REF2  (12b)

(12) In the present case, a nominal value of 14 volts is assumed for parameter V.sub.BATT, a nominal value of >7 volts is assumed for parameter V.sub.CP representing the output voltage of the charge pump, a nominal value of 1.215 volts is assumed, in each case, for undervoltage band gap references V.sub.REF1 and V.sub.REF2 as reference voltages, a nominal value of 3.3 volts is assumed for regulated voltage V.sub.DD_PWR, a nominal value of 3.6 volts is assumed for regulated voltage V.sub.DD_PWR under BIST.sub.PWR, and a nominal value of 3.4 volts is assumed for controlled voltage V.sub.DD_PROT. Moreover, the nominal value of V.sub.DD_PROT for activating FLAG.sub.UV must be less than 2.75 volts. In order to activate FLAG.sub.OV, the average ((V.sub.DD_PWR+V.sub.DD_PROT)/2) must be greater than 3.55 volts, whereas, in order to activate FLAG.sub.OV in BIST.sub.OV, the average ((V.sub.DD_PWR+V.sub.DD_PROT)/2) must be greater than 3.45 volts. The range of the operating voltage for digital logic DT and the load circuits is in the range from 2.7 volts to 3.6 volts.

(13) In the present case, an undervoltage of the controller is detected by comparator COMP.sub.UV and reference V.sub.REF2, in that the FLAG.sub.UV is set to the value 1 when voltage V.sub.DD_PROT is lower than its threshold of 2.75 volts. An overvoltage of the controller is detected by comparator COMP.sub.OV and reference V.sub.REF2, in that the FLAG.sub.OV is set to the value 1 when the V.sub.OV voltage is greater than the V.sub.REF2 reference. Transistor MOS.sub.OV limits the maximum voltage, which is present at the positive input of comparator COMP.sub.OV when voltage V.sub.DD_PWR is higher than 3.6 volts. The digital logic and the load circuits function correctly at a supply voltage between 2.7 volts and 3.6 volts.

(14) During normal operation, when no defects are present, the protection controller permits a passage of total regulated voltage V.sub.DD_PWR of 3.3 volts. This is due to the fact that the protection controller regulates voltage V.sub.DD_PROT to a higher value of 3.4 volts. Therefore, transistor MOS.sub.PROT operates as a so-called source follower during normal operation, whereby voltage V.sub.DD_PROT is equal to voltage V.sub.DD_PWR of 3.3 volts. Since voltage V.sub.OV is less than the COMP.sub.OV threshold of V.sub.REF2, FLAG.sub.OV is not set to the value 1 during normal operation.

(15) The present invention offers a comprehensive coverage for defects within references V.sub.REF1 and V.sub.REF2, the control paths for voltages V.sub.DD_PWR and V.sub.DD_PROT and output transistors MOS.sub.PWR and MOS.sub.PROT. If defects are present, the values of V.sub.DD_PWR, V.sub.DD_PROT, V.sub.REF1 as well as V.sub.REF2 change and result in the activation of FLAG.sub.UV or FLAG.sub.OV. The setting of values for FLAG.sub.UV or FLAG.sub.OV is then utilized for initiating a controlled switch-off of load circuits, in order to avoid damage.

(16) The means for detecting defects in each of the sub-circuits are described in greater detail in the following with reference to FIG. 1.

(17) A defect of the voltage source for the V.sub.REF1 reference voltage may result in the value of the voltage being higher or lower than the nominal value of 1.215 volts. If the V.sub.REF1 reference voltage is less than the setpoint value 1.215 volts, so that voltages V.sub.DD_PWR and V.sub.DD_PROT are less than 2.75 volts, FLAG.sub.UV is set to the value 1 by comparator COMP.sub.UV, which utilizes a second independent reference voltage V.sub.REF2. If the V.sub.REF1 reference voltage is higher than the setpoint value of 1.215 volts, so that voltage V.sub.DD_PWR is higher than 3.7 volts and the protection controller regulates output V.sub.DD_PROT to 3.4 volts, FLAG.sub.OV is set to the value 1, since the average ((V.sub.DD_PWR+V.sub.DD_PROT)/2) is greater than 3.55 volts and, therefore, voltage V.sub.OV is greater than the threshold value of V.sub.REF2 set in comparator COMP.sub.OV.

(18) Any defect of control path V.sub.DD_PWR, such as with respect to feedback resistors R.sub.1, R.sub.2, R.sub.3 or transistor MOS.sub.PWR, causes voltage V.sub.DD_PWR to be higher or lower than the nominal value of 3.3 volts. If a defect in the control loop allows voltage V.sub.DD_PWR to become less than 2.75 volts, in deviation from the nominal value of 3.3 volts, FLAG.sub.UV is set to the value 1, in order to indicate an undervoltage of the power controller. If a defect in the control loop, such as a drain-source short circuit of transistor MOS.sub.PWR, allows voltage V.sub.DD_PWR to deviate upward from the value 3.3 volts and this becomes greater than 3.7 volts, a setting of FLAG.sub.OV to the value 1 takes place, in order to indicate an overvoltage in the power controller.

(19) A defect of the V.sub.REF2 reference voltage may result in the value for V.sub.REF2 being higher or lower than the nominal value of 1.215 volts. If the V.sub.REF2 value is less than the setpoint value of 1.215 volts, so that the protection controller regulates output V.sub.DD_PROT to a value less than V.sub.DD_PWR, a differential voltage develops across transistor MOS.sub.PROT. If the difference is great enough, comparator COMP.sub.OV sets the value for FLAG.sub.OV to 1 in order to thereby indicate a likely defect in the V.sub.REF2 reference voltage. Based on the aforementioned nominal values and equations (1) through (12b), the value of the V.sub.REF2 reference voltage, at which FLAG.sub.OV is set to the value 1, may be calculated to be 1.084 volts and the corresponding voltage drop of voltage V.sub.DD_PROT is 3.033 volts. Therefore, a defect of the V.sub.REF2 voltage value, which reduces its target value by more than 0.131 volts, is indicated by way of the value 1 being set for FLAG.sub.OV. The advantage of the provided overvoltage monitoring concept is that—although comparator COMP.sub.UV and the protection controller utilize the same reference V.sub.REF2—defects in the V.sub.REF2 reference, which result in a lower target value, may be detected by comparator COMP.sub.OV due to the value of FLAG.sub.OV. The setting of the value for FLAG.sub.OV does not necessarily mean, in this case, that an overvoltage is present, but rather indicates a problem in the V.sub.REF2 reference, which causes voltage V.sub.DD_PROT to be lower than voltage V.sub.DD_PWR. If a considerable distinction must be made between an overvoltage with respect to V.sub.DD_PWR and an undervoltage with respect to V.sub.DD_PROT, the specific embodiment described further below in conjunction with FIG. 3 and FIG. 4 may be utilized. If the V.sub.REF2 value is higher than the target value of 1.215 volts, the protection controller attempts to regulate voltage V.sub.DD_PROT to a higher value. Since the input of the protection controller is limited by the power controller, however, the voltage value for V.sub.DD_PROT remains at 3.3 volts and, therefore, the value of voltage V.sub.UV remains unchanged. The higher value for voltage V.sub.REF2 causes comparator COMP.sub.UV to set the value for FLAG.sub.UV to 1, however, since the V.sub.REF2 value is higher than its threshold voltage V.sub.UV. Based on the aforementioned nominal values and equations (1) through (12b), the increase of V.sub.REF2, which results in FLAG.sub.UV being set to the value 1, may be calculated to be 1.458 volts. Therefore, a defect of V.sub.REF2, which increases its target value by 0.243 volts, is indicated by way of FLAG.sub.UV being set to the value 1. The setting of the value for FLAG.sub.UV does not necessarily mean, in this case, that an undervoltage is present, but rather indicates a problem in the V.sub.REF2 reference, which causes voltage V.sub.UV to be lower than reference V.sub.REF2.

(20) Every defect of control path V.sub.DD_PROT, such as with respect to feedback resistors R.sub.4, R.sub.5, R.sub.6 or transistor MOS.sub.PROT, causes voltage V.sub.DD_PROT to be regulated to a lower or higher value than the nominal value of 3.4 volts. If a defect in the control loop causes voltage V.sub.DD_PROT to deviate downward from the nominal value of 3.4 volts and become lower than 2.75 volts, FLAG.sub.UV is set to the value 1, in order to indicate a defect in the control path of voltage V.sub.DD_PROT. If a defect in the control loop, such as a drain-source short circuit of transistor MOS.sub.PROT, results in voltage V.sub.DD_PROT deviating upward from the nominal value 3.4 volts and is regulated to a higher value of 3.5 volts or more, the behavior of the value for FLAG.sub.OV will indicate this defect in the BIST (built-in self-test) phase. The BIST phase is carried out after the switch-on of the controller and before the activation of the load circuit. If there is a defect, the activation of the load circuit and all circuits is blocked until the defect has been eliminated. During the BIST phase, the power controller outputting voltage V.sub.DD_PWR and comparator COMP.sub.OV are stimulated, in order to generate a certain output pattern from FLAG.sub.OV. If this pattern changes, this indicates the presence of a defect in the control path for V.sub.DD_PROT. During normal operation, when no defects are present, digital portion DT stimulates the power controller by way of signal BIST.sub.PWR, so that voltage V.sub.DD_PWR increases to 3.6 volts. The protection controller regulates the output for voltage V.sub.DD_PROT to 3.4 volts, and voltage V.sub.OV, which is less than the reference value of voltage V.sub.REF2, prevents the value 1 from being set for FLAG.sub.OV by comparator COMP.sub.OV. Next, digital portion DT stimulates overvoltage comparator COMP.sub.OV by way of output signal BIST.sub.OV, so that its comparison threshold changes. As a result, FLAG.sub.OV is set to the value 1, since the V.sub.OV voltage is now higher than reference voltage V.sub.REF2. Therefore, if no defects are present, the expected output pattern of FLAG.sub.OV during the BIST phase is a value 0, followed by a value 1. If, however, control path V.sub.DD_PROT has a defect, so that it, at 3.5 volts, is regulated to a higher value than the nominal value, the value for V.sub.DD_PROT will increase to 3.5 volts during the BIST phase—if the protection controller is stimulated by digital portion DT by way of signal BIST.sub.PWR—and, therefore voltage V.sub.OV will become greater than reference voltage V.sub.REF2, whereby comparator COMP.sub.OV is prompted to set FLAG.sub.OV to the value 1. Therefore, in the presence of a defect in the control loop, the output pattern of FLAG.sub.OV is the value 1, followed by a value 1 again. Without a defect, however, a first value 0 is followed by the second value 1. Actually, in the BIST phase, a defect in the control loop is also detected when voltage V.sub.DD_PROT deviates downward from the nominal value 3.4 volts and is regulated to a lower value of 3.3 volts or less. In this case, the output pattern of FLAG.sub.OV in the presence of a defect in the control loop is the value 0, followed by a value 0 again.

(21) The same applies for a defect in transistors MOS.sub.PWR, MOS.sub.PROT or in the control loop with respect to voltage V.sub.DD_PWR or references V.sub.REF1 and V.sub.REF2. Actually, the BIST phase is passed only when the V.sub.DD_PWR controller and V.sub.DD_PROT controller as well as references V.sub.REF1 and V.sub.REF2 operate within their limits. Based on the aforementioned nominal values and equations (1) through (12b), a defect is produced in the BIST phase when one of voltages V.sub.DD_PWR or V.sub.DD_PROT deviates from its nominal value by approximately ±0.1 volts or when one of references V.sub.REF1 or V.sub.REF2 deviates from its nominal value by approximately ±0.034 volts. If one of the voltages or references deviates upward, the FLAG.sub.OV produces the value 1, followed by a value 1 again, in the BIST phase. If the voltage deviates downward, the FLAG.sub.OV produces the value 0, followed by a value 0 again, in the BIST phase.

(22) In FIG. 2, the sequences, explained with reference to FIG. 1, for the circuit according to the present invention are graphically represented on the basis of appropriate wave shapes during the BIST phase, with and without defect in the control path. In this case, for parameters V.sub.BATT, V.sub.REF1, V.sub.REF2, V.sub.DD_PWR, V.sub.DD_PROT and V.sub.OV, the corresponding voltage values are indicated in volts, the logic or binary values 0 and 1 being assumed for parameters FLAG.sub.UV, FLAG.sub.OV, BIST.sub.PWR and BIST.sub.OV, however. As explained above, the sequence of the values 0 and 1 represented first in the progression of parameter FLAG.sub.OV represents the presence of a defect-free V.sub.DD_PROT control loop. The subsequently represented sequence of the values 1 and 1 or 0 and 0 for parameter FLAG.sub.OV, however, indicates the presence of a defect in V.sub.DD_PROT control loop.

(23) In FIG. 3, a specific example embodiment of the circuit according to the present invention is represented, which enables a considerable distinction to be made between an overvoltage with respect to V.sub.DD_PWR and an undervoltage with respect to V.sub.DD_PROT. In this case, the circuit additionally encompasses two double voltage detection comparators COMP.sub.UV1 and COMP.sub.UV2, which operate at reference voltages V.sub.REF1 and V.sub.REF2. In this specific embodiment, if voltage V.sub.DD_PROT is considerably lower than 2.75 volts, the value for FLAG.sub.UV is additionally set to 1, due to interconnected logic AND-gate AND, by comparator COMP.sub.UV2, which operates at reference voltage V.sub.REF1. In this way, a defect in the V.sub.REF2 reference is detected, in that FLAG.sub.UV and FLAG.sub.OV are set to the value 1.

(24) In FIG. 4, a specific example embodiment of the circuit according to the present invention is represented, which, in contrast to FIG. 3, encompasses only one undervoltage detection comparator COMP.sub.UV having a variable reference, in order to enable a considerable distinction to be made between overvoltage/undervoltage due to defects in the controllers and defects in the references. The COMP.sub.UV utilizes reference V.sub.REF2 when the FLAG.sub.OV has the value 0 and utilizes reference V.sub.REF1 when the FLAG.sub.OV has the value 1. In this specific embodiment, due to a defect in reference V.sub.REF2 when voltage V.sub.DD_PROT is considerably lower than 2.75 volts, the value for FLAG.sub.UV is additionally set to 1 due to the switch to the V.sub.REF1 reference. In this way, a defect in the V.sub.REF2 reference is detected, in that FLAG.sub.UV and FLAG.sub.OV are set to the value 1. Similarly, an overvoltage exists at V.sub.DD_PWR when reference V.sub.REF1 deviates to a higher value than 1.5 volts due to a defect. The protection controller limits voltage V.sub.DD_PROT to 3.4 volts and, therefore, voltage V.sub.UV to 1.5 volts. Due to overvoltage, the COMP.sub.OV sets the FLAG.sub.OV to the value 1 and, therefore, switches the reference for COMP.sub.UV from V.sub.REF2 to V.sub.REF1. The higher value for voltage V.sub.REF1 causes comparator COMP.sub.UV to set the value for FLAG.sub.UV to 1, however, since the V.sub.REF1 value is higher than its threshold voltage V.sub.UV. Therefore, a defect of V.sub.REF1, which increases its target value by 0.285 volts, is indicated by way of FLAG.sub.UV and FLAG.sub.OV being set to the value 1.

(25) In FIG. 5, an alternative specific example embodiment of the circuit according to the present invention is represented, which allows for a switch-off mode, in which overvoltage detection comparator COMP.sub.OV may be switched off with the aid of binary signal EN.sub.3 and the protection controller may be switched off with the aid of binary signal EN.sub.1, and protection transistor MOS.sub.PROT is passively regulated via EN.sub.2, so that the voltage does not exceed the maximum operating voltage of 3.6 volts. This is possible due to the utilization of a parallel combination of a Zener clamping diode Z and resistor R.sub.TKP having a positive temperature coefficient and resistor R.sub.TKN having a negative temperature coefficient and a transistor threshold voltage of MOS.sub.PROT2. The gate control voltage for protection transistor MOS.sub.PROT2 is generated from the resistor divider formed from resistors R.sub.TKP, R.sub.TKN and transistor threshold voltage MOS.sub.PROT2, so that the gate voltage shows a temperature coefficient similar to that of the threshold voltage of protection transistor MOS.sub.PROT. This results in a passive gate clamping voltage, which is stable across temperatures, which may limit voltage V.sub.DD_PROT to a maximum of 3.6 volts. In this specific embodiment, the overvoltage detection logic and the protection control loop may be released upon receipt of an external release signal EN.sub.0 by digital portion DT, which switches the complete application specific integrated circuit (ASIC) from the switch-off mode/stand-by mode to the active mode. Instead of the high-resistance resistor divider (R.sub.7, R.sub.8, R.sub.9), alternatively, a differential voltage detector across the drain and source of transistor MOS.sub.PROT may be provided, in order to detect the voltage drop across transistor MOS.sub.PROT. The same principle may also be adapted for controllers including other transistor types, such as PMOS or BJT.