OLED display panel for minimizing area of internalconnection line part for connecting GIP dirving circuit located in active area and OLED display device comprising the same

Abstract

The present disclosure relates to an OLED display panel for minimizing the size of a bezel and includes: an active area including data lines, scan lines intersecting the data lines, and sub-pixels arranged at each intersection; and a stage of a GIP driving circuit distributed and arranged in a plurality of unit pixel regions driven by m (m being a natural number) scan lines in the active area, to supply scan pulses to the corresponding scan lines, wherein the active area further includes m GIP internal connection lines parts respectively adjacent to the m scan lines, and a plurality of internal connection lines for connecting elements constituting each stage is distributed and arranged in the m GIP internal connection line parts.

Claims

1. An OLED display panel, comprising: a plurality of data lines and a plurality of scan lines intersecting the plurality of data lines, and a plurality of sub-pixels arranged at each intersection of the plurality of data lines and the plurality of scan lines at an active area; a stage of a gate in panel (GIP) driving circuit including m (m being a natural number of 2 or more) scan pulse output units outputting m scan pulses to m scan lines, wherein a plurality of elements constituting the stage of the GIP driving circuit are arranged in a plurality of unit pixel regions of m horizontal lines driven by the m scan lines in the active area; m GIP internal connection line parts respectively adjacent to the m scan lines at the active area; and a plurality of internal connection lines connecting the plurality of elements constituting the stage of the GIP driving circuit and the m GIP internal connection line parts, wherein each scan line and each GIP internal connection line part are parallel with each other, and wherein the number of the m GIP internal connection line parts corresponds to the number of the m scan lines.

2. The OLED display panel according to claim 1, wherein the stage further includes: a logic unit controlling voltage levels of a first node and a second node using a carry pulse of a previous stage and a carry pulse of a next stage; and a carry pulse output unit outputting an input carry pulse output clock signal as a carry pulse in response to the voltage levels of the first node and the second node.

3. The OLED display panel according to claim 1, wherein at least one of the unit pixel regions includes at least three sub-pixels, a GIP part in which one of the plurality of elements constituting the stage of the GIP driving circuit is arranged, and at least one of the plurality of internal connection lines electrically connected to the one of the plurality of elements and the m GIP internal connection line parts.

4. The OLED display panel according to claim 1, wherein m GIP internal connection line parts include a node Q, a node Qb, a node Qh, a carry pulse output terminal of the previous stage and a carry pulse output terminal of the next stage, in areas respectively adjacent to the m scan lines.

5. The OLED display panel according to claim 1, wherein the m includes one of 2, 3 and 5.

6. The OLED display panel according to claim 1, wherein one of the plurality of elements constituting the stage is located between two adjacent unit pixels and is connected to at least one of the m GIP internal connection line parts through at least one of the plurality of internal connection lines.

7. The OLED display panel according to claim 1, wherein the plurality of internal connection lines are located in a direction perpendicular to the m GIP internal connection line parts between two adjacent unit pixels.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram showing driving circuits of the conventional OLED display device and a relationship between driving circuits.

(2) FIG. 2 is a block diagram of a normal n-th stage GIP.

(3) FIG. 3 is a waveform diagram showing the operation of the n-th stage GIP shown in FIG. 2.

(4) FIG. 4 is a circuit diagram of a sub-pixel in an OLED display panel according to an aspect of the present disclosure.

(5) FIG. 5 is a circuit diagram of a k-th stage of a GIP driving circuit according to an aspect of the present disclosure.

(6) FIG. 6 is a diagram showing a configuration of an active area of an OLED display panel according to a first aspect of the present disclosure.

(7) FIG. 7 is a diagram showing a detailed configuration of two neighboring unit pixel regions arranged in the active area of the OLED display panel of FIG. 6.

(8) FIG. 8 is a diagram for describing internal connection lines arranged in a GIP internal connection line part according to the first aspect of the present disclosure.

(9) FIG. 9 is a block diagram of an n-th stage GIP according to a second aspect of the present disclosure.

(10) FIG. 10 is a diagram for describing internal connection lines arranged in a GIP internal connection line part according to the second aspect of the present disclosure.

DETAILED DESCRIPTION

(11) The applicant applied the technology of distributing and arranging GIP driving circuits in an active area of a display panel in order to minimize the size of a bezel of the display panel (Korean Patent Application No. 10-2017-0125355 (Filing date: Oct. 27, 2017)).

(12) The disclosure of Korean Patent Application (10-2017-0125355) will be briefly described as follows.

(13) FIG. 4 is a circuit diagram of a sub-pixel in an OLED display panel according to the present disclosure and FIG. 5 is a circuit diagram of a k-th stage of a GIP driving circuit according to an aspect of the present disclosure.

(14) That is, FIG. 4 corresponds to FIG. 4 of the Korean Patent Application (10-2017-0125355) and FIG. 5 corresponds to FIG. 5 of the Korean Patent Application (10-2017-0125355).

(15) As shown in FIG. 4, each sub-pixel of the OLED display panel according to an aspect of the present disclosure includes an OLED and a pixel circuit for driving the OLED.

(16) The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst and a driving TFT DT.

(17) The first switching TFT T1 charges a data voltage DATA in the storage capacitor Cst in response to a scan pulse signal. The driving TFT DT controls the quantity of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst to adjust the quantity of emitted light of the OLED. The second switching TFT T2 senses the threshold voltage and mobility of the driving TFT DT in response to a sense signal.

(18) The OLED may be composed of a first electrode (e.g., anode or cathode), an organic emission layer and a second electrode (e.g., cathode or anode).

(19) The storage capacitor Cst is electrically connected between the gate and the source of the driving TFT DT to maintain a data voltage corresponding to an image signal voltage or a voltage corresponding thereto for one frame period.

(20) Although FIG. 4 shows a 3T1C sub-pixel configuration composed of three TFTs T1, T2 and DT and one storage capacitor Cst, the present disclosure is not limited thereto and each sub-pixel of the OLED display panel according to the present disclosure may have a 4T1C, 4T2C, 5T1C or 5T2C sub-pixel configuration.

(21) Meanwhile, as shown in FIG. 5, the circuit of the k-th stage of the GIP driving circuit according to an aspect of the present disclosure includes: blank time first and second node controllers 21 and 26, which include transistors TA, TB, T3qA, T1B, T1C, T5A and T5B and a capacitor C1, selectively store a set signal CP(k) according to a line select pulse (LSP), charge a first node Q of the corresponding stage with a first constant voltage GVDD and discharge a second node Qb to a second constant voltage GVSS2 according to a vertical real-time (VRT) signal in a blank time; driving time first to third node controllers 23 and 25, which include transistors T1, T1A, T3n, T3nA, T3q, T3, T3A and T5, charge the first node Q of the corresponding stage with the voltage of a carry pulse CP(k−3) of the third previous stage according to the carry pulse CP(k−3), discharge the first node Q and a third node Qh to a second constant voltage GVSS2 according to a carry pulse CP(k+3) of the third next stage, and charge the third node Qh with the first constant voltage GVDD according to the voltage of the first node in a driving time; an inverter 24, which includes transistors T4, T4l , T4q and T5q and a capacitor C2, inverts the voltage of the first node Q and applies the inverted voltage to the second node Qb; an output buffer 27, which includes pull-up transistors T6cr and T6, pull-down transistors T7cr and T7 and a bootstrapping capacitor C3, receives one clock signal CRCLK(k) among a plurality of clock signals for carry pulse output and one clock signal SCCLK(k) among a plurality of clock signals for scan pulse output, and outputs a carry pulse CP(k) and a scan pulse SP(k) according to the voltages of the first node Q and the second node Qb; and a reset unit 22 which includes transistors T3nB and T3nC and discharges the first node Q to the second constant voltage GVSS2 according to a reset signal RST output from the timing controller in the blank time.

(22) The transistors TB, TA and T3q in the blank time first and second node controllers 21 and 26 are turned on to store the set signal CP(k) in the capacitor C1 when the LSP is at a high level.

(23) In addition, the transistors T1C and T5B are turned on to charge the first node Q with the first constant voltage GVDD and to discharge the second node Qb to the second constant voltage GVSS2 when the VRT signal is at a high level in the blank time.

(24) The transistors T1, T1A and T5 in the driving time first to third node controllers 23 and 25 are turned on to charge the first node Q with the carry pulse CP(k−3) of the third previous stage and to discharge the second node Qb to the second constant voltage GVSS2 when the carry pulse CP(k−3) of the third previous stage is at a high level in the driving time. When the first node Q is charged and the second node Qb is discharged in this manner, the transistor T3q is turned on to charge the third node Qh with the first constant voltage GVDD.

(25) When the carry pulse CP(k+3) of the third next stage is at a high level, the transistors T3n and T3nA are turned on to discharge the first node Q and the third node Qh to the second constant voltage GVSS2.

(26) The inverter 24 inverts the voltage of the first node Q and applies the inverted voltage to the second node Qb.

(27) In the output buffer 27, the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned off to output one clock signal CRCLK(k) among the plurality of clock signals for carry pulse output as a carry pulse CP(k) when the first node Q is at a high level and the second node Qb is at a low level. Further, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off to output one clock signal SCCLK(k) among the plurality of clock signals for scan pulse output as a scan pulse SP(k) when the first node Q is at a high level and the second node Qb is at a low level.

(28) Here, when the clock signal SCCLK(k) for scan pulse output is applied at a high level, the bootstrapping capacitor C3 of the output buffer 27 bootstraps (couples) the first node Q and thus the first node Q has a higher potential.

(29) In this manner, the output buffer 27 outputs the clock signal CRCLK(k) for carry pulse output and the clock signal SCCLK(k) for scan pulse output, which are input thereto, as a carry pulse CL(k) and a scan pulse SP(k) in a state in which the first node Q is bootstrapped, and thus output loss can be prevented.

(30) In the reset unit 22, the transistors T3nB and T3nC are turned on to discharge the first node Q to the second constant voltage GVSS2 when the reset signal RST output from the timing controller is at a high level in the blank time.

(31) Although FIG. 5 shows a stage of the GIP driving circuit driven with 6 phases, the present disclosure is not limited thereto and stages of the GIP driving circuit can be configured in various manners.

(32) As shown in FIG. 5, each stage of the GIP driving circuit includes 25 transistors and 3 capacitors.

(33) Accordingly, when an element (transistor or capacitor) constituting the stage of the GIP driving circuit is distributed and arranged in a unit pixel region, the circuit of a stage for driving a gate line (scan line) can be arranged.

(34) FIG. 6 is a diagram showing a configuration of the active area of the OLED display panel according to a first aspect of the present disclosure and FIG. 7 is a diagram showing a detailed configuration of two neighboring unit pixels arranged in the active area of the OLED display panel shown in FIG. 6.

(35) That is, FIG. 6 corresponds to FIG. 6 of the Korean Patent Application (10-2017-0125355) and FIG. 7 corresponds to FIG. 7 of the Korean Patent Application (10-2017-0125355).

(36) As shown in FIGS. 6 and 7, in arrangement of the GIP driving circuit in the active area of the OLED display panel, a unit pixel region of the active area is divided into at least three sub-pixels R, G, B and W, a GIP part 31 and a GIP internal interconnection line part 32.

(37) The at least three sub-pixels (R, G, B and W) 33 are configured in such a manner that a plurality of data lines DL1 to DL8, a plurality of reference voltage lines Vref and first and second constant voltage lines EVDD and EVSS are arranged in the vertical direction and a plurality of gate lines (scan lines) SCAN are arranged in the horizontal direction.

(38) The GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit. That is, the element (transistor or capacitor) constituting the stage of the GIP driving circuit is distributed and arranged in a unit pixel region composed of red, green, blue and white sub-pixels R, G, B and W.

(39) That is, at least one stage ST of the GIP driving circuit for driving a gate line (scan line) is distributed and arranged in a plurality of unit pixel regions driven by a gate line (scan line).

(40) The GIP internal interconnection line part 32 is an area in which connection lines (a node Q, a node QB, a node Qh, a carry pulse output terminal of the previous stage, a carry pulse output terminal of the next stage, etc.) for connecting elements in a stage of the GIP driving circuit are arranged.

(41) As described above, as the GIP driving circuit is arranged in the active area, the plurality of data lines DL1 to DL8 and the reference voltage lines Vref for driving the sub-pixels R, G, B and W are arranged in the vertical direction, as shown in FIG. 7.

(42) In addition, since the GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, one of the signals LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK and SCCLK shown in FIG. 5 is applied to the GIP part 31.

(43) Furthermore, in the OLED display panel according to the first aspect of the present disclosure, the circuit of a stage for driving a gate line (scan line) is distributed and arranged in unit pixel regions driven by the gate line (scan line) and thus all connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) for connecting elements in the stage of the GIP driving circuit need to be arranged in the GIP internal connection line part 32 corresponding to the gate line (scan line).

(44) FIG. 8 shows internal connection lines arranged in the GIP internal connection line part 32 according to the first aspect of the present disclosure.

(45) In FIG. 5, a signal line CP(k+3) to which a carry pulse output from the third next stage is applied is connected to the gate electrode of the transistor T3n, the node Q is connected to the source electrode of the transistor T3n, and the node Qh is connected to the drain electrode of the transistor T3n, for example.

(46) Accordingly, when it is assumed that the transistor T3n shown in FIG. 5 is arranged in a GIP part 31, at least the signal line CP(k+3), to which the carry pulse output from the third next stage is applied, the node Q and the node Qb need to be arranged in the GIP internal connection line part 32.

(47) In this manner, the circuit of a stage for driving a gate line (scan line) is distributed and arranged in unit pixel regions driven by the gate line (scan line) in the OLED display panel according to the first aspect of the present disclosure, and thus a maximum of four GIP internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) are arranged in the GIP internal connection line part 32 of each line. For example, a connection line between elements corresponds to a connection line between the gate electrode of the transistor T4 and the drain electrode of the transistor T4l in FIG. 5.

(48) Accordingly, the aperture ratio of the OLED display panel according to the first aspect of the present disclosure decreases and the area occupied by the GIP internal connection line parts 32 increases, and thus the OLED display panel is not suitable for high definition.

(49) To solve this problem, in an OLED display panel and an OLED display device according to a second aspect of the present disclosure, the stages of the GIP driving circuit are arranged in the pixel array to increase the aperture ratio of the OLED display panel while providing a narrow bezel and to reduce the area occupied by the GIP internal connection line parts, realizing high definition.

(50) FIG. 9 is a block diagram of the n-th stage GIP according to the second aspect of the present disclosure.

(51) In the OLED display panel according to the second aspect of the present disclosure, the stages of the GIP driving circuit are arranged in the pixel array in such a manner that a stage including a plurality of scan pulse output units is configured for unit pixels driven by a plurality of scan lines.

(52) That is, the circuit of the k-th stage of the GIP driving circuit according to an aspect of the present disclosure includes the blank time first and second node controllers 21 and 26, the driving time first to third node controllers 23 and 25, the inverter 24, the output buffer 27 and the reset unit 22, as described above with reference to FIG. 5.

(53) However, the OLED display panel according to the second aspect of the present disclosure has the stages of the GIP driving circuit, which are arranged in the pixel array, wherein the blank time first and second node controllers 21 and 26, the driving time first to third node controllers 23 and 25, the inverter 24 and the reset unit 22, which are described above with reference to FIG. 5, and the output buffer 27 including a carry pulse output unit and a plurality of scan pulse output units are arranged in unit pixels driven by a plurality of scan lines, as shown in FIG. 9.

(54) In FIG. 9, the blank time first and second node controllers 21 and 26, the driving time first to third node controllers 23 and 25, the inverter 24 and the reset unit 22, which are described above with reference to FIG. 5, are represented by a logic unit S/R1.

(55) The logic unit S/R1 controls the voltage levels of the first node Q and the second node Qb using the line select signal LSP, the set signal CP(k), the vertical real-time signal VRT, the carry pulse CP(k−3) of the m-th previous stage, the carry pulse CP(k+3) of the m-th next stage and the reset signal RST, as described in FIG. 5.

(56) In addition, the output buffer 27 includes a carry pulse output unit and a plurality of scan pulse output units.

(57) That is, the output buffer 27 includes: a carry pulse output unit composed of a pull-up transistor T6cr and a pull-down transistor T7cr, and configured in such a manner that the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned off to output a clock signal CRCLK1 among the plurality of carry pulse output clock signals as a carry pulse CP(1) when the first node Q is at a high level and the second node Qb is at a low level; a first scan pulse output unit composed of a first pull-up transistor T6-1, a first pull-down transistor T7-1 and a first bootstrapping capacitor Cq1, and configured in such a manner that the first pull-up transistor T6-1 is turned on and the first pull-down transistor T7-1 is turned off to output a clock signal SCCLK(1) among the plurality of scan pulse output clock signals as a scan pulse SP(1) when the first node Q is at a high level and the second node Qb is at a low level; a second scan pulse output unit composed of a second pull-up transistor T6-2, a second pull-down transistor T7-2 and a second bootstrapping capacitor Cq2, and configured in such a manner that the second pull-up transistor T6-2 is turned on and the second pull-down transistor T7-2 is turned off to output a clock signal SCCLK(2) among the plurality of scan pulse output clock signals as a scan pulse SP(2) when the first node Q is a high level and the second node Qb is a low level; a third scan pulse output unit composed of a third pull-up transistor T6-3, a third pull-down transistor T7-3 and a third bootstrapping capacitor Cq3, and configured in such a manner that the third pull-up transistor T6-3 is turned on and the third pull-down transistor T7-3 is turned off to output a clock signal SCCLK(3) among the plurality of scan pulse output clock signals as a scan pulse SP(3) when the first node Q is at a high level and the second node Qb is at a low level; a fourth scan pulse output unit composed of a fourth pull-up transistor T6-4, a fourth pull-down transistor T7-4 and a fourth bootstrapping capacitor Cq4, and configured in such a manner that the fourth pull-up transistor T6-4 is turned on and the fourth pull-down transistor T7-4 is turned off to output a clock signal SCCLK(4) among the plurality of scan pulse output clock signals as a scan pulse SP(4) when the first node Q is at a high level and the second node Qb is at a low level; and a fifth scan pulse output unit composed of a fifth pull-up transistor T6-5, a fifth pull-down transistor T7-5 and a fifth bootstrapping capacitor Cq5, and configured in such a manner that the fifth pull-up transistor T6-5 is turned on and the fifth pull-down transistor T7-5 is turned off to output a clock signal SCCLK(5) among the plurality of scan pulse output clock signals as a scan pulse SP(5) when the first node Q is at a high level and the second node Qb is at a low level.

(58) When the output buffer 27 includes one carry pulse output unit and five scan pulse output units, as shown in FIG. 9, elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by five scan lines in the OLED display panel according to the second aspect of the present disclosure.

(59) Although the output buffer 27 includes one carry pulse output unit and five scan pulse output units in FIG. 9, the present disclosure is not limited thereto and the output buffer 27 may include one carry pulse output unit and at least two scan pulse output units.

(60) If the output buffer 27 includes one carry pulse output unit and two scan pulse output units, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by two scan lines in the OLED display panel according to the second aspect of the present disclosure.

(61) Further, when the output buffer 27 includes one carry pulse output unit and three scan pulse output units, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by three scan lines in the OLED display panel according to the second aspect of the present disclosure.

(62) That is, in the OLED display panel according to the second aspect of the present disclosure, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by as many scan lines as the number of scan pulse output units.

(63) Line arrangement of the GIP internal connection line parts when the stage having the aforementioned configuration is arranged in the corresponding area will be described below.

(64) FIG. 10 is a diagram for describing internal connection lines arranged in the GIP internal connection line parts according to the second aspect of the present disclosure.

(65) FIG. 10 illustrates internal connection lines when the output buffer 27 includes one carry pulse output unit and five scan pulse output units as shown in FIG. 9.

(66) That is, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in arbitrary unit pixels among the unit pixels driven by the first to fifth scan lines SCAN1 to SCAN5.

(67) In addition, one of the internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) is arranged in each GIP internal connection line part 32 adjacent to each scan line SCAN1 to SCAN5.

(68) That is, the node Q is arranged in the GIP internal connection line part 32 adjacent to the first scan line SCAN1, the node Qb is arranged in the GIP internal connection line part 32 adjacent to the second scan line SCAN2, the connection line CP(k+3) connected to the carry pulse output terminal of the next stage is arranged in the GIP internal connection line part 32 adjacent to the third scan line SCAN3, the node Qb is arranged in the GIP internal connection line part 32 adjacent to the fourth scan line SCAN4, and the connection line CP(k−3) connected to the carry pulse output terminal of the previous stage is arranged in the GIP internal connection line part 32 adjacent to the fifth scan line SCAN5.

(69) In addition, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in arbitrary unit pixels among the unit pixels driven by the first to fifth scan lines SCAN1 to SCAN5, as described above.

(70) For example, the signal line CP(k+3) to which the carry pulse output from the third next stage is applied is connected to the gate electrode of the transistor T3n (refer to FIG. 5) among the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9, the node Q is connected to the source electrode of the transistor T3n, and the node Qh is connected to the drain electrode of the transistor T3n.

(71) Accordingly, if the transistor T3n shown in FIG. 5 is arranged in the GIP part 31, the node Q arranged in the GIP internal connection line part 32 adjacent to the first scan line SCAN1, the connection line CP(k+3) connected to the carry pulse output terminal of the next stage, which is arranged in the GIP internal connection line part 32 adjacent to the third scan line SCAN3, and the node Qh arranged in the GIP internal connection line part 32 adjacent to the fourth scan line SCAN4 are connected to the transistor T3n, as shown in FIG. 10.

(72) In addition, the signal line CP(k−3) to which the carry pulse output from the third previous stage is applied is connected to the gate electrode and the source electrode of the transistor T1 (refer to FIG. 5) among the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9, and the node Qh is connected to the source electrode of the transistor T1.

(73) Accordingly, if the transistor T1 shown in FIG. 5 is arranged in the GIP part 31, the node Qh arranged in the GIP internal connection line part 32 adjacent to the fourth scan line SCAN4 and the connection line CP(k−3) connected to the carry pulse output terminal of the previous stage, which is arranged in the GIP internal connection line part 32 adjacent to the fifth scan line SCAN53, are connected to the transistor T1, as shown in FIG. 10.

(74) Since the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in arbitrary unit pixels among the unit pixels driven by the first to fifth scan lines SCAN1 to SCAN5, as described above, GIP elements are not arranged in the GIP parts 31 of all unit pixels. Accordingly, signal lines extended to the GIP parts 31 and arranged in the GIP internal connection line parts 32 can be connected to the GIP elements.

(75) Although FIG. 10 illustrates that the unit elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in arbitrary unit pixels among the unit pixels driven by the first to fifth scan lines SCAN1 to SCAN5, the present disclosure is not limited thereto and the unit elements constituting the stage may be distributed and arranged in arbitrary unit pixels among unit pixels driven by at least two scan lines.

(76) If the output buffer 27 shown in FIG. 9 includes one carry pulse output unit and two scan pulse output units, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by the first and second scan lines SCAN1 and SCAN2 in the OLED display panel according to the second aspect of the present disclosure. In addition, the internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) are distributed and arranged in two GIP internal connection line parts 32 adjacent to the first and second scan lines SCAN1 and SCAN2.

(77) If the output buffer 27 shown in FIG. 9 includes one carry pulse output unit and three scan pulse output units, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by the first to third scan lines SCAN1 to SCAN3 in the OLED display panel according to the second aspect of the present disclosure. In addition, the internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) are distributed and arranged in three GIP internal connection line parts 32 adjacent to the first to third scan lines SCAN1 to SCAN3.

(78) That is, in the OLED display panel according to the second aspect of the present disclosure, the elements constituting the stage having the logic unit S/R1 and the output buffer 27 shown in FIG. 9 are distributed and arranged in unit pixels driven by as many scan lines as the number of scan pulse output units included in the output buffer 27, and the internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) are distributed and arranged in GIP internal connection line parts 32 adjacent to the corresponding scan lines.

(79) As described above, in the OLED display panel according to the second aspect of the present disclosure, the output buffer illustrated in FIG. 9 includes a plurality of scan pulse output units, GIP elements are distributed and arranged in unit pixels driven by as many scan lines as the number of scan pulse output units, and the internal connection lines (the node Q, the node Qb, the node Qh, the carry pulse output terminal of the previous stage, the carry pulse output terminal of the next stage, connection lines between elements, etc.) are distributed and arranged in GIP internal connection line parts 32 adjacent to the corresponding scan lines, and thus the number of internal connection lines arranged in the GIP internal connection lines parts 32 can be reduced.

(80) Accordingly, the aperture ratio of the OLED display panel according to the second aspect of the present disclosure can increase and the area occupied by the GIP internal connection lines 32 can be reduced, and thus a high-definition display panel can be realized.

(81) Those skilled in the art will appreciate that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure through the above description. Accordingly, the scope of the disclosure should be determined by the appended claims and their legal equivalents, not by the above description.