Switched-mode power controller with multi-mode startup

Abstract

A switched-mode power controller includes a primary side controller circuit configured in a startup mode of operation to generate a fixed switching frequency pulse width modulation (PWM) signal with incrementing duty-ratio value. The PWM signal drives a main-switch that charges an inductive device with stored energy and discharges the stored energy into a capacitor on a secondary side to generate a power controller output voltage. Based on a comparison of the power controller output voltage with a reference voltage, the primary side controller circuit is configured to stop the incrementing of the duty-ratio of the PWM signal and begin a quasi-resonant mode of operation during which the primary side controller circuit reduces a number of valleys detected in one or more off-times of the main-switch in one or more respective main-switch switching periods.

Claims

1. A controller circuit, comprising: a digital controller configured to generate, in a first mode of startup operation, a pulse width modulation (PWM) signal with an incrementing on-time duty-ratio value; and a gate driver circuit configured to control a main-switch of a power converter using the PWM signal; wherein, the digital controller is further configured to: receive an indication of an output voltage of the power converter; exit the first mode of startup operation when a difference between a reference voltage and the indication of the output voltage is not greater than an error window; generate, in a second mode of startup operation, the PWM signal with a decreasing off-time duty-ratio value; and exit the second mode of startup operation when a difference between the reference voltage and the indication of the output voltage is not greater than a predefined threshold voltage.

2. The controller circuit of claim 1, wherein: the digital controller is further configured to stop decreasing the off-time duty-ratio value of the PWM signal when the digital controller exits the second mode of startup operation.

3. The controller circuit of claim 2, wherein the predefined threshold voltage is about 150 mV.

4. The controller circuit of claim 2, wherein: the digital controller is further configured to enter a third mode of operation when the digital controller exits the second mode of startup operation, the third mode of operation being a steady-state mode of operation.

5. The controller circuit of claim 1, further comprising: a feedback circuit; wherein the digital controller is further configured, in the second mode of startup operation, to: detect, using the feedback circuit, a number of valleys of a quasi-resonant oscillating signal during an off-time of the main-switch; and decrease the off-time duty-ratio value of the PWM signal by reducing, in the second mode of startup operation, the number of valleys detected in one or more subsequent off-times of the main-switch in one or more switching periods of the main-switch.

6. The controller circuit of claim 5, wherein: the digital controller is further configured, in the second mode of startup operation, to reduce the number of valleys by one during each switching period of the main-switch.

7. The controller circuit of claim 1, further comprising: a decoder circuit configured to receive, using a communications link, an encoded digital data stream comprising digital representations of the output voltage and to generate a digital voltage value using the encoded digital data stream; wherein the digital voltage value is used as the indication of the output voltage.

8. The controller circuit of claim 7, wherein: the decoder circuit receives, using the communications link, the encoded digital data stream from a secondary side of the power converter.

9. The controller circuit of claim 7, wherein: the encoded digital data stream further comprises a digital representation of the reference voltage; and the decoder circuit generates the reference voltage using the encoded digital data stream.

10. The controller circuit of claim 7, wherein: the decoder circuit receives, using the communications link, the encoded digital data stream from the secondary side of the power converter after the output voltage has exceeded an under-voltage lockout threshold voltage value.

11. The controller circuit of claim 10, wherein: the decoder circuit does not receive the encoded digital data stream from a secondary side of the power converter before the output voltage has exceeded the under-voltage lockout threshold voltage value.

12. A method, comprising: generating, in a first mode of startup operation of a controller circuit, a pulse width modulation (PWM) signal with an incrementing on-time duty-ratio value; controlling a main-switch of a power converter based on the PWM signal; receiving an indication of an output voltage of the power converter; exiting the first mode of startup operation when a difference between a reference voltage and the indication of the output voltage is not greater than an error window; generating, in a second mode of startup operation of the controller circuit, the PWM signal with a decreasing off-time duty-ratio value; and exiting the second mode of startup operation when a difference between the reference voltage and the indication of the output voltage is not greater than a predefined threshold voltage.

13. The method of claim 12, further comprising: stopping a decrease of the off-time duty-ratio value of the PWM signal when the controller circuit exits the second mode of startup operation.

14. The method of claim 13, further comprising: entering a third mode of operation when the controller circuit exits the second mode of startup operation, the third mode of operation being a steady-state mode of operation.

15. The method of claim 12, further comprising: detecting, in the second mode of startup operation, a number of valleys of a quasi-resonant oscillating signal during an off-time of the main-switch; and decreasing the off-time duty-ratio value of the PWM signal by reducing, in the second mode of startup operation, the number of valleys detected in one or more subsequent off-times of the main-switch in one or more switching periods of the main-switch.

16. The method of claim 15, further comprising: reducing, in the second mode of startup operation, the number of valleys by one during each switching period of the main-switch.

17. The method of claim 12, further comprising: receiving an encoded digital data stream comprising digital representations of the output voltage; and generating a digital voltage value using the encoded digital data stream; wherein the digital voltage value is used as the indication of the output voltage.

18. The method of claim 17, wherein: the encoded digital data stream is received by the controller circuit from a secondary side of the power converter.

19. The method of claim 17, wherein: the encoded digital data stream is received from a secondary side of the power converter after the output voltage has exceeded an under-voltage lockout threshold voltage value.

20. The method of claim 19, wherein: the encoded digital data stream is not received by the controller circuit from the secondary side of the power converter before the output voltage has exceeded the under-voltage lockout threshold voltage value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagrammatic top view of an example quasi-resonant switched-mode power converter and a mixed-signal controller that includes a primary side circuit and a secondary side circuit.

(2) FIG. 2 shows example waveforms for startup output voltage (V.sub.out), an averaged main-switch (MS) gate-source voltage (c.sup.avg), and digital link waveforms for the quasi-resonant switched-mode power converter shown in FIG. 1.

(3) FIG. 3 shows example waveforms of the main-switch (MS) drain-source voltage and the output voltage (V.sub.out).

(4) FIG. 4 is a flow diagram of an example startup sequence that is initiated on power-on-reset, where the primary controller comes out of under-voltage lockout.

(5) FIG. 5 shows an example of typical output voltage and main-switch drain-source voltage waveforms during startup.

DETAILED DESCRIPTION

(6) Reference now will be made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, it will be apparent to those skilled in the art that modifications and variations can be made in the present technology without departing from the scope thereof. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter cover all such modifications and variations within the scope of the appended claims and their equivalents.

(7) The disclosure describes a multimode startup method for a quasi-resonant switched-mode power controller that includes a startup ramp mode followed by a valley reduction mode. The initial startup ramp voltage involves increasing the main-switch on-times to enable the power controller components to power-up quickly. The follow-on valley reduction mode decreases the off-times by reducing the number of valleys each period, which effectively increases the on-times. Thus, reducing the number of valleys by one (or more) each switching cycle enables the quasi-resonant switched-mode power converter to have faster startup time while, at the same time, obtaining the benefits of a quasi-resonant mode of operation.

(8) FIG. 1 shows an example quasi-resonant switched-mode power converter 10 that is implemented by an alternating current (AC)/direct current (DC) flyback converter 12 and a mixed-signal controller 14 that includes a primary side controller circuit 16, a secondary side controller circuit 18, and a uni-directional high-speed digital link 20 that transmits digital representations of the changing output voltage and the target reference voltage from the secondary side controller circuit 18 to the primary side controller circuit 16.

(9) The primary side controller circuit 16 includes a gate driver 22, a digital controller 24, a decoder 26, and a power-on-reset (POR) circuit 71. The primary side controller circuit 16 is connected to the gate 32 of a primary side main-switch 34 (MS). The digital controller 24 supplies a low-power pulse width modulation (PWM) signal 36 to the input of the gate driver 22. The gate driver 22 receives the low-voltage PWM signal and produces a high-voltage PWM drive input signal (c) that is applied to the main-switch gate 32 to periodically turn-on and turn-off the high-current main-switch 34. The main-switch 34 controls the current through an inductive device which, in the instant example, is implemented by a transformer 35 that includes a primary winding 38 and a secondary winding 40 which are inductively coupled together when current flows through the main-switch 34.

(10) The quasi-resonant switched-mode power converter 10 converts an input AC voltage (V.sub.AC) into an output DC voltage (V.sub.out) and an output DC current (I.sub.OUT) to power a load (R.sub.LOAD). In the instant example, the power source is an alternating current voltage (V.sub.AC) that is rectified to produce the input voltage (V.sub.BUS). The primary side controller circuit 16 provides the high-voltage PWM input for the high-current main-switch 34 to periodically turn on and off the main-switch 34. The current flowing in the primary winding 38 induces a current in the secondary winding 40 that drives a current through an output circuit 27 to produce the output voltage (V.sub.out) across the load (R.sub.LOAD).

(11) In some examples, the quasi-resonant switched-mode power converter 10 also includes an auxiliary winding 41 that is inductively coupled to the primary winding 38 and the secondary winding 40. A feedback circuit 43 component (FB) of the primary side controller circuit 16 receives an auxiliary winding voltage (V.sub.AUX) across an auxiliary winding capacitor (C.sub.AUX). The auxiliary winding voltage is correlated with the main-switch on-times. After the transformer or inductor has been demagnetized, the auxiliary winding voltage begins to oscillate between signal peaks and signal valleys. The feedback circuit 43 generates a digital representation of a valley signal 45 for each valley detected in the auxiliary winding voltage (V.sub.AUX).

(12) The secondary side controller circuit 18 includes an analog-to-digital converter (ADC) 42, an encoder/finite state machine (FSM) 44, and an under-voltage lockout (UVLO) circuit 47. The analog-to-digital converter 42 converts the output voltage (V.sub.out) and the reference voltage (V.sub.ref) to digital values (e.g., V.sub.out[n], V.sub.ref[n]) and the encoder/finite state machine 44 encodes the digital values into respective digital representations of the output voltage and the reference voltage (e.g., d.sub.in). The uni-directional high-speed digital link 20 transmits the encoded digital representations of the changing output voltage and the encoded reference voltage (e.g., clout) to the decoder 26 in the primary side controller circuit 16. The decoder 26 converts the respective digital representations of the output voltage and the reference voltage into digital voltage values (e.g., V.sub.out[n], V.sub.ref[n]) that are input into the digital controller 24 to control the gate driver 22 based on the feedback regarding the current output voltage (Vow) and the current reference voltage (V.sub.ref).

(13) FIG. 2 shows graphs of example output waveforms for an output voltage 49 (V.sub.out), an averaged main-switch (MS) gate-source voltage 51 (c.sup.avg), and digital link representations 52 (i.e., {d.sub.in[n], d.sub.out[n]}) for the quasi-resonant switched-mode power converter 10 shown in FIG. 1.

(14) In an example startup mode of operation 46, the digital controller 24 and gate driver 22 components of the primary side controller circuit 16 generate a fixed switching frequency (f.sub.sw) PWM signal 36 with increasing duty-ratio value that drives the flyback converter main-switch (MS) switch 34. The switching of the main-switch, in turn, charges the transformer magnetizing inductance of the transformer 35 with the rectified AC input (V.sub.BUS) and discharges the stored energy into the output voltage capacitor (C.sub.OUT). The output voltage (V.sub.out) begins to slowly ramp towards the target reference voltage (V.sub.ref). After some period, the output voltage (V.sub.out) reaches an under-voltage lockout (UVLO) threshold 50 of the UVLO circuit 47 enabling the secondary side controller circuit 18 to turn on and also drive the uni-directional digital link 20. In some examples, the secondary side controller circuit 18 does not include a UVLO circuit, in which case the secondary side controller circuit 18 may turn on at an earlier time in the startup ramp mode of operation 46.

(15) As soon as the secondary side controller circuit 18 turns on (e.g., when V.sub.OUT reaches UVLO 50) it begins to send digital representations 52 of the changing output voltage and the target reference voltage (i.e., {V.sub.out[n], V.sub.ref[n]}) to the uni-directional digital link 20, which transmits encoded versions of the digital representations (d.sub.in, d.sub.out) to the decoder 26 component of the primary side controller circuit 16. This information is processed by the digital controller 24 of the primary side controller circuit 16 in such a way that when the output voltage (V.sub.out) is close to the target reference voltage (V.sub.ref), the PWM duty-ratio ramp is no longer incremented and the primary side controller circuit 16 switches to a quasi-resonant valley reduction mode 58. In some examples, the primary side controller circuit 16 stops incrementing the PWM duty-ratio ramp when the output voltage (V.sub.out) is within range of an error window 54 of an internal digital compensator component of the primary side controller circuit 16 that compares the output voltage (V.sub.out) with the target reference voltage (V.sub.ref). In some examples, the digital compensator is a proportional-integral-derivative (PID) digital compensation circuit. As long as the difference between the output voltage (V.sub.out) and the reference voltage (V.sub.ref) is greater than a pre-defined threshold voltage (e.g., approximately 150 mV in some examples), the primary side controller circuit 16 remains in the quasi-resonant valley reduction mode 58 and continues to reduce the number of valleys in each switching period. In some examples, the number of valleys is reduced by one each switching period. In this way, a smooth and well-controlled transition from startup ramp mode into normal steady-state operation 60 can be achieved, while minimizing startup time and component peak current and voltage stress.

(16) FIG. 3 shows example waveforms of the main-switch (MS) drain-source voltage (Y.sub.ds) and the output voltage (V.sub.out) during valley reduction mode 58 and normal operation mode 60. In the valley reduction mode 58, the digital controller 24 component of the primary side controller circuit 16 receives from the feedback circuit 43 a respective valley signal 45 for each valley detected in the oscillating auxiliary winding voltage (V.sub.AUX) that begins after demagnetization completes. During startup, it is generally not possible to detect valleys until the output voltage is high enough. In some examples, after a threshold output voltage has been reached, the primary side controller circuit 16 will determine the number of valleys in the off-time of a period and then begin reducing the number of valleys during the off-times of the switching periods. In some examples, the primary side controller circuit 16 reduces the off-times by reducing the number of valleys by one per switching cycle (e.g., by turning on the main-switch when the valley number is one less than the valley number that was cut off in the preceding period). In some examples, for one or more periods, more than one valley is cut off per switching cycle. Reducing the number of valleys by one (or more) each switching cycle enables the quasi-resonant switched-mode power converter 10 to have faster startup time while, at the same time, obtaining the benefits of a quasi-resonant mode of operation.

(17) In the example shown in FIG. 3, during the valley reduction mode 58, the primary side controller circuit 16 initially turns on the main-switch 34 at a time that coincides with the fourth valley signal (VS4) in a first period in the valley reduction mode 58. In the next period, the primary side controller circuit 16 turns on the main-switch 34 at a time that coincides with the third valley signal (VS3) in a second period in the valley reduction mode 58. In the next period, the primary side controller circuit 16 turns on the main-switch 34 at a time that coincides with the second valley signal (VS2) in a third period in the valley reduction mode 58. The fourth period occurs after the difference between the output voltage (Vow) and the reference voltage (V.sub.ref) has dropped below the pre-defined threshold voltage (e.g., 150 mV). As a result, the power converter 10 enters the normal mode of operation. In some examples, during the normal mode of operation, the primary side controller circuit 16 turns on the main-switch 34 to coincide with the signal valley number in the valley reduction mode of operation 58 (e.g., 2.sup.nd valley in the example illustrated in FIG. 3).

(18) FIG. 4 is a flow diagram of an example startup sequence that is initiated by receipt of a power-on-reset (POR) signal, where the primary side controller circuit 16 comes out of under-voltage lockout. In accordance with this method, the power-on-reset circuit 71 detects the power applied to the primary side controller circuit 16 and generates a reset impulse that resets the entire circuit 16 to a known state (FIG. 4, block 70). The primary side controller circuit 16 increments the PWM gate driver duty ratio (FIG. 4, block 72). The primary side controller circuit 16 continues to increment the PWM gate driver duty ratio until the difference between the reference voltage (V.sub.ref) and the output voltage (V.sub.out) does not exceed the width of the PID error window (FIG. 4, block 74). The primary side controller circuit 16 decrements the number of quasi-resonant valleys (e.g., by one per period) (FIG. 4, block 76). The primary side controller circuit 16 continues to decrement the number of quasi-resonant valleys (e.g., by one per period) until the difference between the reference voltage (V.sub.ref) and the output voltage (Vow) does not exceed the predetermined threshold (e.g., approximately 150 mV in some examples) (FIG. 4, block 78). When the difference between reference voltage (V.sub.ref) and the output voltage (Vow) does not exceed the predetermined threshold, the primary side controller circuit 16 enters the normal operational mode (FIG. 4, block 80).

(19) FIG. 5 shows an example of typical output voltage and main-switch drain-source voltage waveforms during startup that illustrates the smooth mode transition made possible by the examples of the quasi-resonant switched-mode power converter 10 that is described herein.

(20) Embodiments of the systems described herein may be used in combination with any switched mode power supply (SMPS) where energy is stored in an inductive device (e.g., a winding, inductor or transformer) during the primary stroke and transferred to the output during the secondary stroke. Examples of such SMPS include a flyback converter, a buck converter and a buck-boost converter.

(21) While the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only and is not intended to limit the invention.