Neutral-point voltage balance control method and system for three-level converter in full power factor range

Abstract

A neutral-point voltage balance control method and system for a three-level converter in a full power factor range. The method includes: using a large, medium, and zero vector modulation method to synthesize a reference voltage vector, and duty cycles of a large vector, a medium vector, and a zero vector; obtaining a voltage difference between two dc-link capacitors of signal acquisition, and the voltage difference as a neutral-point potential of the three-level converter; according to a value relationship between the neutral-point potential of the three-level converter and a specified threshold, selecting a small vector and calculating a duty cycle of the small vector; and updating a duty cycle of each basic vector, and obtaining a switching sequence for controlling a power switch of a three-phase bridge arm. An amplitude of a common-mode voltage of an NPC three-level converter is equal to one sixth of a dc-link voltage.

Claims

1. A neutral-point voltage balance control method for a three-level converter in a full power factor range, comprising: using a large, medium, and zero vector modulation method to synthesize a reference voltage vector, and respectively determining duty cycles of a large vector, a medium vector, and a zero vector; obtaining a voltage difference between two dc-link capacitors by means of signal acquisition, and determining the voltage difference as a neutral-point potential of the three-level converter; according to a value relationship between the neutral-point potential of the three-level converter and a specified threshold, selecting a small vector and calculating a duty cycle of the small vector; and updating a duty cycle of each basic vector, and obtaining a switching sequence for controlling a power switch of a three-phase bridge arm.

2. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 1, wherein the respectively determining duty cycles of a large vector, a medium vector, and a zero vector is specifically: constructing a volt-second balance equation according to the large vector, the medium vector, the zero vector, and a relationship between their respective duty cycles and the reference voltage vector, and obtaining the duty cycles of the large vector, the medium vector, and the zero vector by solving the volt-second balance equation.

3. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 1, wherein the large vector, the medium vector, the zero vector, and the small vector are respectively selected as basic vectors, and there are six large vectors, six medium vectors, six small vectors, and one zero vector.

4. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 1, wherein when the neutral-point potential of the three-level converter is greater than the specified threshold, a PI controller is used to obtain the duty cycle of the selected small vector.

5. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 1, wherein when the neutral-point potential of the three-level converter is less than or equal to the specified threshold, the small vector is selected according to a sector in which the reference voltage vector locates and a situation of a three-phase output current; then, the duty cycle of each basic vector is updated, and the switching sequence is redesigned.

6. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 5, wherein when the reference voltage vector is in sector 1: if a phase B current is greater than 0 and a phase A current is greater than 0, or if a phase B current is less than 0 and a phase A current is less than 0, a large vector PNN, a medium vector PON, a small vector POO, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OOO-POO-PON-PNN-PON-POO-OOO.

7. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 5, wherein when the reference voltage vector is in sector 1: if a phase B current is greater than 0 and a phase C current is greater than 0, or if a phase B current is less than 0 and a phase C current is less than 0, a large vector PNN, a medium vector PON, a small vector OON, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OOO-OON-PON-PNN-PON-OON-OOO.

8. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 5, wherein when the reference voltage vector is in sector 1: if a phase B current is greater than 0 and both a phase A current and a phase C current are less than 0, or if a phase B current is less than 0 and both a phase A current and a phase C current are greater than 0, a large vector PNN, a medium vector PON, a small vector OPO, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OPO-OOO-PON-PNN-PON-OOO-OPO.

9. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 6, wherein when the reference voltage vector is in other sectors, a method similar to the method for sector 1 is used to determine the duty cycle of the small vector, and the determining is performed through analysis with reference to symmetry of a space vector diagram.

10. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 1.

11. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 7, wherein when the reference voltage vector is in other sectors, a method similar to the method for sector 1 is used to determine the duty cycle of the small vector, and the determining is performed through analysis with reference to symmetry of a space vector diagram.

12. The neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 8, wherein when the reference voltage vector is in other sectors, a method similar to the method for sector 1 is used to determine the duty cycle of the small vector, and the determining is performed through analysis with reference to symmetry of a space vector diagram.

13. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 2.

14. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 3.

15. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 4.

16. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 5.

17. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 6.

18. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 7.

19. A neutral-point voltage balance control system for a three-level converter in a full power factor range, comprising a server, wherein the server comprises a memory, a processor, and a computer program that is stored in the memory and that can run on the processor, and when executing the program, the processor implements the neutral-point voltage balance control method for a three-level converter in a full power factor range according to claim 8.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings constituting a part of this application are used for providing further understanding for this application. Exemplary embodiments of this application and descriptions thereof are used for explaining this application and do not constitute any inappropriate limitation to this application.

(2) FIG. 1 is a topology of an NPC three-level converter system in Embodiment 1;

(3) FIG. 2 is a space vector diagram of a neutral-point voltage balance control method for a three-level converter in a full power factor range in Embodiment 1;

(4) FIG. 3 is a control block diagram of the neutral-point voltage balance control method for a three-level converter in a full power factor range in Embodiment 1;

(5) FIG. 4 is simulation waveforms of the proposed method and conventional space voltage vector modulation when power factor PF=1 in Embodiment 1, where the simulation waveforms are respectively for three-phase currents, a line voltage, a common-mode voltage, and upper and lower dc-link capacitor voltages from top to bottom; and

(6) FIG. 5 is simulation waveforms of the proposed method and conventional space voltage vector modulation when power factor PF=0 in Embodiment 1, where the simulation waveforms are respectively for three-phase currents, a line voltage, a common-mode voltage, and upper and lower dc-link capacitor voltages from top to bottom.

DETAILED DESCRIPTION

(7) It should be noted that, the following detailed descriptions are all exemplary, and are intended to provide further descriptions of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs.

(8) It should be noted that terms used herein are only for the purpose of describing specific implementations and are not intended to limit the exemplary implementations of this application. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. In addition, it should further be understood that terms “comprise” and/or “include” used in this specification indicate that there are features, steps, operations, devices, components, and/or combinations thereof.

Embodiment 1

(9) A neutral-point voltage balance control method for a three-level converter in a full power factor range is disclosed in one or more implementations. As shown in FIG. 3, the method includes the following steps:

(10) (1) Use a large, medium, and zero vector modulation method to synthesize a reference voltage vector, and respectively determine duty cycles of a large vector, a medium vector, and a zero vector.

(11) (2) Obtain a voltage difference between two dc-link capacitors by means of signal acquisition, and determine the voltage difference as a neutral-point potential of the three-level converter.

(12) (3) According to a value relationship between the neutral-point potential of the three-level converter and a specified threshold, select a small vector and calculate a duty cycle of the small vector.

(13) (4) Update a duty cycle of each basic vector, and obtain a switching sequence for controlling a power switch of a three-phase bridge arm.

(14) The method is mainly for an NPC three-level converter system. As shown in FIG. 1, the NPC three-level converter system includes a phase A bridge arm, a phase B bridge arm, and a phase C bridge arm, and each bridge arm includes four power switches and two clamping diodes. In the dc-link, there exist two filter capacitors connected in series, a neutral point is formed in the middle between the two filter capacitors, and the middle between the two clamping diodes of each bridge arm is connected to the neutral point.

(15) It should be understood that the power switch is an insulated gate bipolar transistor (IGBT). Certainly, the power switch may also be implemented by using a transistor of another type.

(16) Specifically, there are three working states P, O, and N for each bridge arm of the NPC three-level converter system. The neutral point of the two dc-link filter capacitors is used as a reference point. In the state P, an output voltage of the bridge arm is half of an output DC voltage value; in the state O, the output voltage of the bridge arm is zero; and in the state N, the output voltage of the bridge arm is negative half of the output DC voltage value.

(17) Switch-on or switch-off of the power switch is completed by a control system.

(18) In the method of the present invention, a new space vector modulation method is designed to control switch-on or switch-off of the power switch in the NPC three-level converter system, and a total of 19 basic vectors are used. According to different amplitudes, the basic vectors are classified into a large vector, a medium vector, a small vector, and a zero vector. FIG. 2 shows a space vector diagram.

(19) Table 1 lists basic voltage vectors selected in the method of the present invention and corresponding common-mode voltage amplitudes.

(20) A common-mode voltage is defined as an average value of three-phase output voltages of an NPC three-level converter.
v.sub.CM=⅓(v.sub.AO+v.sub.BO+v.sub.CO)  (1)

(21) TABLE-US-00001 TABLE 1 Basic voltage vectors selected in the method of the present invention and corresponding common-mode voltage amplitudes Common- Common- Common- mode mode mode Vector Class State Voltage State Voltage State Voltage Large vector PNN −V.sub.dc/6 PPN  V.sub.dc/6 NPN −V.sub.dc/6 NPP  V.sub.dc/6 NNP −V.sub.dc/6 PNP  V.sub.dc/6 Medium vector PON 0 OPN 0 NPO 0 NOP 0 ONP 0 PNO 0 Small P- POO  V.sub.dc/6 OPO  V.sub.dc/6 OOP  V.sub.dc/6 vector type N- OON −V.sub.dc/6 NOO −V.sub.dc/6 ONO −V.sub.dc/6 type Zero vector OOO 0 — — — —

(22) First, a large, medium, and zero vector modulation method is used to synthesize a reference voltage vector, and a volt-second balance equation is obtained.

(23) $\begin{array}{cc}\{\begin{array}{c}{V}_L{d}_L+V_M{d}_M+V_Z{d}_Z=V_{\mathrm{ref}}\\ d_L+d_M+d_Z=1\end{array}& \left(2\right)\end{array}$
d.sub.L, d.sub.M, and d.sub.Z are respectively duty cycles of the large vector, the medium vector, and the zero vector, and V.sub.ref is an amplitude of the reference voltage vector.

(24) The volt-second balance equation is solved to obtain the duty cycles of the large vector, the medium vector, and the zero vector, which are respectively:

(25) $\begin{array}{cc}\{\begin{array}{c}{d}_L=\sqrt{3}m\sin \left(\frac{\pi }{6}-\theta \right)\\ d_M=2m\sin \theta \\ d_Z=1-\left(d_L+d_M\right)\end{array}& \left(3\right)\end{array}$

(26) m is a modulation depth and is defined as

(27) $m=\frac{\sqrt{3}{V}_{\mathrm{ref}}}{V_{\mathrm{dc}}}.$
V.sub.ref is the amplitude of the reference voltage vector, and V.sub.dc is a DC input voltage.

(28) A neutral-point potential of the NPC three-level converter is equal to a difference of two capacitor voltages, that is, Δv=v.sub.p−v.sub.N A neutral-point potential threshold Δv.sub.th is set. When Δv>Δv.sub.th, a PI controller is used to obtain a duty cycle of a selected small vector. Specifically, a voltage deviation of two dc-link capacitors is input to a PI controller, and an absolute value operation is performed for output of the PI controller, to obtain the duty cycle of the selected small vector. When Δv≤v.sub.th, the following steps are used to accurately calculate the duty cycle of the selected small vector.

(29) To suppress low-frequency oscillation of the neutral-point potential, the small vector is selected according to a sector in which the reference voltage vector locates and a situation of a three-phase output current; then, the duty cycle of each basic vector is updated, and the switching sequence is redesigned. After the selection of the small vector, it is assumed that duty cycles of the large vector, the medium vector, the small vector, and the zero vector are respectively updated to d′.sub.L, d′.sub.M, d′.sub.S, and d′.sub.Z. i.sub.a, i.sub.b, and i.sub.c respectively represent a phase A output current, a phase B output current, and a phase C output current of the NPC three-level converter system. Implementation steps of the method of the present invention are analyzed by using an example in which the reference voltage vector is in sector 1. The implementation steps include the following six cases.

(30) (1) When a phase B current is greater than 0 and a phase A current is greater than 0, a large vector PNN, a medium vector PON, a small vector POO, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OOO-POO-PON-PNN-PON-POO-OOO. The duty cycle of each basic vector is updated according to a modified volt-second balance equation.

(31) $\begin{array}{cc}\{\begin{array}{c}{d}_L^{\prime }=d_L-\frac{y}{2}\\ d_M^{\prime }=d_M\\ d_S^{\prime }=y\\ d_Z^{\prime }=d_Z-\frac{y}{2}\end{array}& \left(4\right)\end{array}$

(32) To eliminate low-frequency oscillation of the neutral-point potential, it is assumed that neutral-point potential fluctuation generated by the medium vector PON is equal to that generated by the small vector POO, that is,
d.sub.Mi.sub.b=yi.sub.a  (5)

(33) The following is obtained.

(34) $\begin{array}{cc}y=\frac{d_M{i}_b}{i_a}& \left(6\right)\end{array}$

(35) A value of the duty cycle of the small vector is further obtained by considering a constraint that the duty cycle of the small vector needs to meet, and the value is:

(36) $\begin{array}{cc}0<y=\min \left\{\frac{d_M{i}_b}{i_a},2d_L,2d_Z\right\}& \left(7\right)\end{array}$

(37) (2) When a phase B current is greater than 0 and a phase C current is greater than 0, a large vector PNN, a medium vector PON, a small vector OON, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OOO-OON-PON-PNN-PON-OON-OOO. The duty cycle of each basic vector is updated according to a modified volt-second balance equation.

(38) $\begin{array}{cc}\{\begin{array}{c}{d}_L^{\prime }=d_L+\frac{y}{2}\\ d_M^{\prime }=d_M-y\\ d_S^{\prime }=y\\ d_Z^{\prime }=d_Z-\frac{y}{2}\end{array}& \left(8\right)\end{array}$

(39) To eliminate low-frequency oscillation of the neutral-point potential, it is assumed that neutral-point potential fluctuation generated by the medium vector PON is equal to that generated by the small vector OON, that is,
(d.sub.M−y)i.sub.b=yi.sub.c  (9)

(40) The following is obtained.

(41) $\begin{array}{cc}y=\frac{d_M{i}_b}{i_b+i_c}& \left(10\right)\end{array}$

(42) A value of the duty cycle of the small vector is further obtained by considering a constraint that the duty cycle of the small vector needs to meet, and the value is:

(43) $\begin{array}{cc}0<y=\min \left\{\frac{d_M{i}_b}{i_b+i_c},2d_Z\right\}& \left(11\right)\end{array}$

(44) (3) When a phase B current is greater than 0 and both a phase A current and a phase C current are less than 0, a large vector PNN, a medium vector PON, a small vector OPO, and a zero vector OOO are selected to synthesize the reference voltage vector, and the switching sequence is designed as OPO-OOO-PON-PNN-PON-OOO-OPO. The duty cycle of each basic vector is updated according to a modified volt-second balance equation.

(45) 0$\begin{array}{cc}\{\begin{array}{c}{d}_L^{\prime }=d_L+y\\ d_M^{\prime }=d_M-y\\ d_S^{\prime }=y\\ d_Z^{\prime }=d_Z-y\end{array}& \left(12\right)\end{array}$

(46) To eliminate low-frequency oscillation of the neutral-point potential, it is assumed that neutral-point potential fluctuation generated by the medium vector PON is equal to that generated by the small vector OPO, that is,
(d.sub.M−y)i.sub.b=yi.sub.b  (13)

(47) The following is obtained.

(48) $\begin{array}{cc}y=\frac{d_M}{2}& \left(14\right)\end{array}$

(49) A value of the duty cycle of the small vector is further obtained by considering a constraint that the duty cycle of the small vector needs to meet, and the value is:

(50) $\begin{array}{cc}0<y=\min \left\{\frac{d_M}{2},2d_Z\right\}& \left(15\right)\end{array}$

(51) (4) When a phase B current is less than 0 and a phase A current is less than 0, selection of basic voltage vectors, duty cycle update, and switching sequence design are the same as those in case (1).

(52) (5) When a phase B current is less than 0 and a phase C current is less than 0, selection of basic voltage vectors, duty cycle update, and switching sequence design are the same as those in case (2).

(53) (6) When a phase B current is less than 0 and both a phase A current and a phase C current are greater than 0, selection of basic voltage vectors, duty cycle update, and switching sequence design are the same as those in case (3).

(54) When the reference voltage vector is in other sectors, a method similar to the method for sector 1 can be used, and analysis is performed with reference to symmetry of a space vector diagram.

(55) FIG. 4 and FIG. 5 are simulation waveforms of the proposed method and conventional space voltage vector modulation when power factor PF=1 and PF=0 respectively, where the simulation waveforms are respectively for three-phase currents, a line voltage, a common-mode voltage, and upper and lower dc-link capacitor voltages from top to bottom. When time t<0.5 s, the proposed method is used. When t>0.5 s, the conventional space vector modulation method is used. It can be seen that a sinusoidal degree of a three-phase current is similar in the two methods, and a line voltage includes five levels in these two methods. However, a common-mode voltage in the proposed method is only half of that in the conventional method, so that an amplitude of the common-mode voltage is effectively reduced. In addition, neutral-point potential fluctuation is effectively suppressed in the proposed method, compared with the conventional method. Especially when PF=0, neutral-point potential fluctuation in the conventional method is greater than 10V, but the neutral-point potential fluctuation of the proposed method is effectively reduced.

Embodiment 2

(56) A neutral-point voltage balance control system for a three-level converter in a full power factor range is disclosed in one or more implementations. The system includes a controller and an algorithm program. When executing the algorithm program, the controller implements the neutral-point voltage balance control method for a three-level converter in a full power factor range in Embodiment 1.

(57) The foregoing specific implementations of this disclosure are described with reference to the accompanying drawings, but are not intended to limit the protection scope of this disclosure. A person skilled in the art should understand that various modifications or variations may be made without creative efforts based on the technical solutions of this disclosure, and such modifications or variations shall fall within the protection scope of this disclosure.