BOOTSTRAP PRE-CHARGE CIRCUIT IN TOTEM-POLE POWER FACTOR CORRECTION CONVERTER

Abstract

A power factor correction converter that outputs a DC output voltage from an AC input voltage, includes two channels each including a high-side switch and a low-side switch connected in cascade between a positive output terminal and a negative output terminal of the power factor correction converter and with a node between the high-side switch and the low-side switch; an inductor connected to a first terminal of the AC input voltage and the first node; a gate driver connected to the second high-side switch and the second low-side switch; a bootstrap circuit connected to the second node and the gate driver; wherein the second node is connected to a second terminal of the AC input voltage; and the bootstrap circuit is pre-charged at beginnings of negative half-cycles of the AC input voltage.

Claims

1: A power factor correction converter that outputs a DC output voltage from an AC input voltage, the power factor correction converter comprising: a first high-side switch and a first low-side switch connected in cascade between a positive output terminal and a negative output terminal of the power factor correction converter and with a first node between the first high-side switch and the first low-side switch; a second high-side switch and a second low-side switch connected in cascade between the positive output terminal and the negative output terminal and with a second node between the second high-side switch and the second low-side switch; an inductor connected to a first terminal of the AC input voltage and the first node; a gate driver connected to the second high-side switch and the second low-side switch; a bootstrap circuit connected to the second node and the gate driver; wherein the second node is connected to a second terminal of the AC input voltage; and the bootstrap circuit is pre-charged at beginnings of negative half-cycles of the AC input voltage.

2: The power factor correction converter of claim 1, wherein the first high-side switch and the first low-side switch define a first channel; and the second high-side switch and the second low-side switch are line transistors.

3: The power factor correction converter of claim 1, further comprising a third high-side switch and a third low-side switch connected in cascade between the positive output terminal and the negative output terminal and with a third node between the second high-side switch and the second low-side switch; wherein the first high-side switch and the first low-side switch define a first channel; the second high-side switch and the second low-side switch define a second channel; and the third high-side switch and the third low-side switch are line transistors.

4: The power factor correction converter of claim 3, wherein the first channel is engaged by turning on and off the first high-side switch and the first low-side switch in a complementary manner; and the second channel is disengaged by turning off both the second high-side switch and the second low-side switch, except to turn on the second low-side switch to pre-charge the bootstrap circuit at the beginnings of the negative half-cycles of the AC input voltage.

5: The power factor correction converter of claim 4, wherein, when the second channel is engaged by turning on and off the second high-side switch and the second low-side switch in a complementary manner, the bootstrap circuit is not pre-charged.

6: The power factor correction converter of claim 3, wherein during positive half-cycles of the AC input voltage: during boost operation of the first channel, the first low-side switch and the third low-side switch are turned on, and the first high-side switch and the third high-side switch are turned off; during boost operation of the second channel, the second low-side switch and the third low-side switch are turned on, and the second high-side switch and the third high-side switch are turned off; during synchronous operation of the first channel, the first high-side switch and the third low-side switch are turned on, and the first low-side switch and the third high-side switch are turned off; and during synchronous operation of the second channel, the second high-side switch and the third low-side switch are turned on, and the second low-side switch and the third high-side switch are turned off; and during negative half-cycles of the AC input voltage: during boost operation of the first channel, the first high-side switch and the third high-side switch are turned on, and the first low-side switch and the third low-side switch are turned off; during boost operation of the second channel, the second high-side switch and the third high-side switch are turned on, and the second low-side switch and the third low-side switch are turned off; during synchronous operation of the first channel, the first low-side switch and the third high-side switch are turned on, and the first high-side switch and the third low-side switch are turned off; and during synchronous operation of the second channel, the second low-side switch and the third high-side switch are turned on, and the second high-side switch and the third low-side switch are turned off.

7: The power factor correction converter of claim 1, wherein the bootstrap circuit includes a diode and a capacitor connected in series with each other; and pre-charging the bootstrap circuit pre-charges the capacitor.

8: A control circuit for a power factor correction converter that outputs a DC output voltage from an AC input voltage, the control circuit comprising: a gate driver including: a high-side driver terminal connected to a high-side switch of the power factor correction converter to turn the high-side switch on and off; a low-side driver terminal connected to a low-side switch of the power factor correction converter to turn the low-side switch on and off; a high-side ground terminal connected to a node between the high-side switch and the low-side switch; a low-side ground terminal connected to a negative output terminal of the power factor correction converter; a high-side voltage terminal; and a low-side voltage terminal; a controller connected to the gate driver; a bootstrap circuit including: a bootstrap capacitor connected in parallel with the high-side voltage terminal and the high-side ground terminal and connected to the node; and a diode connected between the bootstrap capacitor and the low-side voltage terminal; and a capacitor connected in parallel with the low-side voltage terminal and the low-side ground terminal and connected to the negative output terminal; wherein the controller is programmed or configured to turn on the low-side switch to pre-charge the bootstrap capacitor at beginnings of negative half-cycles of the AC input voltage.

9: A power factor correction converter including the control circuit of claim 8, wherein the controller disengages a channel of the power factor correction converter by turning off both the high-side switch and the low-side switch, except to turn on the second low-side switch to pre-charge the bootstrap circuit at the beginnings of the negative half-cycles of the AC input voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a circuit diagram of a single-channel PFC totem-pole boost converter according to a preferred embodiment of the present invention.

[0020] FIG. 2 is a circuit diagram of a dual-channel PFC totem-pole boost converter according to a preferred embodiment of the present invention.

[0021] FIGS. 3A-3D are circuit diagrams that show current flow in a single-channel PFC totem-pole boost converter according to a preferred embodiment of the present invention.

[0022] FIG. 4 is a circuit diagram of a gate driver with an external bootstrap circuit according to a preferred embodiment of the present invention.

[0023] FIG. 5 shows waveforms illustrating operation of a bootstrap pre-charging circuit according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0024] FIG. 1 is a circuit diagram of a single-channel TPPFC boost converter according to a preferred embodiment of the present invention. In FIG. 1, the single-channel TPPFC converter includes an AC voltage input V.sub.AC, an inductor L.sub.1, switches Q.sub.1 and Q.sub.2 that can act like switching devices to control the flow of current, switches Q.sub.3 and Q.sub.4 that can act as line transistors in that the switches Q.sub.3 and Q.sub.4 are turned on and off at the input line frequency, usually about 50 Hz to about 60 Hz to mimic diodes, and a load capacitance C.sub.L. The switches Q.sub.1 and Q.sub.2 are connected in cascade, and the switches Q.sub.3 and Q.sub.4 are connected in cascade. The inductor L.sub.1 is connected between a terminal of the AC voltage input V.sub.AC and a node between the switches Q.sub.1 and Q.sub.2. The other terminal of the AC voltage input V.sub.AC is connected to a node between the switches Q.sub.3 and Q.sub.4. The load capacitance C.sub.L is connected in parallel with the switches Q.sub.1 and Q.sub.2 and with the switches Q.sub.3 and Q.sub.4. The switches Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4 can be any suitable switches, including MOSFETs, GaN transistors, SiC transistors, or the like.

[0025] FIG. 2 is a circuit diagram of a dual-channel TPPFC boost converter according to a preferred embodiment of the present invention. FIG. 2 shows a dual-channel TPPFC converter similar to that shown in FIG. 1 and includes an AC voltage input V.sub.AC, an inductor L.sub.1, switches Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4 that can act like switching devices to control the flow of current, and switches Q.sub.5 and Q.sub.6 that can act as line transistors in that the switches Q.sub.5 and Q.sub.6 are turned on and off to mimic diodes, and a load capacitance C.sub.L. In the first channel (also referred to as the primary switching leg or channel 1), the inductor L.sub.1 is connected between a terminal of the AC voltage input V.sub.AC and a node between the switches Q.sub.1 and Q.sub.2. In the second channel (also referred to as the secondary switching leg or channel 2), the inductor L.sub.2 is connected between the same terminal of the AC voltage input V.sub.AC as the inductor L.sub.1 and a node between the switches Q.sub.3 and Q.sub.4. The switches Q.sub.1 and Q.sub.2 are connected in cascade, the switches Q.sub.3 and Q.sub.4 are connected in cascade, and the switches Q.sub.5 and Q.sub.6 are connected in cascade. The other terminal of the AC voltage input V.sub.AC is connected to a node between the switches Q.sub.5 and Q.sub.6. The load capacitance C.sub.L is connected in parallel with the switches Q.sub.1 and Q.sub.2, with the switches Q.sub.3 and Q.sub.4, and with the switches Q.sub.5 and Q.sub.6. The switches Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, and Q.sub.6 can be any suitable switches, including MOSFETs, GaN transistors, SiC transistors, or the like.

[0026] FIGS. 3A-3D are circuit diagrams that show the principle of operation and current flow in a single-channel TPPFC boost converter according to a preferred embodiment of the present invention. FIGS. 3A and 3B show the principle of operation and current flow during the positive AC half-cycle, and FIGS. 3C and 3D show the principle of operation and current flow during the negative AC half-cycle. The current flow in FIGS. 3A-3D is represented by the dotted line arrow. Each switching cycle includes a boost portion as shown FIGS. 3A and 3C in which energy is stored in the inductor L.sub.1 and a synchronous portion as shown in FIGS. 3B and 3D in which power is provided to the load. For simplicity, duty cycle D will refer to the boost portion of the switching cycle, and duty cycle 1-D will refer to the synchronous portion of the switching cycle. For switches in a cascade configuration, one switch is turned on for the boost portion of the switching cycle with a duty cycle D and then switched off, while the other transistor is switched on for the remainder of switching cycle, i.e., duty cycle 1-D, and then turned off at the end of the switching cycle. The process is repeated in the next switching cycle.

[0027] In FIGS. 3A and 3B, switch Q.sub.2 acts as a boost switch in the positive half cycle of the AC voltage during the boost portion of the switching cycle, and switch Q.sub.1 acts as a synchronous switch in the positive half cycle of the AC voltage during the synchronous portion of the switching cycle. During the boost portion, switch Q.sub.2 is turned ON with a duty cycle D. The duty cycle D is determined by the circuit control for each switching cycle to regulate the output of the converter and is within a range from 0 to 1.

[0028] Since switch Q.sub.2 is driven by the low-side gate driver, a positive voltage gate-source Vgs is easily provided. In the same positive AC half-cycle and during the synchronous portion of the switching cycle, switch Q.sub.1 operates as a synchronous transistor that is turned ON with duty cycle 1-D, as shown in FIG. 3B. The synchronous transistors are switched at the switching frequency, e.g. 100 kHz. As shown in FIGS. 3A and 3B, switch Q.sub.4 is ON during the entire positive AC half-cycle.

[0029] After the positive AC half-cycle, the input voltage is reversed and the converter begins operation in the negative AC half-cycle as shown in FIGS. 3C and 3D. In the negative AC half-cycle, roles of the switches are swapped. Thus, the switch Q.sub.1 is a boost switch during the boost portion of the switching cycle and is turned ON with a duty cycle of D, while switch Q.sub.2 is a synchronous transistor during the synchronous portion of the switching cycle and is turned on with a duty cycle 1-D. Switch Q.sub.3 is ON during the entire negative AC half-cycle. Therefore, switches Q.sub.3 and Q.sub.4 alternately change roles according to the line frequency (i.e., 60 Hz or 50 Hz).

[0030] In a dual-channel TPPFC topology, the second channel is usually disengaged to eliminate unnecessary switching loses when the power requirement is low to improve efficiency. During light-load operation, the TPPFC converter's output power is entirely provided by the first channel, and in this mode, the TPPFC converter operates as a single-channel TPPFC converter. The second channel of the dual-channel TPPFC converter is required to immediately engage in case of: (i) significant load increase, or (ii) recovery from line drop-out (drop-out ride-through) when both channels should provide power for faster recovery of the TPPFC converter's output voltage. Drop-out is a condition when AC power is lost for a short period of time, usually due to unexpected occurrences in the grid or input power supply. During such drop-out events, the converter should continue to supply rated output power to the load. Power conversion systems can be designed to be able to generate power from internal power storage for a few milliseconds during which the AC input is out of range (i.e., dropped out). The ability of the converter to supply the load without interruption during this type of event is the so-called ride-through capability. However, the problems with operation of the second channel with a bootstrapped power supply for the high-side gate driver described above arise when it is required to engage the second channel in the negative portion of the AC voltage cycle.

[0031] FIG. 4 is a circuit diagram of a bootstrap pre-charging circuit that includes a gate driver with an external bootstrap power supply according to a preferred embodiment of the present invention. FIG. 4 shows a gate driver circuit 3 with a bootstrapped power supply, including capacitor C.sub.1 and diode D.sub.1, for the high-side switch Q.sub.3 in the second channel of a dual-channel TPPFC converter. The bootstrapped power supply is connected between terminals VDDA and GNDA of the gate driver 3. As shown in FIG. 4, the bootstrap power supply can include bootstrap capacitor C.sub.1 and diode D.sub.1.

[0032] As shown in FIG. 4, the second channel includes switches Q.sub.3 and Q.sub.4. The Q.sub.3-Q.sub.4 cascade is connected between the positive output terminal PFC V+ and the negative output terminal PFC V− of the dual-channel TPPFC converter and is joined at the half-bridge node HB. The power supply for the low-side gate driver is connected between terminals VDDB and GNDB. The power supply for the low-side gate driver can include capacitor C.sub.2. The power supply for both the high- and low-side switches Q.sub.3 and Q.sub.4 and input to VDDA and VDDB is VCC. The output driving pulses for the high-side switch Q.sub.3 are generated on terminal OUTA of the gate driver 3, while the output driving pulses for the low-side switch Q.sub.4 are generated on terminal OUTB of the gate driver 3. The internal pulse width modulator (PWM) 2 of the microcontroller 1 generates the input pulses IN_A and IN_B.

[0033] As shown in FIG. 4, the microcontroller 1 and the PWM 2 can be included in a single integrated circuit (IC), and the gate driver 3 can be a separate IC. Other arrangements are possible. For example, the microcontroller 1, PWM 2, and gate driver 3 can be included in a single IC or can each be a separate IC. The ICs can be a dedicated circuit, a general purpose processing unit, a programmable device, or the like. Optionally, the circuit functions can be separate or combined into a single device. That is, the circuitry can be implemented on any type of digital processor regardless of the architecture, including but not limited to a digital signal processor (DSP), programmable intelligence computer (PIC), field-programmable gate array (FPGA), AVR microcontroller, programmable microcontroller, etc. The control algorithm can be executed at arbitrary speed with a custom sampling rate depending on the converter switching frequency. The controller gains and loop bandwidth can be adjusted in a way to fit a design and provide stable control loop.

[0034] If the second channel of the TPPFC converter is disengaged, and the switching operation starts in the negative AC half-cycle when the high-side switch Q.sub.3 is the boost transistor, the converter will be unable to start operating if the bootstrap capacitor C.sub.1 is discharged because the bootstrap capacitor C.sub.1 cannot provide the minimum required gate-source voltage Vgs to turn ON switch Q.sub.3. Failure to start operating will introduce a delay of up to half an AC cycle.

[0035] To eliminate a delay in starting the second channel shown in FIG. 4, the bootstrap capacitor C.sub.1 is pre-charged at the beginning of each negative half-cycle after the input voltage zero crossing. The dashed line arrow shown in FIG. 4 represents the current path that is established to charge bootstrap capacitor C.sub.1. This current path from the power supply VCC to the PFC V− terminal is available only when low-side switch Q.sub.4 is ON.

[0036] FIG. 5 shows waveforms of driving signals illustrating operation of the bootstrap pre-charging circuit shown in FIG. 4 according to a preferred embodiment of the present invention. FIG. 5 shows that at time T.sub.0 a bootstrap circuit enable signal BSC_EN transitions from low to high, which is the enable flag to the pre-charge circuit. Signal BSC_EN is a control signal generated in the microcontroller 1 as part of the control algorithm that controls the pre-charging, and becomes high after power-up initialization. In operation, the PWM 2 drives switches Q.sub.3 and Q.sub.4 in complementary mode via output terminals OUTA and OUTB. At time T.sub.1 during an AC input zero-crossing from a positive AC half cycle to a negative AC half cycle, the PWM 2 independently drives switches Q.sub.3 and Q.sub.4. In this case, the pre-charge control disables the PWM 2 to switch Q.sub.3 to ensure that switch Q.sub.3 is safely turned OFF before switching ON switch Q.sub.4. This avoids the possibility of a shoot-through by accidentally simultaneously turning ON both switches Q.sub.3 and Q.sub.4. When switch Q.sub.4 is switched ON, the current path to charge C.sub.1 is established, and a voltage on bootstrap capacitor C.sub.1 rises instantaneously to the voltage level of power supply VCC. The required time to charge bootstrap capacitor C.sub.1 is determined in the design process and can be programmed and maintained by the microcontroller 1. If the charging current is limited, the charging period can be extended to several switching cycles.

[0037] When the charging of bootstrap capacitor C.sub.1 is over at the end of time T.sub.1, the PWM 2 control is changed back to the complementary MOSFET drive mode. From time T.sub.1 to T.sub.2, the voltage across bootstrap capacitor C.sub.1 linearly drops due to leakage currents that discharge the bootstrap capacitor C.sub.1. Proper selection of bootstrap capacitor C.sub.1 is necessary to ensure that stored energy is sufficient to turn ON switch Q.sub.3 during the entire interval from time T.sub.1 to T.sub.2. At time T.sub.2, the charging process is repeated to restore the voltage across bootstrap capacitor C.sub.1 to the voltage level of power supply VCC. In the same fashion, the procedure to pre-charge bootstrap capacitor C.sub.1 is applied at the beginning of each negative AC half cycle of the input voltage. As shown in FIG. 5, at time T.sub.3, microcontroller generated signal CH.sub.2_EN transitions from low to high, which allows the second channel to start switching, and the TPPFC converter's second channel begins operation. At time T.sub.4, signal BSC_EN transitions from high to low to disable the pre-charge circuit. Therefore, switch Q.sub.4 charge pulses during an AC input zero-crossing from a positive AC half cycle to a negative AC half cycle. Once switching operation has initiated, pre-charging bootstrap capacitor C.sub.1 is no longer needed because the bootstrap capacitor's C.sub.1 voltage is maintained by normal operation of the converter.

[0038] It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.