Method for making a wideband Doherty amplifier with reduced plan width and amplifier thereof

Abstract

A method for making a wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, the amplifier including: a signal source adapted to generate an input signal; a hybrid coupler or a splitter network adapted to receive the input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input the first output signal; a peak amplifier adapted to receive as input the second output signal; an output network arranged between the carrier and peak amplifiers and a delivery node adapted to be connected to a load, the output network including a recombination node adapted to receive the signals output by the carrier amplifier and the peak amplifier, and a transmission line implemented as a printed circuit track applied to an insulating substrate, wherein capacitors are inserted on the track which are adapted to compensate for the non-ideality characteristics of the semiconductor used for making the line.

Claims

1. A method for making a wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, said amplifier comprising: a signal source adapted to generate an input signal; means, in particular a hybrid coupler or a splitter network, adapted to receive said input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input said first output signal; a peak amplifier adapted to receive as input said second output signal; an output network arranged between said carrier and peak amplifiers and a delivery node adapted to be connected to a load, said output network comprising a recombination node adapted to receive the signals output by said carrier amplifier and said peak amplifier, and a transmission line implemented as a printed circuit track applied to an insulating substrate, said method comprising the steps of: a) determining an index n indicative of a mismatching considered as acceptable of an impedance value at said recombination node; b) determining a total capacity of said transmission line; c) determining a total inductance of said transmission line from said total capacity and from a cut-off frequency of said wideband Doherty amplifier, imposing that said cut-off frequency is higher than said maximum frequency value; d) based on said total inductance and on the material of said track and said insulating substrate of said transmission line, determining a maximum distance at which two capacitors should be inserted on said transmission line; e) determining a minimum number of steps where to locate one or more capacitors based on the total length of said line and a step length, imposing that said step length is shorter than or equal to said maximum distance; f) inserting on said track of said transmission line one or more capacitors based on said minimum number of steps, said one or more capacitors having a capacity value equal to said total capacity divided by the product of said minimum number of steps and said index n.

2. The method for making a wideband Doherty amplifier according to claim 1, wherein said capacitors are inserted so as to be distributed at a constant mutual distance along said transmission line.

3. The method for making a wideband Doherty amplifier according to claim 1, wherein said capacitors are inserted at an irregular mutual distance along said transmission line.

4. The method according to claim 1, wherein at least one of said inserted capacitors is replaced by a plurality of capacitors having the same capacity as said at least one capacitor.

5. The method according to claim 1, wherein said transmission line comprises one of the following lines: a delay line, arranged between said carrier amplifier and said peak amplifier, having an electric length equal to ¼ of a wave of the frequency of said input signal; a transformation line arranged between said recombination node and said delivery node; a first offset line, arranged between said peak amplifier and said transmission line, having an electric length equal to ¼ of a wave of the frequency of said input signal; a second offset line, arranged between said carrier amplifier and said recombination node, having an electric length equal to ¼ of a wave of the frequency of said input signal.

6. A Wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, said amplifier comprising: a signal source adapted to generate an input signal; means, in particular a hybrid coupler or a splitter network, adapted to receive said input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input said first output signal; a peak amplifier adapted to receive as input said second output signal; an output network arranged between said carrier and peak amplifiers and a delivery node adapted to be connected to a load, said output network comprising a recombination node adapted to receive the signals output by said carrier amplifier and said peak amplifier and a transmission line implemented as a printed circuit track applied to an insulating substrate, said amplifier being characterized in that it comprises one or more capacitors arranged on said track of said transmission line in accordance with the method according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further features and advantages of the present invention will become more apparent from the following description of an embodiment thereof as shown in the annexed drawings, which are supplied merely by way of non-limiting example, wherein:

(2) FIG. 1a is a block diagram of a prior-art Doherty amplifier in the classical configuration;

(3) FIG. 1b is a block diagram of a prior-art Doherty amplifier in the inverted configuration;

(4) FIGS. 1c and 1d illustrate two respective circuit configurations of prior-art Doherty amplifiers;

(5) FIGS. 2a, 2b and 2c illustrate, respectively, three equivalent circuits of a tract of infinitesimal length of a transmission line in case of negligible losses;

(6) FIG. 3 shows a graph representing the impedance mismatching introduced by the circuit addition of a capacitor to a transmission line of a wideband Doherty amplifier in accordance with the method of the present invention;

(7) FIGS. 4a, 4b and 4c illustrate, respectively, three circuits representative of a transmission line;

(8) FIG. 5 shows a block diagram of a method for making a wideband Doherty amplifier according to the present invention.

(9) FIG. 6 is a block diagram of a Doherty amplifier according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(10) With reference to FIG. 2a, there is shown a first simplified equivalent circuit 20 of a tract of infinitesimal length of a transmission line having negligible losses, such as, for example, the delay line 7 or the first offset line 13′ or the second offset line 13 or the transformation line 14 of the Doherty amplifier 10 of FIGS. 1a or 1b, comprising an inductance 21 of value L in series with a capacitor 22 of value C.

(11) In case of negligible resistive loss, the electric impedance Z and the electric length EL of the tract of infinitesimal length are respectively given, therefore, by the following formulae:

(12) $\begin{array}{cc}{Z}_1=\sqrt{\frac{L}{C}}& \left(1\right)\\ \mathrm{EL}=\omega l\sqrt{LC}& \left(2\right)\end{array}$

(13) where l is the physical length of the line and ω=2πf, where f is the frequency of the signal that flows through the line.

(14) With reference to FIG. 2b, there is shown a second circuit 25 identical to the one shown in FIG. 2a save for the addition, in parallel with the capacitor 22 of value C, of a second capacitor 23 of value C/n, where n is a number greater than zero belonging to the set of real numbers, e.g., the set of natural numbers.

(15) The equivalent capacity C.sub.eq of the second circuit 25 is given, therefore, by the formula:

(16) $\begin{array}{cc}{C}_{eq}=C\left(\frac{n+1}{n}\right)& \left(3\right)\end{array}$

(17) The introduction of the second capacitor 23 involves a variation in both the impedance Z.sub.2 and the electric length EL.sub.2 of the second circuit 25 in comparison with the first circuit 20. Using the formulae (1) and (2), one thus obtains that:

(18) $\begin{array}{cc}{Z}_2=\sqrt{\frac{L}{C}\left(\frac{n}{n+1}\right)}& \left(4\right)\\ E{L}_2=\omega l\sqrt{LC\left(\frac{n+1}{n}\right)}& \left(5\right)\end{array}$

(19) In order to restore the original value of the electric length of the first circuit 20, it is possible to change the value of the inductance 21 of the second circuit 25 by suitably multiplying it by a factor

(20) $\left(\frac{n}{n+1}\right).$

(21) A third circuit 30 will thus be obtained, which is shown in FIG. 2c, where the values of the impedance Z.sub.3 and of the electric length EL.sub.3 are expressed, again by applying the formulae (1) and (2), as:

(22) $\begin{array}{cc}{Z}_3=\sqrt{\frac{L}{C}}\left(\frac{n}{n+1}\right)& \left(6\right)\\ E{L}_3=\omega l\sqrt{LC}& \left(7\right)\end{array}$

(23) It can then be observed that the third circuit 30 has the same electric length as the first circuit 20, but a different impedance.

(24) In order to calculate the mismatching introduced by the impedance variation between the first circuit 20 and the third circuit 30, the following formula can be applied:

(25) $\begin{array}{cc}\Gamma =\frac{Z_3-Z_1}{Z_3+Z_1}& \left(8\right)\end{array}$

(26) With some simple mathematical passages, and defining RL=−20 login, the following Return Loss RL will be obtained:

(27) $\begin{array}{cc}RL=-20\log .Math.\frac{-1}{2n+1}.Math.& \left(9\right)\end{array}$

(28) FIG. 3 shows the graph of the Return Loss RL as a function of the value n. The value n represents, therefore, an index indicating the extent to which the inductance, and hence the line length, can be reduced to detriment of the impedance matching. The circuit designer can thus choose a value n that will allow obtaining a mismatching considered as acceptable. Such mismatching will essentially imply a variation in the impedance at the recombination node 9 of the circuit of FIG. 1a or FIG. 1b compared with the case wherein no capacitor is added to the circuit.

(29) From the graph of FIG. 3 it can be inferred that, e.g., considering 20 dB as an acceptable mismatching, n=5. In this example, therefore, the value of the capacitor that needs to be added to each infinitesimal tract of the transmission line taken into consideration is equal to C/5.

(30) Now, instead of adding a capacitor having a value equal to C/n to each infinitesimal tract of the transmission line, it is conceivable to add one capacitor every m infinitesimal tracts, as in a fourth circuit 40 shown in FIG. 4a. Based on the above description, the value of the capacitor to be added to the fourth circuit 40 will have to be equal to C.Math.(m/n).

(31) The fourth circuit 40 of FIG. 4a is equivalent to a fifth circuit 50 of FIG. 4b that comprises a transmission line TL.sub.1 and a capacitor 52 having a value C.Math.(m/n). Having analyzed infinitesimal tracts and defined C′ as the capacity per length unit of the transmission line TL1 of the fifth circuit 50, the following relationship applies:
C=∫.sub.0.sup.lC′ dl  (10)

(32) where l represents the physical length of the transmission line TL1 of the fifth circuit 50.

(33) If C′ is a constant value, C=C′l, which, as previously stated, equals C.Math.m because m infinitesimal tracts have been considered.

(34) The fifth circuit 50 of FIG. 4b is essentially a low-pass filtering element having a cut-off frequency f.sub.c that can be obtained by means of the following empirical formula (assuming that the impedance of TL1 is Z.sub.0, i.e., the characteristic impedance of the transmission line):

(35) $\begin{array}{cc}{f}_c=\frac{1}{\pi Z_0\frac{C_{TOT}}{n}}=\frac{1}{\pi Z_0\frac{C^{\prime }.Math.l_{\max }}{n}}& \left(11\right)\end{array}$

(36) where C.sub.TOT depends on the length of the transmission line TL.sub.1 and amounts to C′.Math.l.sub.max.

(37) Referring back to the Doherty amplifier 10 of FIG. 1, it operates within a certain frequency range, or passband, defined between a minimum frequency f.sub.min and a maximum frequency f.sub.max. As the length of the line grows, the value C.sub.TOT increases, and hence f.sub.c decreases.

(38) With a view to avoiding any malfunctions of the amplifier 10, it is necessary to impose that the cut-off frequency f.sub.c is outside the passband. The maximum operating frequency being known, this will limit the line length to the value l.sub.max that can be obtained from the equation (11).

(39) In fact, the equation (11) can be solved with respect to l.sub.max because: the value n is defined by the designer; the cut-off frequency f.sub.c is imposed by the designer; the characteristic impedance Z.sub.0 of the transmission line TL1 can be determined by means of suitable simulation software; the capacity C′ per length unit of the transmission line TL1 can be determined by means of suitable simulation software or convenient tables.

(40) The value l.sub.max corresponds, therefore, to the maximum distance at which two successive capacitors can be arranged in order to obtain a cut-off frequency higher than the upper end of the passband of the amplifier 10.

(41) Indicating a step length as l.sub.STEP, and given the total length l.sub.TOT of the transmission line, a number of steps n.sub.passi can be obtained as l.sub.TOT/l.sub.STEP, where l.sub.STEP≤l.sub.max.

(42) The capacitor to be added at each step length will thus have a value equal to C.sub.TOT/(n.Math.n.sub.passi).

(43) In this way, a physical length of the matching line is obtained which is shorter than in the prior art, so that the plan width of the wideband Doherty amplifier can be reduced. In fact, it is possible to reduce the physical length of the delay line 7 and/or of the first offset line 13′ and/or of the second offset line 13 and/or of the transformation line 14.

(44) The impedance mismatching which is found at the recombination node 9 of the circuit of FIG. 1a or FIG. 1b can thus be advantageously compensated for by appropriately sizing the delay line 7 and/or the first offset line 13′ and/or the second offset line 13 and/or the transformation line 14.

(45) A generic representation of a transmission line (which in the circuits of FIGS. 1a or 1b may be the delay line 7 and/or the first offset line 13′ and/or the second offset line 13 and/or the transformation line 14) modified by inserting some capacitors in accordance with the method of the present invention is illustrated in the circuit 60 of FIG. 4c, where N is the number of capacitors inserted between line tracts TL1, TL2 and TL3, and C.sub.TOT is the total capacity of the circuit 60.

(46) C.sub.TOT includes both the parasitic capacities which are peculiar to the semiconductor and the capacities inserted in accordance with the method of the present invention.

(47) The value and the number of the inserted capacitors should be chosen by the designer on the basis of the operating frequency of the wideband Doherty amplifier, of the extent to which the physical dimensions of the line need to be reduced, and of the physical complexity introduced in the circuit by the capacitors.

(48) Preferably, the capacitors should be distributed at a regular mutual distance along the transmission line, so as to ensure symmetry and approximate at best the above-described electric behaviours.

(49) Nevertheless, the capacitors may also be inserted empirically at irregular mutual distances, should any mounting problems or difficulties make it necessary to choose a different arrangement, while still fulfilling the constraint L.sub.STEP≤l.sub.max.

(50) Likewise, if a given value of one or each unitary capacitor to be added to the circuit results in an operating frequency close to the resonance frequency of that particular capacitor, it will be possible to divide such capacitor into multiple capacitors equivalent to the unitary capacitor, to be positioned at a suitable distance in compliance with the above-described conditions.

(51) With reference to FIG. 5, the following will describe a method 100 which can be used by a designer in order to make a wideband Doherty amplifier having a reduced plan width in comparison with the prior art.

(52) At step 110, a factor n is selected which is representative of the reduction in the physical length of the delay line 7 and/or of the first offset line 13′ and/or of the second offset line 13 and/or of the transformation line 14 to detriment of the impedance matching of the line itself. In practice, having available the graph of FIG. 3, the designer selects a value of n by taking into account the maximum tolerable mismatching indicated by the Return Loss variable RL in the graph of FIG. 3.

(53) At step 120, a value is determined for the capacitor C that should be inserted at each step length L.sub.STEP, which will be defined by the designer at the next step 160, of the transmission line.

(54) At step 130, a cut-off frequency f.sub.c is imposed, which must be positioned outside the passband of the amplifier, i.e., having a value which is higher than the maximum operating frequency f.sub.max of the amplifier, wherein f.sub.max is a design specification.

(55) At step 150, by means of the equation (11) the value l.sub.max is obtained, which is the maximum step length at which it is possible to position two successive capacitors for the cut-off frequency f.sub.c to be higher than the maximum operating frequency f.sub.max of the amplifier.

(56) At step 160, the minimum number of steps n.sub.passi=l.sub.TOT/l.sub.STEP is obtained at which a capacitor must be inserted in the transmission line, where l.sub.STEP≤l.sub.max and l.sub.TOT is the length of the delay line 7 and/or of the first offset line 13′ and/or of the second offset line 13 and/or of the transformation line 14.

(57) At step 170, a capacitor having the value C.sub.TOT/(n.Math.n.sub.passi) is added at every step length L.sub.STEP.

(58) Since the delay line 7, the first offset line 13′, the second offset line 13 and the transformation line 14 are made by using suitably shaped and sized tracks applied to an insulating substrate in accordance with the known printed circuit technique, in order to implement the method of the present invention it is necessary to insert or add one or more capacitors on a track associated with the line the physical length of which is to be reduced. For example, this is practically achieved by soldering the capacitors onto the track.

(59) The method according to the present invention is therefore applicable to one or more of the transmission lines of the output network 15,15′ of the Doherty amplifier, i.e., to the delay line 7, the transformation line 14, the first offset line 13′ and the second offset line 13.

(60) The method for making a wideband Doherty amplifier with reduced plan width and such amplifier described herein by way of example may be subject to many possible variations without departing from the novelty spirit of the inventive idea; it is also clear that in the practical implementation of the invention the illustrated details may have different shapes or be replaced with other technically equivalent elements.

(61) It can therefore be easily understood that the present invention is not limited to a method for making a wideband Doherty amplifier and to such wideband Doherty amplifier with reduced plan width described herein by way of example, but may be subject to many modifications, improvements or replacements of equivalent parts and elements without departing from the inventive idea, as clearly specified in the following claims.