PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE

Abstract

According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.

Claims

1. A preparation method for a semiconductor structure, comprising: sequentially preparing a channel layer, a barrier layer, and a p-type semiconductor layer on a substrate; preparing a dielectric layer in a gate region above the p-type semiconductor layer; preparing an n-type semiconductor layer in a region other than the gate region above the p-type semiconductor layer; and activating a p-type impurity in the p-type semiconductor layer covered by the dielectric layer, to form an active region.

2. The preparation method for a semiconductor structure according to claim 1, further comprising: removing the dielectric layer, and preparing a gate above the active region of the p-type semiconductor layer.

3. The preparation method for a semiconductor structure according to claim 2, wherein the dielectric layer is removed by a wet etching method.

4. The preparation method for a semiconductor structure according to claim 1, further comprising: preparing a source and a drain respectively in a source region and a drain region, wherein the source and the drain penetrate the n-type semiconductor layer and the p-type semiconductor layer.

5. The preparation method for a semiconductor structure according to claim 1, wherein the preparing a source and a drain respectively in a source region and a drain region comprises: forming a groove by etching on two sides of a gate, wherein the groove penetrates through the n-type semiconductor layer and the p-type semiconductor layer, and stops at the barrier layer; and depositing metal in the groove to prepare the source and the drain.

6. The preparation method for a semiconductor structure according to claim 5, wherein an etching method of the groove is a dry etching method.

7. The preparation method for a semiconductor structure according to claim 1, wherein a method of forming the active region comprises annealing a semiconductor structure.

8. The preparation method for a semiconductor structure according to claim 7, wherein the annealing comprises performing annealing in a hydrogen-free environment.

9. The preparation method for a semiconductor structure according to claim 1, wherein the dielectric layer comprises at least one of SiO.sub.2 and Al.sub.2O.sub.3.

10. The preparation method for a semiconductor structure according to claim 1, wherein the p-type semiconductor layer and the n-type semiconductor layer comprise a GaN-based semiconductor.

11. The preparation method for a semiconductor structure according to claim 1, wherein before preparing the channel layer, the preparation method further comprises: sequentially forming a nucleation layer and a buffer layer on the substrate.

12. The preparation method for a semiconductor structure according to claim 11, wherein the nucleation layer comprises one or more of AN, AlGaN, and GaN.

13. The preparation method for a semiconductor structure according to claim 11, wherein the buffer layer comprises one or more of GaN, AlGaN, and AlInGaN.

14. The preparation method for a semiconductor structure according to claim 1, wherein the channel layer, the barrier layer and the p-type semiconductor layer are grown in situ, or be grown by Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Metal-Organic Chemical Vapor Deposition (MOCVD), or a combination thereof.

15. The preparation method for a semiconductor structure according to claim 1, wherein the preparing a dielectric layer in a gate region above the p-type semiconductor layer comprises: forming a dielectric layer on the p-type semiconductor layer; and etching the dielectric layer in a region other than the gate region above the p-type semiconductor layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1a-1b and FIG. 2-6 are respectively schematic exploded diagrams of a semiconductor structure in a preparing process according to an embodiment of the present application.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following describes the present application in detail with reference to specific implementations corresponding to the accompanying drawings. However, the present application is not limited to these implementations, and the structural, method, or functional changes made by those of ordinary skill in the art according to these implementations are all included in the protection scope of the present application.

[0017] In addition, repeated reference signs or marks may be used in different embodiments. These repetitions are only to briefly and clearly describe the present application, and do not represent any relevance between different embodiments and/or structures discussed.

[0018] An embodiment of the present application provides a preparation method for a semiconductor structure, including the following specific steps.

[0019] Step 1: as shown in FIG. 1a, sequentially preparing a channel layer 21, a barrier layer 22, and a p-type semiconductor layer 23 on a substrate 1.

[0020] The substrate 1 preferably includes sapphire, diamond, silicon carbide, silicon, lithium niobate, silicon on insulator (SOI), gallium nitride, or aluminum nitride.

[0021] The channel layer 21 and the barrier layer 22 may include a semiconductor material that can form a two-dimensional electron gas. The channel layer 21 and the barrier layer 22 may include, for example, a GaN-based material. The GaN-based material is a compound including at least a Ga atom and an N atom. For example, the channel layer 21 may include GaN, and the barrier layer 22 may include AlGaN. The channel layer 21 and the barrier layer 22 constitute a heterostructure, to form a two-dimensional electron gas.

[0022] The p-type semiconductor layer 23 includes a GaN-based material, for example, doping GaN with a p-type impurity, for example, Mg.

[0023] In an embodiment of the present application, as shown in FIG. 1b, before the channel layer 21 is grown, a nucleation layer 31 and a buffer layer 32 may also be grown sequentially on the substrate 1. Taking a GaN-based semiconductor structure as an example, the nucleation layer 31 may reduce dislocation density and defect density, improving crystal quality. The nucleation layer 31 may include one or more of AN, AlGaN, and GaN. The buffer layer 32 may buffer stress in an epitaxial structure above the substrate, preventing the epitaxial structure from cracking. The buffer layer 32 may include one or more of GaN, AlGaN, and AlInGaN.

[0024] The channel layer 21, the barrier layer 22, and the p-type semiconductor layer 23 may be grown in situ, or may be grown by Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Metal-Organic Chemical Vapor Deposition (MOCVD), or a combination thereof. It should be understood that, for the formation of the channel layer 21 and the barrier layer 22 described herein, the channel layer, the barrier layer and the semiconductor layer may be formed by any method known to those skilled in the art in the present application.

[0025] Step 2: as shown in FIG. 2, preparing a dielectric layer 24 in a gate region above the p-type semiconductor layer 23.

[0026] A dielectric layer is formed on the p-type semiconductor layer 23, and the dielectric layer in a region other than the gate region above the p-type semiconductor layer 23 is etched, so that the dielectric layer 24 is formed only in the gate region above the p-type semiconductor layer 23. The dielectric layer 24 covers the p-type semiconductor layer 23 under the gate region.

[0027] Step 3: as shown in FIG. 3, preparing an n-type semiconductor layer 25 in a region other than the gate region above the p-type semiconductor layer 23.

[0028] The n-type semiconductor layer 25 is selectively grown. The n-type semiconductor layer 25 is formed only in the region other than the gate region above the p-type semiconductor layer 23, and the n-type semiconductor layer 25 covers the p-type semiconductor layer 23 that is in the region other than the gate region.

[0029] Further, the n-type semiconductor layer includes an n-type GaN-based semiconductor layer, for example, an n-type impurity is doped in GaN to form n-GaN.

[0030] Step 4: as shown in FIG. 4, activating a p-type impurity in the p-type semiconductor layer covered by the dielectric layer 24, to form an active region 231.

[0031] In this embodiment, the epitaxial structure may be annealed to form an active region. The annealing includes performing annealing in a hydrogen-free environment. The p-type impurity in the p-type semiconductor layer 23 covered by the dielectric layer 24 is selectively activated to form the active region 231. For the p-type semiconductor layer 23 covered by the n-type semiconductor layer 25, due to blocking of the n-type semiconductor layer 25, H atoms cannot overflow, and the p-type impurity in the p-type semiconductor layer cannot be activated, forming an inactive region 232. It may be understood that a size of the active region 231 may be larger than that of the dielectric layer 24 covering the p-type semiconductor layer 23, may be less than that of the dielectric layer 24 covering the p-type semiconductor layer 23, or may be equal to that of the dielectric layer 24 covering the p-type semiconductor layer 23. A size of the active region 231 is not limited in the present application.

[0032] In this embodiment, a specific method for forming the active region 231 is that in a hydrogen-free annealing environment, the hydrogen component in the p-type semiconductor layer 23 overflows through the dielectric layer 24 to activate the p-type impurity in the p-type semiconductor layer 23. For the p-type semiconductor layer 23 covered by the n-type semiconductor layer 25, due to blocking of the n-type semiconductor layer 25, H atoms cannot overflow in the annealing environment but bond with the p-type impurity (such as Mg—H) in the p-type semiconductor layer, and the p-type impurity in the p-type semiconductor layer cannot be activated, forming the inactive region 232.

[0033] A material type of the dielectric layer is not specifically limited in the present application. The material type of the dielectric layer 24 only needs to meet the following requirements: in a process of activating the p-type impurity in the p-type semiconductor layer, overflow of H atoms is ensured. Specifically, after the active region 231 is formed, H content in the dielectric layer 24 may be, for example, not more than 10%. The dielectric layer may include, for example, at least one of SiO.sub.2 and Al.sub.2O.sub.3.

[0034] Step 5: as shown in FIG. 5, removing the dielectric layer 24, and preparing a gate 43 above the active region 231 of the p-type semiconductor layer 23.

[0035] The dielectric layer 24 may be removed by a wet etching method, and a gate material is deposited on a position where the dielectric layer 24 is removed, that is, above the active region 231, to form the gate 43.

[0036] Further, the preparation method for a semiconductor structure further includes Step 6: as shown in FIG. 6, preparing a source 41 and a drain 42 respectively in a source region and a drain region, the source 41 and the drain 42 penetrate the n-type semiconductor layer and the p-type semiconductor layer.

[0037] Specifically, a groove can be formed by etching on two sides of the gate. The groove penetrates through the n-type semiconductor layer 25 and the inactive region 232 of the p-type semiconductor layer 23 and stops at the barrier layer 22. Metal is deposited in the groove to prepare the source and the drain, to form an ohmic contact.

[0038] Further, an etching method of the groove may be a dry etching method.

[0039] It may be understood that a sequence of Step 5 and Step 6 may be exchanged, that is, a sequence of preparation of the source, the gate, and the drain is not limited, as long as the gate, the source and the drain are formed on the epitaxial structure.

[0040] According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.

[0041] It should be understood that although this specification is described in accordance with the implementations, each implementation includes not only one independent technical solution. The description in the specification is only for clarity, and those skilled in the art should regard the specification as a whole. The technical solutions in the embodiments can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

[0042] The series of detailed descriptions listed above are only specific descriptions of the feasible implementations of the present application. They are not used to limit the protection scope of the present application. Any equivalent implementation or change made without departing from the technical spirit of the present application shall fall within the protection scope of the present application.