Systems and methods for voltage conversion implementing a switched-capacitor circuit

Abstract

A voltage conversion system including a source configured to supply a voltage and a switch capacitor circuit electrically coupled to the source. The switch capacitor circuit is configured to switch between a discharging state and a charging state. The switching between the discharging state and the charging state produces a boost to the supplied voltage. The voltage conversion system includes a capacitor in the switch capacitor circuit configured to store charge during the charging state and drain charge during the discharging state. The voltage conversion system includes a switching arrangement having a plurality of switch pairs configured to supply a converted voltage to a load. The switch capacitor circuit and the switching arrangement are interfaced to produce a unified circuit.

Claims

1. A voltage conversion system, comprising: a switched capacitor circuit; a voltage source configured to supply voltage to the switched capacitor circuit; and an inverter electrically coupled between the switched capacitor circuit and a load; wherein the switched capacitor circuit includes: a pair of switches electrically coupled across the voltage source and arrange in series with each other; a third switch electrically coupled between a terminal of the voltage source and the inverter; and a capacitor electrically coupled between a first node and a second node, where the first node is disposed between the third switch and the inverter and the second node is disposed between the pair of switches.

2. The voltage conversion system of claim 1 wherein the switched capacitor circuit is configured to charge the capacitor with voltage from the voltage source during a charging state and discharge voltage from the capacitor during a discharging state.

3. The voltage conversion system of claim 1 wherein the load is a motor in a vehicle.

4. The voltage conversion system of claim 2 wherein the switched capacitor circuit is configured to place the capacitor is parallel with the load during the charging state and place the capacitor is series with the load during the discharging state.

5. The voltage conversion system of claim 4 wherein the pair of switches is comprised of a first switch electrically coupled to a high side of the voltage source and a second switch electrically coupled electrically coupled to a low side of the voltage source, such that the first switch is open and the second switch is closed during the charging state, and the first switch is closed and the second switch is open during the discharging state.

6. The voltage conversion system of claim 5 wherein the first switch, the second switch and the third switch are further defined as metal oxide semiconductor field effect transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure will become more fully understood from the detailed description and the accompanying drawings.

(2) FIG. 1 is an example circuit topology of conventional inverter-converter topology in the prior art.

(3) FIG. 2 is an example circuit topology of a switch capacitor converter according to the principles of the present disclosure.

(4) FIG. 3 is an example circuit topology of the switch capacitor converter of FIG. 2 in a charging state.

(5) FIG. 4 is an example circuit topology of the switch capacitor converter of FIG. 2 in a discharging state.

(6) FIG. 5A is an example space vector hexagon.

(7) FIG. 5B is an example of reference vector synthesis in sector I of the space vector hexagon of FIG. 5A.

(8) FIG. 6 is a graph depicting the relationship between a maximum voltage and a power factor angle of an example circuit.

(9) FIGS. 7A-7D are graphs depicting a charging time with respect to a minimum charging time with varying boost factor (A) and modulation index (M.sub.i).

(10) FIG. 8 is an example implementation of a carrier-based modulation with variable duty ratio of a switch capacitor converter according to the principles of the present disclosure.

(11) FIG. 9 is an example implementation of a carrier-based modulation with fixed duty ratio of a switch capacitor converter according to the principles of the present disclosure.

(12) FIGS. 10-17 are alternative example circuit topologies of a switch capacitor converter.

(13) In the drawings, reference numbers may be reused to identify similar and/or identical elements.

DETAILED DESCRIPTION

(14) An improved switch capacitor (SC) voltage boost converter and control method for implementing a DC-AC power conversion is presented. The SC buck-boost voltage source converter includes a power source, a main circuit, and a SC circuit. The SC converter is bidirectional and can operate as a DC-AC inverter or an AC-DC rectifier. The SC converter is configured such that the SC converter can buck and boost the voltage.

(15) The SC converter employs an SC circuit augmented with the main converter circuit electrically coupled to the power source, such as a battery, thus providing unique features that cannot be attained by a traditional voltage-source inverter (VSI) or boost VSI. The additional features include doubling the area of the linear modulation region. The SC converter eliminates the need for a large inductor in the boost DC-DC stage and a large filtering capacitor, leading to a higher energy density and lower cost.

(16) Additionally, conventional SC techniques are limited to low power applications, such as less than 100 W, because a high current in the charging stage may destroy the switches. That is, a voltage drop occurs when draining a capacitor during a discharging state, resulting in a very high current being produced to charge the capacitor during a following charging state. However, as shown in the SC converter of the present disclosure, the SC circuit is designed to limit a charging current, allowing for a variety of high-power applications, such as in the 10 kW to 20 kW range.

(17) Referring again to FIG. 1, an example circuit topology of conventional inverter-converter 100 topology in the prior art is shown. The conventional inverter-converter 100 provides voltage to a motor 104. The conventional inverter-converter 100 includes a boost DC-DC converter stage 108 and an inverter stage 112. The boost DC-DC converter stage 108 includes an inductor 116 and a capacitor 120 and a pair of switches. The capacitor is connected in parallel the pair of switches, such as a first switch 124 and a second switch 128, as well as pairs of switches in the inverter stage 112.

(18) Referring now to FIG. 2, an example circuit topology of a SC converter 200 according to the principles of the present disclosure is shown. The SC converter 200 concept can be applied to all DC-AC, AC-DC, AC-AC, and DC-DC power conversion. In example implementations, FIG. 2 depicts the SC converter 200 topology for DC-AC power conversion for machine drive—for example, driving a motor 204.

(19) The SC converter 200 employs a SC circuit 208 with an inverter 212 or switching arrangement to form a unified circuit. The SC circuit 208 is used to create a discrete value of the voltage. Therefore, the proposed SC circuit 208 differs from the conventional one by not having the reverse blocking diode at the load side and a large filtering capacitor. Additionally, the SC circuit 208 removes the inductor 116 of FIG. 1 and instead utilizes a switch capacitor technique. Eliminating the inductor reduces the overall weight of the SC circuit 208, resulting in the ability to obtain a higher power density. Additionally, a higher level of voltage can be obtained when using multiple switch capacitor circuits. The SC circuit 208 design is controlled by limiting the charging current, for example, by adjusting a size of the SCs, adjusting a switching frequency, and including limiting resistors in the capacitor charging path.

(20) In FIG. 2, a new SC 216 is included and a capacitor 220 is connected to an end of the new SC 216 and now between the first switch 124 and the second switch 128. A source 224 supplies voltage to the SC circuit 208. The SC circuit 208 can have two possible states: a discharging state and a charging state. FIG. 3 depicts a first state when a capacitor 304 is charging. When charging, the capacitor 304 is in a parallel configuration with a load 308. FIG. 4 depicts a second state when the capacitor 304 is discharging. When discharging, the capacitor 304 is in a series configuration with the load 308. Switching between the first state and the second state can provide two times the voltage to the load 308.

(21) With respect to FIG. 3, the voltage of the battery, V.sub.bat, can be expressed as follows in Equation 1:
V.sub.bat=v.sub.cap=v.sub.i  (1)
The current, i.sub.i, through the load 308 in FIG. 3, such as a motor of a hybrid vehicle, can be expressed as follows in Equation 2:
i.sub.i=S.sub.ai.sub.a+S.sub.bi.sub.b+S.sub.ci.sub.c  (2)
With respect to FIG. 4, the voltage of the battery, V.sub.bat, can be expressed as follows in Equation 3:
V.sub.bat=v.sub.cap; v.sub.i=2V.sub.bat  (3)
The current, i.sub.i, through the load 308 in FIG. 4, such as a motor of a hybrid vehicle, can be expressed as follows in Equation 4:
i.sub.i=S.sub.ai.sub.a+S.sub.bi.sub.b+S.sub.ci.sub.c  (4)

(22) In addition to these options, the other phase legs still feature the eight known inverter states. The overall feasible states in the SC converter 200 are fourteen. FIG. 5A depicts the fourteen states in a space vector hexagon 500. Notably, the states of the SC converter resemble a three-level inverter with phase voltage possibilities {0; V.sub.bat; 2V.sub.bat}. FIG. 5B is an example of reference vector synthesis in sector I of the space vector hexagon of FIG. 5A.

(23) To derive a dwell time from each vector, a few assumption are made. For example, in each sector, the four adjacent active vectors and the zero vectors are used to synthesis the reference voltage vector. During the discharge state (FIG. 3), the capacitor voltage is assumed constant and equal to the battery voltage. Therefore, the dwell time during the discharge state needs to be minimized to allow for a minimum voltage drop during the capacitor discharge.

(24) Assume that the reference voltage vector V.sub.ref can be synthesis using the following virtual vectors:
V.sub.refT.sub.s=V.sub.xt.sub.x+V.sub.yt.sub.y+V.sub.0t.sub.0  (5)
where,
V.sub.xt.sub.x=V.sub.11t.sub.11+V.sub.12t.sub.12  (6)
V.sub.yt.sub.y=V.sub.21t.sub.21+V.sub.22t.sub.22  (7)

(25) With some algebraic manipulation, the dwell time for the four active vectors is depicted in the following equations:
t.sub.11=(1−A)t.sub.x  (8)
t.sub.12=At.sub.x  (9)
where,

(26) $\begin{array}{cc}{t}_x=\sqrt{3}{T}_s*M_i*\sin \left(\frac{\pi }{3}-\theta \right)& \left(10\right)\\ \mathrm{and}& \\ A=\{\begin{array}{cc}0,& 0\le M_i\le \frac{1}{\sqrt{3}}\\ \sqrt{3}{M}_i-1,& \frac{1}{\sqrt{3}}<M_i\le \frac{2}{\sqrt{3}}\end{array}& \left(11\right)\\ t_{21}=\left(1-A\right)t_y& \left(12\right)\\ t_{22}=A{t}_y& \left(13\right)\end{array}$
where,
t.sub.y=√{square root over (3)}T.sub.s*M.sub.i*sin(θ)  (14)
Further, the modulation index (M.sub.i) is defined as follows: M.sub.i=|V.sub.ref|/V.sub.bat. The factor A∈[0,1] is the boost factor.

(27) Therefore, when

(28) $0\le M_i\le \frac{1}{\sqrt{3}},t_{11}=t_x$
and t.sub.12=0, t.sub.21=t.sub.y and t.sub.22=0. The capacitor is maintained in parallel with the DC source and no discharge occurs during anytime. The SC converter operation in this case is typical to the operation of a two-level inverter, which is referred to as (Abstemious Mode). On the other hand, when

(29) $\frac{1}{\sqrt{3}}<M_i\le \frac{2}{\sqrt{3}},0<A\le 1,$
and the capacitor is charged and discharged with a rate proportional to the value of A, the operation mode is referred to as (Gluttonous Mode). When

(30) $M_i=\frac{2}{\sqrt{3}},t_{11}=0,t_{12}=t_y,t_{21}=0,$
and t.sub.22=t.sub.y. In this case, the capacitors are only charging during zero vector implementation. Therefore, the six step operation cannot be performed in the gluttonous mode and the minimum vector requirement must be met to maintain the capacitor charge level.

(31) As mentioned above, to prevent the SC switches from being destroyed, the SC circuit 208 is analyzed and designed according to certain current limitations. That is, since switch capacitors are routinely used in low voltage applications, using switch capacitors in the presently claimed invention presents a unique challenge of preventing the destruction of circuit components, such as the SCs, due to a high current travelling through the SC circuit 208 in a charging state (FIG. 3) after the capacitor has been discharged, resulting in a voltage drop, during the discharging state (FIG. 4).

(32) In a pre-discharge state shown in FIG. 3, the capacitor 304 is charged with voltage equal to:
V.sub.cap=V.sub.bat−(V.sub.D+V.sub.p)=V.sub.dc  (15)
where V.sub.D is the forward voltage drop across a diode 312 and, for simplification, V.sub.p refers to the summation of the parasitic voltages drop along the charging path, including the voltage drop across the series resistance of the capacitor 304 and the series resistance of the switch.

(33) Then, the capacitor 304 is discharged to the load 308 as shown in FIG. 4. During this time the capacitor 304 is connected in series with the source 224 and the load 308; therefore:
i.sub.i=i.sub.s=i.sub.cap=S.sub.ai.sub.a+S.sub.bi.sub.b+S.sub.ci.sub.c  (16)

(34) To estimate the charging current of the capacitor, the sequence in which the capacitor is charged and discharged with respect to the inverter states is considered. In an example where the capacitor is discharged in two separate intervals per sampling time T.sub.s, the first interval may produce V.sub.12 and V.sub.22 and the second interval produces V.sub.22 and V.sub.12. First, assume that Equation 15 holds, and therefore, before every discharge state, v.sub.cap1=V.sub.dc. The capacitor voltage at point 2 v.sub.cap2 can be predicted as follows:

(35) $\begin{array}{cc}{v}_{\mathrm{cap}2}=V_{dc}-\frac{i_a{t}_{12}}{2C}& \left(17\right)\end{array}$

(36) Similarly, the capacitor voltage at point 3 v.sub.cap3 can be expressed as:

(37) $\begin{array}{cc}{v}_{cap3}=V_{dc}-\frac{i_{a}A{t}_x}{2C}+\frac{i_{c}A{t}_y}{2C}& \left(18\right)\end{array}$

(38) Note that:

(39) $\begin{array}{cc}{i}_a=I_a\cos \left(\theta -\varphi \right)& \left(19\right)\\ i_b=I_b\cos \left(\theta -\varphi +\frac{2\pi }{3}\right)i_c=I_c\cos \left(\theta -\varphi -\frac{2\pi }{3}\right)& \end{array}$
where i.sub.a, i.sub.b, and i.sub.c are phase shifted from the reference voltage by ϕ, which is the power factor angle. I.sub.a=I.sub.b=I.sub.c=I are the phase currents amplitudes. Note that t.sub.x and t.sub.y are functions of the modulation index M.sub.i and the angle θ as expressed in Equations 10 and 14, respectively.

(40) For any assigned value of the modulation index, the capacitor voltage drop in the first discharge interval would be expressed as:

(41) $\begin{array}{cc}\Delta V=V_{dc}-v_{cap3}=\frac{A}{2C}\left(t_x{i}_a-t_y{i}_c\right)& \left(20\right)\end{array}$

(42) and the maximum value of ΔV (ΔV.sub.max) can be obtained be taking the gradient of Equation 20 with respect to θ,

(43) $\begin{array}{cc}\frac{\partial \Delta V}{\partial \theta }=\frac{\sqrt{3}{M}_i{T}_{s}I}{C}\left(\cos \left(2\theta -\varphi -\frac{\pi }{3}\right)+\cos \left(2\theta -\varphi -\frac{2\pi }{3}\right)\right)& \left(21\right)\end{array}$

(44) Note that there exists an angle

(45) 0$\hat{\theta }\in \left\{0,\frac{\pi }{3}\right\}$
that causes maximum ΔV and makes the gradient equal zero:

(46) $\begin{array}{cc}\frac{\partial \Delta V}{\partial \theta }=0=\left(\cos \left(2\hat{\theta }-\varphi -\frac{\pi }{3}\right)+\cos \left(2\hat{\theta }-\varphi -\frac{2\pi }{3}\right)\right)& \left(22\right)\end{array}$

(47) By using the following identity:
cos(x−y)+cos(x+y)=1 cos(x)cos(y)  (23)

(48) Equation 22 can be expressed as:

(49) $\begin{array}{cc}\cos \left(2\hat{\theta }-\varphi -\frac{\pi }{2}+\frac{\pi }{6}\right)+\cos \left(2\hat{\theta }-\varphi -\frac{\pi }{2}-\frac{\pi }{6}\right)=2\cos \left(2\hat{\theta }-\varphi -\frac{\pi }{2}\right)\cos \left(\frac{\pi }{6}\right)& \left(24\right)\end{array}$

(50) Obviously,

(51) $\begin{array}{cc}\cos \left(\frac{\pi }{6}\right)\ne 0;& \end{array}$
therefore,

(52) $\cos \left(2\theta -\varphi -\frac{\pi }{2}\right)=0,$
leading to the following conditions:

(53) $\begin{array}{cc}2\hat{\theta }-\varphi -\frac{\pi }{2}=\frac{\pi }{2}2\hat{\theta }-\varphi -\frac{\pi }{2}=-\frac{\pi }{2}& \left(25\right)\end{array}$

(54) and θ that causes maximum ΔV is one of the two solutions:

(55) $\begin{array}{cc}\hat{\theta }=\{\begin{array}{cc}\frac{\pi +\varphi }{2},& 0>\varphi \ge -\frac{\pi }{2}\\ \frac{\varphi }{2},& 0\le \varphi \le \frac{\pi }{2}\end{array}& \left(26\right)\end{array}$

(56) The formulation of the angle {circumflex over (θ)} gives the insight that for any power factor PF from 0 to 1, the angle that causes maximum ΔV always lies between 0 degrees and 45 degrees of sector I. The maximum voltage drop can be expressed as:

(57) $\begin{array}{cc}\Delta V{|}_{\theta =\frac{\varphi }{2}}=\Delta V_{\max }=\frac{A}{2C}\left(t_x{i}_a-t_y{i}_c\right)=\frac{A}{2C}\sqrt{3}{M}_i{T}_{s}I\left[\sin \left(\frac{\pi }{3}-\frac{\varphi }{2}\right)\cos \left(\frac{\varphi }{2}\right)-\sin \left(\frac{\varphi }{2}\right)\cos \left(\frac{\varphi }{2}-\varphi -\frac{2\pi }{3}\right)\right]& \left(27\right)\end{array}$

(58) So far it has been shown that the maximum voltage drop location within the sector is solely dependent on the power factor PF of the load. Referring to FIG. 6, a graph depicting the relationship between ΔV.sub.max and a power factor angle of an example circuit is shown. However, as can be gathered from FIG. 6, the power factor PF does not affect the value of the maximum voltage drop ΔV.sub.max and all of the terms that include ϕ in Equation 27 are equal to

(59) $\frac{\sqrt{3}}{2}.$
Therefore:

(60) $\begin{array}{cc}\Delta V_{\max }=\frac{3A{M}_{i}I}{4C{f}_{sw}}& \left(28\right)\end{array}$

(61) To complete the analysis, the capacitor must reach ≈V.sub.dc voltage during the charging time. This can be understood by obtaining the minimum charging time location within the sector and its value dependency. The charging time t.sub.ch is a function of M.sub.i and A:

(62) 0$\begin{array}{cc}{t}_{ch}=\frac{t_0}{2}+\left(1-A\right)t_y=\frac{T_s}{2}-\sqrt{3}{T}_s{M}_i\left[\frac{1}{2}\sin \left(\frac{\pi }{3}-\theta \right)-\left(\frac{1}{2}-A\right)\sin \left(\theta \right)\right]& \left(29\right)\end{array}$

(63) Taking the gradient for Equation 29 and equating it to zero results in the angle {circumflex over ({circumflex over (θ)})} at which the minimum charging time is experienced t.sub.ch-min:

(64) $\begin{array}{cc}\frac{\partial t_{ch}}{\partial \theta }=0=\left(\cos \left(\frac{\pi }{3}-\stackrel{\widehat{^}}{\theta }\right)-\left(A-\frac{1}{2}\right)\cos \left(\stackrel{\widehat{^}}{\theta }\right)\right)& \left(30\right)\end{array}$

(65) The optimal angle is determined to be

(66) $\begin{array}{cc}\stackrel{\widehat{^}}{\theta }={\tan }^{-1}\left(\frac{4A-3}{\sqrt{3}}\right)& \left(31\right)\end{array}$

(67) Note that the angle {circumflex over ({circumflex over (θ)})} lies in sector I only when ¾≤A≤1. When 0≤A<¾, the resulting angle is negative, and it does not reside in sector I. However, a small segment of a sinusoidal function has a linear behavior. It is observed that {circumflex over ({circumflex over (θ)})}=0 when 0≤A<¾. Therefore, the general description for {circumflex over ({circumflex over (θ)})} is:

(68) $\begin{array}{cc}\stackrel{\widehat{^}}{\theta }=\{\begin{array}{cc}0,& 0\le A<\frac{3}{4}\\ {\tan }^{-1}\left(\frac{4A-3}{\sqrt{3}}\right),& \frac{3}{4}\le A\le 1\end{array}& \left(32\right)\end{array}$

(69) As a result, the minimum charging time t.sub.ch-min is expressed as follows:

(70) $\begin{array}{cc}{t}_{\mathrm{ch}-\min }\{\begin{array}{cc}\frac{1}{2}{T}_s\left(1-\frac{3}{2}{M}_i\right),& 0\le A<\frac{3}{4}\\ \left[\begin{array}{c}\frac{1}{2}\sin \left(\frac{\pi }{3}-{\tan }^{-1}\left(\frac{4A-3}{\sqrt{3}}\right)\right)-\\ \left(\frac{1}{2}-A\right)\sin \left({\tan }^{-1}\left(\frac{4A-3}{\sqrt{3}}\right)\right)\end{array}\right],& \frac{3}{4}\le A\le 1\end{array}& \left(33\right)\end{array}$

(71) Because of the symmetry of the sector, the other charging intervals have a similar expression for t.sub.ch-min. In order for the capacitor to retain the full voltage after each charging period, the following condition must be met:

(72) $\begin{array}{cc}{t}_{\mathrm{ch}-\min }\ge \mathrm{RC}\ln \left(\frac{V_{dc}-V_{cap}}{\frac{3}{4C}A{T}_s{M}_{i}I}\right)& \left(34\right)\end{array}$

(73) Under these conditions, the maximum charging current amplitude passing through the diode of S.sub.RR and the IGBT of {tilde over (S)}.sub.g can be estimated as:

(74) $\begin{array}{cc}{I}_{\mathrm{charging}-\max }=\frac{3A{M}_{i}I}{4RC{f}_{sw}}& \left(35\right)\end{array}$
where R is the resistance along the charging path including the on-resistance of the switches and the ESR of the switched-capacitor. The power losses resulting from the additional resistance must be very small and can be estimated as follow:

(75) $\begin{array}{cc}{P}_{R-\mathrm{losses}}=\frac{1}{R}{\left(\frac{3A{M}_{i}I}{4C{f}_{sw}}\right)}^2& \left(36\right)\end{array}$

(76) The presented guidelines allow better understanding of the charging current and how the selection of the switching frequency, the capacitor size, M.sub.i, and A will determine the current rating of the switched-capacitor half-bridge. Referring to FIGS. 7A-7D, graphs depicting a charging time with respect to a minimum charging time with varying boost factor (A) and modulation index (M.sub.i) are shown. In other words, FIGS. 7A-7D show the normalized charging time in different values of M.sub.i and A. Note that the expressions of ΔV.sub.max and t.sub.ch-min for the second t.sub.ch interval is the mirror image of the one shown in FIGS. 7A-7D.

(77) Referring now to FIG. 8, an example implementation of a carrier-based modulation 600 with variable duty ratio of a switch capacitor converter according to the principles of the present disclosure is shown. The simplified carrier-based modulation 600 has the flexibility to minimize the discharging time t.sub.dch without causing additional switching losses. That is, the generation of the switching function for the SC converter can be further simplified by adopting the carrier-based modulation 600 method. More specifically, the carrier-based modulation 600 can reduce the charging current by adjusting the SCs switching frequency. This can be done by creating a separate high frequency carrier for creating the switching function (S.sub.g), as shown in FIG. 8.

(78) The constant A represent the depth in the gluttonous mode. The range of A is from zero to one. When A=0, the SC converter of FIG. 2 is operating in the abstemious mode. When A=1, the SC converter is fully gluttonous, and the SC charge is only at the zero vector implementation, which is very small. Because of this, the SC converter cannot operate in the over-modulation region when

(79) $\mathrm{MI}\ge \frac{2}{\sqrt{3}}.$

(80) The carrier frequency of the SC leg is much larger than the carrier frequency of the three inverter legs. The larger frequency allow t.sub.dch to be distributed along the long period of the inverter leg carrier, which causes the reduction of the charging current and the switch losses in the inverter. Furthermore, this allows the use of a SiC switch for the high frequency SC circuit and maintains the use of a Si switch for the low frequency inverter circuit.

(81) FIG. 9 is another example implementation of a carrier-based modulation 700 with fixed duty ratio of a switch capacitor converter according to the principles of the present disclosure. In various implementations, the carrier-based modulation 700 having fixed duty ratio may be accomplished.

(82) Referring to FIGS. 10-17, alternative example circuit topologies of a SC converter are shown. While each circuit configuration depicted in FIGS. 10-17 include variations of an SC converter, each example embodiment depicts an SC converter operating similar to the SC converter described in the present disclosure.

(83) The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.