SIGNAL ANALYSIS METHOD AND SIGNAL ANALYSIS MODULE

Abstract

A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

Claims

1. A signal analysis method for analyzing a pulse modulated input signal, the signal analysis method comprising: receiving the pulse modulated input signal, the input signal comprising a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time, determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence, wherein a level difference between the at least two different levels is determined, and wherein the at least one decision threshold is determined based on the level difference.

2. The signal analysis method of claim 1, wherein the at least two different levels are associated with a maximum level of the symbol sequence and a minimum level of the symbol sequence, respectively.

3. The signal analysis method of claim 1, wherein at least one of an average over several levels of input signal samples being associated with a maximum level, and an average over several levels of input signal samples being associated with a minimum level is determined.

4. (canceled)

5. The signal analysis method of claim 1, wherein the at least one decision threshold A.sub.th is determined according to the equation A.sub.th,i=A.sub.max−(2k+1) p ΔA or according to the equation A.sub.th,i=A.sub.min+(2k+1) p ΔA, wherein A.sub.max corresponds to a maximum level of the input signal samples, wherein A.sub.min corresponds to a minimum level of the input signal samples, wherein k is an integer equal to or bigger than zero, wherein ΔA corresponds to the level difference, and wherein p is a proportionality factor.

6. The signal analysis method of claim 5, wherein the proportionality factor is determined based on an overall number of possible different levels of the symbol sequence.

7. The signal analysis method of claim 1, wherein the input signal is established as a pulse amplitude modulated (PAM)-N signal, wherein N is an integer bigger than 1.

8. The signal analysis method of claim 1, wherein the input signal is decoded based on the at least one decision threshold.

9. The signal analysis method of claim 8, wherein a level of the input signal is compared with the at least one decision threshold in order to decode the input signal.

10. The signal analysis method of claim 9, wherein the level of the input signal and the at least one decision threshold are compared at symbol times, the symbol times being defined by the clock signal.

11. A signal analysis apparatus for analyzing a pulse modulated input signal, the signal analysis apparatus comprising an input, a clock recovery circuit, and a signal decoder circuit, the input being configured to receive a pulse modulated input signal, the input signal comprising a symbol sequence, the clock recovery circuit being configured to recover a clock signal from the input signal, the clock signal being associated with the input signal, the signal decoder circuit being configured to sample the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time, the signal decoder circuit being configured to determine at least two different levels input signal samples being associated with different symbols of the symbol sequence, and the signal decoder circuit further being configured to determine at least one decision threshold based on the at least two different levels, the decision threshold being associated with a symbol transition of the symbol sequence, wherein the signal decoder circuit is configured to determine a level difference between the at least two different levels, and wherein the signal decoder circuit is configured to determine the at least one decision threshold based on the level difference.

12. The signal analysis apparatus of claim 11, wherein the at least two different levels are associated with at least one of a maximum level of the symbol sequence and a minimum level of the symbol sequence, respectively.

13. The signal analysis apparatus of claim 11, wherein the signal decoder circuit is configured to determine at least one of an average over several levels of input signal samples being associated with a maximum level, and an average over several levels of input signal samples being associated with a minimum level.

14. (canceled)

15. The signal analysis apparatus of claim 11, wherein the signal decoder circuit is configured to determine the at least one decision threshold according to the equation A.sub.th,i=A.sub.max−(2k+1) p ΔA or according to the equation A.sub.th,i=A.sub.min+(2k+1) p ΔA, wherein A.sub.max corresponds to a maximum level of the input signal samples, wherein A.sub.min corresponds to a minimum level of the input signal samples, wherein k is an integer equal to or bigger than zero, wherein ΔA corresponds to the level difference, and wherein p is a proportionality factor.

16. The signal analysis apparatus of claim 15, wherein the signal decoder circuit is configured to determine the proportionality factor based on an overall number of possible different levels of the symbol sequence.

17. The signal analysis apparatus of claim 11, wherein the input signal is established as a pulse amplitude modulated (PAM)-N signal, wherein N is an integer bigger than 1.

18. The signal analysis apparatus of claim 11, wherein the signal decoder circuit is configured to decode the input signal based on the at least one decision threshold.

19. The signal analysis apparatus of claim 18, wherein the signal decoder circuit is configured to compare the level of the input signal with the at least one decision threshold in order to decode the input signal.

20. The signal analysis apparatus of claim 19, wherein the signal decoder circuit is configured to compare the level of the input signal and the at least one decision threshold at symbol times, the symbol times being defined by the clock signal.

21. A signal analysis apparatus for analyzing a pulse modulated input signal, the signal analysis apparatus comprising an input, a clock recovery circuit, and a signal decoder circuit, the input being configured to receive a pulse modulated input signal, the input signal comprising a symbol sequence, the clock recovery circuit being configured to recover a clock signal from the input signal, the clock signal being associated with the input signal, the signal decoder circuit being configured to sample the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time, the signal decoder circuit being configured to determine at least two different levels input signal samples being associated with different symbols of the symbol sequence, and the signal decoder circuit further being configured to determine at least one decision threshold based on the at least two different levels, the decision threshold being associated with a symbol transition of the symbol sequence, wherein the signal decoder circuit is configured to determine at least one of an average over several levels of input signal samples being associated with a maximum level, and an average over several levels of input signal samples being associated with a minimum level.

Description

DESCRIPTION OF THE DRAWINGS

[0055] The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0056] FIG. 1 schematically shows a block diagram of a signal analysis module according to an embodiment of the present disclosure;

[0057] FIG. 2 shows a flow chart of a representative signal analysis method according to an embodiment of the present disclosure;

[0058] FIG. 3 shows a diagram of an input signal plotted against time; and

[0059] FIG. 4 shows a diagram illustrating several steps of the method of FIG. 2.

DETAILED DESCRIPTION

[0060] The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

[0061] FIG. 1 schematically shows a measurement device 10 comprising a signal analysis module 12. In various embodiments described herein, the term “module” is understood to describe suitable hardware, suitable software, or a combination of hardware and software that is configured to have a certain functionality. The hardware may, inter alia, comprise a CPU, a GPU, an FPGA, an ASIC, or other types of electronic circuitry.

[0062] In general, the measurement device 10 may be established as any type of measurement instrument being configured to analyze a pulse modulated signal. In some embodiments, the measurement device 10 may be established as an oscilloscope, as a signal analyzer, or as a vector network analyzer. Alternatively, the measurement device 10 may be established as a receiver being configured to decode a pulse modulated signal.

[0063] The signal analysis module 12 comprises an input 14, a clock recovery circuit or module 16, a signal decoder circuit or module 18, and a processing module 20 composed of, for example, one or more processor circuits. Generally speaking, the signal analysis module 12 is configured to analyze a pulse modulated input signal received via the input 14.

[0064] More precisely, the signal analysis module 12 is configured to perform a signal analysis method for analyzing a pulse modulated input signal that is described in the following with reference to FIG. 2.

[0065] A pulse modulated input signal is received via the input 14 (step S1).

[0066] The input signal may be generated by a device under test (if the measurement device 10 is established as a measurement instrument) or by any other signal source (e.g. if the measurement device 10 is established as a receiver).

[0067] In some embodiments, the input signal is established as a pulse amplitude modulated (PAM)-N signal, wherein N is an integer bigger than 1. For example, the input signal is established as a PAM-3 signal or as a PAM-4 signal. Alternatively, the input signal may be established as a non-return-to-zero (NRZ) signal, for example.

[0068] In some embodiments, the input signal may be established as a digital signal. If the input signal is established as an analog signal, the input signal may be digitized by an analog-to-digital converter, and the steps described in the following may be performed based on the digitized input signal.

[0069] A clock signal being associated with the input signal is recovered by the clock recovery module 16 (step S2). In general, the input signal is generated based on an internal clock signal of the signal source generating the input signal. However, according to many data transmission standards, the clock signal is not transmitted together with the generated input signal. Thus, the receiver (i.e. the measurement device 10) needs to recover this information by a so-called clock data recovery (CDR).

[0070] In step S2, any suitable clock recovery method known in the state of the art may be employed.

[0071] The input signal is sampled based on the clock signal recovered previously, thereby obtaining a set of input signal samples (step S3). Step S3 is illustrated in FIG. 3, which shows a diagram of an amplitude A of the input signal x.sub.in plotted against time t.

[0072] The input signal x.sub.in is sampled after the clock recovery such that each input signal sample of the set of input signal samples x.sub.sa is associated with exactly one symbol of the symbol sequence. Each of the input signal samples has a certain level, namely the signal amplitude of the input signal x.sub.in at the respective sample time. The level of each input signal sample is constant for the symbol duration T.sub.S of the respective symbol, wherein the symbol duration T.sub.S is defined by the clock signal. In other words, the duration of each input signal sample is equal to the clock period of the clock signal.

[0073] It is noted that while the input signal x.sub.S is illustrated as a continuous line in FIG. 3, the input signal x.sub.in may as well consist of samples. If the input signal x.sub.in is already digital or digitized, the input signal x.sub.in may be re-sampled in order to obtain the set of input signal samples x.sub.sa.

[0074] At least two different levels of at least two different input signal samples are determined, wherein the at least two different input samples are associated with at least two different symbols (step S4). Step S4 is illustrated in FIG. 4, which shows a diagram of an amplitude A of the set of input samples x.sub.sa obtained in step S3 plotted against time.

[0075] Without restriction of generality, the input signal corresponding to the set of input signal samples x.sub.sa in FIG. 4 is established as a PAM-3 coded signal. Accordingly, there are three possible symbol values for the individual symbols of the symbol sequence, which are denoted by “1”, “0” and “−1” in FIG. 4.

[0076] The at least two different levels are associated with a maximum level of the symbol sequence (i.e. level “1” in the case of FIG. 4) and a minimum level of the symbol sequence (i.e. level “−1” in the case of FIG. 4). In some embodiments, the highest level A.sub.max and the lowest level A.sub.min occurring in the set of input signal samples x.sub.sa may be determined.

[0077] While a highest level A.sub.max of the set of input signal samples x.sub.sa may not be exactly equal to the designated level “1” of the symbol sequence, it is nonetheless clear that the highest level of the input signal samples is associated with the symbol level “1”. Similarly, the lowest level A.sub.min of the input signal samples is associated with the symbol level “4”. Accordingly, the highest level A.sub.max and the lowest level A.sub.min constitute an estimate for the actual symbol levels “1” and “4”, respectively.

[0078] At least one decision threshold A.sub.th,i, for example several decision thresholds A.sub.th,i are determined based on the at least two different levels determined previously (step S5). In some embodiments, the decision thresholds A.sub.th,i, are determined based on the highest level A.sub.max and the lowest level A.sub.min of the set of input signal samples, and based on the modulation type of the input signal.

[0079] More precisely, the decision thresholds A.sub.th,i, are determined according to the equation

[00001]$A_{\mathrm{th},i}=A_{\max }-\left(2k+1\right)p\Delta A,$

[0080] or according to the equation

[00002]$A_{\mathrm{th},i}=A_{\min }+\left(2k+1\right)p\Delta A,$

[0081] wherein k is an integer equal to or bigger than zero, and wherein ΔA corresponds to the level difference between the highest level A.sub.max and the lowest level A.sub.min, i.e. ΔA=A.sub.max−A.sub.min. Moreover, p is a proportionality factor.

[0082] In general, the proportionality factor p depends on the actual modulation type of the input signal. For several different types of modulations, e.g. for the class PAM-N modulations, the distance between neighboring levels of the symbol sequence is (approximately) constant. Accordingly, the proportionality factor can be determined directly based on the overall number N of possible different levels according to p=1/(2(N−1)). Moreover, the range of the integer k is also limited by the employed modulation. More precisely, k can run from 0 to N−2.

[0083] The resulting decision thresholds A.sub.th,i, are located half way between respective pairs of neighboring levels of the symbol sequence.

[0084] In the particular example shown in FIG. 4, the first decision threshold A.sub.th,i=may be obtained by setting k=0 and p=¼, such that A.sub.th,i=A.sub.max¼ ΔA.

[0085] The second decision threshold A.sub.th,2 may be obtained by setting k=1 and p=¼, such that A.sub.th,2=A.sub.max−¾ ΔA.

[0086] The input signal may be decoded based on the decision threshold(s) A.sub.th,i, determined previously (step S6). In other words, the symbol values of the individual symbols of the symbol sequence are determined based on the decision threshold(s) A.sub.th,i, determined previously.

[0087] In general, the decision thresholds A.sub.th,i, define decision corridors that are each associated with one particular symbol value.

[0088] The level of the input signal and the decision threshold(s) may be compared at symbol times in order to decode the input signal, wherein the symbol times are defined by the clock signal.

[0089] In general, the symbol time is located in an inner portion of the respective symbol, for example in the middle of the respective symbol. In other words, the symbol time is located rather far away from potential signal edges and the usual deformations of the input signal being associated with the signal edges.

[0090] In the particular example shown in FIG. 4, a first decision corridor is located below the second decision threshold A.sub.th,2. If the amplitude of the input signal lies below A.sub.th,2 at a certain decision time (e.g. at the symbol time), the value of the current symbol is determined to be “4”.

[0091] A second decision corridor is located between the first decision threshold A.sub.th,1 and the second decision threshold A.sub.th,2. If the amplitude of the input signal lies within that decision corridor at the certain decision time (e.g. at the symbol time), the value of the current symbol is determined to be “0”.

[0092] A third decision corridor is located above the first decision threshold A.sub.th,1. If the amplitude of the input signal lies above A.sub.th,1 at the certain decision time (e.g. at the symbol time), the value of the current symbol is determined to be “1”.

[0093] The decoded input signal and the recovered clock signal may be forwarded to the processing module 20 for further processing and/or analysis of the input signal.

[0094] For example, the processing module may analyze certain properties of the input signal based on the decoded input signal and/or based on the recovered clock signal, e.g. properties being related to a signal integrity of the input signal, such as noise and jitter comprised in the input signal.

[0095] With the signal analysis method described above, the decision threshold(s) can be determined with high accuracy, as the input signal samples used for determining the at least two different levels carry less perturbations compared to the original input signal. Accordingly, the input signal can be decoded with a small symbol error rate. Moreover, no user input is required, for example no user input regarding the decision thresholds. Instead, the signal analysis method described above can be performed in a fully automatic manner

[0096] The measurement device 10 and/or the signal analysis module 12, including such components as, for example, a clock recovery module 16, a signal decoder module 18, and the processing module 20, etc., is configured to perform one or more steps schematically shown, for example, in FIG. 2. In some embodiments, one or more of these components includes one or more computer-readable media containing computer readable instructions embodied thereon that, when executed by one or more computer circuits (contained in or associated with the measurement device 10 or components thereof), cause the one or more computer circuits to perform one or more steps of the method of FIG. 2 described above. In some embodiments, the one or more computer circuits, sometimes referred to as computing devices, includes a microprocessor, a microcontroller, a central processing unit, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc. In some embodiments, the one or more computer-readable media contains computer readable instructions embodied thereon that, when executed by the one or more computer circuits, cause the one or more computer circuits to perform one or more steps of any of the methods of claims 1-10.

[0097] As described briefly above, certain embodiments disclosed herein utilize circuitry (e.g., one or more circuits) in order to implement standards, protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, store information, display information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph.

[0098] In an embodiment, circuitry includes, among other things, one or more computing devices or computer circuits such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof. In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof).

[0099] In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein. In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation. In an embodiment, circuitry includes one or more processors or portions thereof and accompanying software, firmware, hardware, and the like.

[0100] In some examples, the functionality described herein can be implemented by special purpose hardware-based computer systems or circuits, etc., or combinations of special purpose hardware and computer instructions.

[0101] Of course, in some embodiments, two or more of the modules, units, etc., described above, or parts thereof, can be integrated or share hardware and/or software, circuitry, etc. In some embodiments, these components, or parts thereof, may be grouped in a single location or distributed over a wide area. In circumstances were the components are distributed, the components are accessible to each other via communication links. The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.