Driving method for active matrix display

Abstract

A method is provided for driving an active matrix display device comprising a matrix of pixels configured to display an n-bit image data in an image frame by dividing the image frame for each pixel into n subframes; defining the n-bit image data to have n1 number of greater significant bits and n2 number of lesser significant bits, where n1+n2=n; and selecting the rows of pixels non-sequentially in the subframes corresponding to the n2 number of lesser significant bits such that there is no more than one row of pixel being selected in each subframe. The provided method can utilize the scan sequence in a more flexible way to make better use of the available scan time such that a higher display resolution or dynamic range can be achieved without increasing the scanning frequency.

Claims

1. A method for driving an active matrix display panel comprising a matrix of pixels organized in Nr number of rows and Nc number of columns, each pixel being configured to display an n-bit image data in an image frame; the method comprising: dividing the image frame for each pixel into n subframes, SF.sub.i, each corresponds to a bit b.sub.i in the image data to be displayed by the pixel, where i=0, 1, . . . , n−1, and having a subframe duration being weighted according to a position of the corresponding bit b.sub.i in the image data; dividing each subframe into a scan time and a hold time occurring after the scan time; selecting each row of pixels for each subframe by applying a scanning signal to a scan line connected to the row of pixels over the scan time; and driving each pixel of the row selected in each subframe to emit a luminance by applying a data signal to a data line connected to the pixel and holding the luminance over the hold time; wherein the emitted luminance represents a logic value of a corresponding bit in the image data to be displayed by the pixel; and wherein: the n-bit image data is defined to have n1 number of greater significant bits and n2 number of lesser significant bits, where n1+n2=n; and the rows of pixels are selected non-sequentially in the subframes corresponding to the n2 number of lesser significant bits such that there is no more than one row of pixel being selected in each subframe.

2. The method according to claim 1, wherein the plurality of rows of pixels are grouped into k groups, where k is a natural number equal or greater than 2; subframes corresponding to the n2 number of lesser significant bits for the rows of pixels of the same group are arranged in the same order; and subframes corresponding to the n2 number of lesser significant bits for the rows of pixels of different groups are arranged in different orders.

3. The method according to claim 2, wherein k is a factor of n and the number of rows of pixels of each group is equal to n/k.

4. The method according to claim 2, wherein the plurality of rows of pixels are consecutively grouped.

5. The method according to claim 2, wherein the plurality of rows of pixels are alternately grouped.

6. The method according to claim 1, wherein the subframes corresponding to the n1 number of greater significant bits are arranged before the subframes corresponding to the n2 number of less significant bits.

7. The method according to claim 6, wherein the subframes corresponding to the n1 number of greater significant bits are arranged in a descending order.

8. The method according to claim 6, wherein the subframes corresponding to the n1 number of greater significant bits are arranged in an ascending order.

9. The method according to claim 1, wherein the subframes corresponding to the n1 number of greater significant bits are arranged after the subframes corresponding to the n2 number of less significant bits.

10. The method according to claim 9, wherein the subframes corresponding to the n1 number of greater significant bits are arranged in an ascending order.

11. The method according to claim 9, wherein the subframes corresponding to the n1 number of greater significant bits are arranged in a descending order.

12. The method according to claim 1, wherein the subframes corresponding to the n1 number of greater significant bits are grouped into a first group and a second group; and the first group are arranged before the subframes corresponding to the n2 number of less significant bits; and the second group are arranged after the subframes corresponding to the n2 number of less significant bits.

13. The method according to claim 12, wherein the first group of subframes corresponding to the n1 number of greater significant bits are arranged in an ascending order.

14. The method according to claim 12, wherein the first group of subframes corresponding to the n1 number of greater significant bits are arranged in a descending order.

15. The method according to claim 12, wherein the second group of subframes corresponding to the n1 number of greater significant bits are arranged in an ascending order.

16. The method according to claim 12, wherein the second group of subframes corresponding to the n1 number of greater significant bits are arranged in a descending order.

17. The method according to claim 1, wherein the rows of pixels are selected, in the subframes corresponding to the n2 number of lesser significant bits, based on a prescribed sequence stored in a look-up table.

18. The method according to claim 1, wherein duration in each subframe SF.sub.i is weighted by a weighting factor $\left(\frac{2^i}{2^n}\right).$

19. The method according to claim 18, wherein a subframe SF.sub.0 corresponding to the least significant bit b.sub.0 of the image data is configured to have a duration of ½.sup.nT, while a subframe SF.sub.n−1 corresponding to a most significant bit b.sub.n−1 of the image data is configured to have a duration of ½T, where T is the frame period.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention are described in more details hereinafter with reference to the drawings, in which:

(2) FIG. 1 shows a simplified system block diagram of an active matrix display device according to an embodiment of the present invention;

(3) FIG. 2 depicts an active driving circuit in each pixel of the active matrix display device according to an embodiment of the present invention;

(4) FIG. 3 depicts more detailed system block diagram of a timing controller according to an embodiment of the present invention;

(5) FIG. 4 show scanning pulse waveforms associated with a conventional method for driving an active matrix display;

(6) FIGS. 5-7 depicts how the subframes corresponding to the lesser significant bits are arranged according to various embodiments of the present invention; FIG. 5 shows an embodiment wherein the rows of pixels are grouped; FIG. 6 depicts an embodiment wherein the rows of pixels are consecutively grouped; and FIG. 7 depicts an embodiment wherein the rows of pixels are alternately grouped;

(7) FIG. 8 shows an exemplary look-up table storing a prescribed sequence of scanning for the subframes corresponding to the lesser significant bits according to one embodiment of the present invention;

(8) FIGS. 9A-9B, 10A-10B and 11 illustrates how the subframes corresponding to the greater significant bits are arranged according to various embodiments of the present invention;

(9) FIG. 12A illustrates shows a typical subframe according to an embodiment of the present invention; and FIG. 12B shows a summary table of minimum required numbers of lesser significant bits, n2_min, for different total scan times.

DETAILED DESCRIPTION OF THE INVENTION

(10) In the following description, methods for driving an active matrix display and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

(11) FIG. 1 shows a simplified system block diagram of an active matrix display device. Referring to FIG. 1. the display panel may include a host processor; a timing controller connected to the host processor; a gate driver connected between the timing controller and an active matrix display panel; and a source driver connected between the timing controller and the active matrix display panel.

(12) The host processor may be configured to generate a plurality of input display data and a synchronization signal. The timing controller may be configured to receive the input display data and synchronization signal and generate a row selection signal to the gate driver for selecting the rows of pixels and generate a plurality of output display data, a shift signal and a latch signal to the source driver for programming luminance of each pixel.

(13) Referring to FIG. 2. The active matrix display panel may include a two-dimensional array of pixels. Each pixel has an active driving circuit including transistors T1, T2 and T3, and capacitor C1 and an electroluminescent element, such as LED D1. LED D1 has a positive terminal connected to an anode of the pixel. The capacitor C1 has a first terminal connected to a cathode of the pixel. The transistor T1 has a gate terminal connected to a scan line, a drain terminal connected to a data line and source terminal connected to a second terminal of the capacitor C1. The transistor T2 has a gate terminal connected to the second terminal of the capacitor C1, a drain terminal connected to a negative terminal of the LED D1. The transistor T3 has a gate terminal connected to a current reference grid, a drain terminal connected to a source terminal of transistor T2 and a source terminal connected to the cathode.

(14) Transistor T1 controls gate ON/OFF. Transistor T2 controls the ON/OFF of an electroluminescent element such as a LED. Transistor T3 controls the current amplitude. The gate driver selects through the scan lines the row of pixels to be turn on. The source driver programs the luminance of each pixel through the data lines. All pixels on the display take reference voltage from the current reference grid.

(15) Referring to FIG. 3, the timing controller may comprise a memory module and a time multiplex control logic. The memory module is configured to receive input display data in parallel and dispatch output display data in series. The time multiplex control logic is configured to receive the synchronization signal and control the read and write of the memory module. The time multiplex control logic is further configured to generate the row selection signal to the gate driver, and generate the shift signal and the latch signal to the source driver.

(16) Referring to FIG. 3. The memory module may comprise an array of random access memory (RAM) cells arranged such that the number of RAM columns is at least equal to the number of data lines in the display panel and the number of RAM rows is at least equal to the product of the number of scan lines and the number of bits of image data to be displayed. Each RAM cell is configured to store a value “1” or “0” of a corresponding bit in an image data to be displayed by a corresponding pixel in the display panel.

(17) To represent an image data with n bits, n successive RAM rows of memory will be accessed and RAM cells in each row of the n successive RAM rows are configured to store value of bits in the input data respectively. For example, to represent image data with 8 bits, RAM cells in the first row of the 8 successive rows store values of b0, RAM cells in the second row of the 8 successive rows store values of b1, RAM cells in the third row of the 8 successive rows store values of b2 and so on.

(18) FIG. 4 show scanning pulse waveforms associated with a conventional method for driving an active matrix display. For simplicity, only 16 scan lines (G0, G1, . . . G15) are illustrated. In order to represent a n-bit digital image data, each frame is divided into n sub-frames SF.sub.i, each corresponding to a bit b.sub.i in the digital image data, where i=0, 1, . . . , n−1. The subframes may have different durations which are weighted according to positions of bits to be represented respectively and under a rule that the more significant bit the subframe represents the longer the subframe duration is.

(19) In some embodiments, duration in each subframe SF.sub.i may be weighted by a weighting factor

(20) $\left(\frac{2^i}{2^n}\right)$
and the durations t.sub.i of each the subframes SF.sub.i may be given by

(21) $t_i=\left(\frac{2^i}{2^n}\right)T,$
where T is the frame period. Accordingly, the least significant bit b.sub.0 of the image data may be represented by subframe SF.sub.0 having a duration of

(22) $\frac{1}{2^n}T,$
while the most significant bit b.sub.n−1 may be represented by the subframe SF.sub.n−1 having a duration of

(23) $\frac{1}{2}T.$

(24) In each sub-frame, each row of pixels (or scan lines) is scanned for a scan time. Pixels of the scanned row are then controlled to emits at a fixed luminance (turned ON) or zero luminance (turned OFF) to represent a logical value of “1” or “0” respectively and hold the state over a hold time within the subframe duration. As such, a gray level scale of 2.sup.n levels can be achieved by means of aggregation of the hold times over which the pixel is turned ON within each frame. Assuming the image data has 6 bits, if a pixel at ith row and jth column, denoted as P.sub.ij, has its b3, b2, b1 and b0 being equal to ‘1’, the pixel P.sub.ij may have a relative brightness equals to 15.

(25) The timing controller may further include an internal scan counter (not shown) configured to increment number of clock cycles provided in the synchronization signal and generate scan counts for measuring and controlling the subframe durations.

(26) In order to utilize the scan sequence in a more flexible way, the n-bit image data may be defined to have n1 number of greater significant bits and n2 number of lesser significant bits, where n1+n2=n; and the rows of pixels are selected non-sequentially in the subframes corresponding to the n2 number of lesser significant bits such that there is no more than one row of pixels being selected in each subframe.

(27) FIG. 12A shows a typical subframe according to an embodiment of the present invention. Each row of pixels is scanned for a scan time, Ts. The total scan time to scan all rows of a display is marked as ΣTs. The hold time for a particular bit bi is denoted as Th(i), where i=0, 1, 2, . . . n−1. As such, the hold time for b0 is marked as Th(0) and the hold time for b1 is marked as Th(1) and the hold time for b2 is marked as Th(2) and so on. In this embodiment, Th(1)=2*Th(0) and Th(2)=4*Th(0). The hold time of an upper bit is twice the hold time of its direct successive lower bit. That is Th(i)=2*Th(i−1).

(28) For higher scanning rate, a shorter total scan time is allowed and the rows of pixels should be selected non-sequentially in subframes corresponding to more lesser significant bits.

(29) The maximum total scan time that can be support by b0, b1, b2:

(30) $\begin{array}{c}=\frac{Th\left(0\right)+Th\left(1\right)+Th\left(2\right)}{1.7\times 3}=\frac{Th\left(0\right)+2\times Th\left(0\right)+4\times Th\left(0\right)}{1.7\times 3}\\ =1.37\times Th\left(0\right)\end{array}$

(31) The maximum total scan time that can be support by b0, b1, b2, b3:

(32) $\begin{array}{c}=\frac{Th\left(0\right)+Th\left(1\right)+Th\left(2\right)+Th\left(3\right)}{1.7\times 4}\\ =\frac{Th\left(0\right)+2\times Th\left(0\right)+4\times Th\left(0\right)+8\times Th\left(0\right)}{1.7\times 4}\\ =2.21\times \mathrm{Th}\left(0\right)\end{array}$

(33) The maximum total scan time that can be support by b0, b1, b2, b3, b4:

(34) $\begin{array}{c}=\frac{Th\left(0\right)+Th\left(1\right)+Th\left(2\right)+Th\left(3\right)+\mathrm{Th}\left(4\right)}{1.7\times 5}\\ =\frac{Th\left(0\right)+2\times Th\left(0\right)+4\times Th\left(0\right)+8\times Th\left(0\right)+16\mathrm{Th}\left(0\right)}{1.7\times 5}\\ =3.64\times \mathrm{Th}\left(0\right)\end{array}$

(35) The number 1.7 used in the above calculation is a magic number which is needed to provide enough margin to maneuver the swapping of subframes within each group.

(36) FIG. 12B shows a summary table of minimum required numbers of lesser significant bits, n2 min, for different total scan times. When ΣTs≤1.3Th(0), the minimum required number of lesser significant bits is 3; When ΣTs≤2.2 Th(0), the minimum required number of lesser significant bits is 4; When ΣTs≤3.6 Th(0), the minimum required number of lesser significant bits is 5.

(37) Therefore, if ΣTs is equal to 1.5*Th(0), then the lesser significant bits must include b0, b1, b2 and b3. If ΣTs is equal to 2.5*Th(0), then the lesser significant bits must include b0, b1, b2, b3 and b4. Of course, if Ts equals 1.5*Th(0), the lesser significant bits can include more than the required bits, such as b0, b1, b2, b3 and b4, but this would make the hardware design unnecessarily complicated.

(38) In accordance with some embodiments of the present invention, the plurality of rows of pixels are grouped into k groups, where k is a natural number equal or greater than 2. Preferably, k may be a factor of n and the number of rows of pixels of each group may be equal to n/k.

(39) Subframes corresponding to the n2 number of lesser significant bits for the rows of pixels of the same group are arranged in the same order; and subframes corresponding to the n2 number of lesser significant bits for the rows of pixels of different groups are arranged in different orders.

(40) FIG. 5 depicts scanning pulse waveforms associated with a method for driving an active matrix display according to an embodiment of the present invention. In this embodiment, the number of lesser significant bits, n2, is defined to be 4. The subframes corresponding to the 4 lesser significant bits b3, b2, b1 and b0 are SF3, SF2, SF1, and SF0 respectively.

(41) Referring to FIG. 5. The 16 scan lines are grouped into 2 groups. For the first group (G0, G1, G2, G3, G12, G13, G14, G15), the sequence of subframes is arranged in the order of SF3-SF0-SF1-SF2. For the second group (G4, G5, G6, G7, G8, G9, G10, G11), the sequence of subframes is arranged in the order of SF1-SF0-SF3-SF2.

(42) In accordance with some embodiments of the present invention, the plurality of rows of pixels may be consecutively grouped. FIG. 6 depicts scanning pulse waveforms associated with a method for driving an active matrix display wherein the rows of pixels are consecutively grouped. For simplicity, only 16 scan lines (G0, G1, G15) are illustrated. In this embodiment, the number of lesser significant bits, n2, is defined to be 4. The subframes corresponding to the 4 lesser significant bits b3, b2, b1 and b0 are SF3, SF2, SF1, and SF0 respectively.

(43) Referring to FIG. 6. The 16 scan lines are consecutively grouped into 4 groups. For the first group (G0, G1, G2, G3), the sequence of subframes is arranged in the order of SF3-SF0-SF1-SF2. For the second group (G4, G5, G6, G7), the sequence of subframes is arranged in the order of SF2-SF1-SF0-SF3. For the third group (G8, G9, G10, G11), the sequence of subframes is arranged in the order of SF1-SF0-SF3-SF2. For the fourth group (G12, G13, G14, G15), the sequence of subframes is arranged in the order of SF0-SF3-SF2-SF1.

(44) In accordance with some embodiments of the present invention, the plurality of rows of pixels may be alternately grouped. FIG. 7 depicts scanning pulse waveforms associated with a method for driving an active matrix display wherein the rows of pixels are alternately grouped. For simplicity, only 16 scan lines (G0, G1, G15) are illustrated. In this embodiment, the number of lesser significant bits, n2, is defined to be 4. The subframes corresponding to the 4 lesser significant bits b3, b2, b1 and b0 are SF3, SF2, SF1, and SF0 respectively.

(45) Referring to FIG. 7. The 16 scan lines are alternately grouped into 2 groups. For the first group (G0, G2, . . . , G14), the sequence of subframes is arranged in the order of SF3-SF0-SF1-SF2. For the second group (G1,

(46) , . . . , G15), the sequence of subframes is arranged in the order of SF1-SF0-SF3-SF2.

(47) In accordance with various embodiments of the present invention, the sequence of scanning for the subframes corresponding to the n2 number of lesser significant bits may be prescribed and stored in a look-up table. FIG. 8 shows an exemplary look-up table according to the embodiment of FIG. 6. For illustration purpose, the look-up table are separated into Part 1, 2, 3. Based on the look-up table, at most one scan line is selected and one RAM row is deployed for driving the pixels in the selected row with the value of a corresponding bit for each scan count.

(48) For example, at the 10.sup.th scan count, the 10.sup.th scan line is selected and RAM row 41 is deployed for driving the pixels in the 10.sup.th row with the value of bit b1; at the 20.sup.th scan count, the 12.sup.th scan line is selected and RAM row 51 is deployed for driving the pixels in the 12.sup.th row with the value of bit b3; at the 40.sup.th scan count, no scan line is selected and no RAM is deployed; and at the 99.sup.th scan count, the 11.sup.th scan line is selected and RAM row 46 is deployed for driving the pixels in the 11.sup.th row with the value of bit b2.

(49) The size of the look-up table depends on a total number of scan counts (or time slots) required to complete the scanning for the subframes corresponding to the n2 number of lesser significant bits. The number of scan counts required for each subframe is proportional to the duration of the subframe. Therefore, for representing an image data, the numbers of time slots N.sub.i for representing a bit bi of an image data may be given by N.sub.i=2.sup.iN.sub.0, where N.sub.0 is the number of time slots in the subframe representing the least significant bit b0. Therefore, the total number of time slots required to complete the scanning for the subframes corresponding to the n2 number of lesser significant bits is equal to N.sub.0Σ.sub.i=0.sup.i=n2−12.sup.i.

(50) Referring back to the look-up table of FIG. 8, the number of time slots in the subframe representing the least significant bit b0 is set to be 8, therefore the total number of scan counts for scanning the subframes corresponding to the 4 lesser significant bits b3, b2, b1 and b0 is equal to 8*Σ.sub.i=0.sup.i=32.sup.i=8*(1+2+4+8)=200 (from scan counts 0 to 119).

(51) FIGS. 9A-9B, 10A-10B and 11 illustrate how the subframes corresponding to the n1 number of greater significant bits in the n-bit image data are arranged according to various embodiments of the present invention.

(52) In some embodiments, the subframes corresponding to the n1 number of greater significant bits are arranged before the subframes corresponding to the n2 number of less significant bits.

(53) FIGS. 9A and 9B depict embodiments in which subframes corresponding to the greater significant bits are arranged before the subframes corresponding to the less significant bits. For simplicity, the n-bit image data is assumed to be a 6-digit image data and defined to have 2 greater significant bits and 4 lesser significant bits.

(54) In one embodiment, the subframes corresponding to the n1 number of greater significant bits may be arranged in a descending order (with durations arranged from the longest to the shortest). As shown in FIG. 9A, the subframes SF5 and SF4 corresponding to the 2 greater significant bits b5 and b4 are arranged in the order of SF5-SF4 (with durations arranged from ½ to ¼).

(55) In another embodiment, the subframes corresponding to the n1 number of greater significant bits may be arranged in an ascending order (with durations arranged from the shortest to the longest). As shown in FIG. 9B, the subframes SF5 and SF4 corresponding to the 2 greater significant bits b5 and b4 are arranged in the order of SF4-SF5 (with durations arranged from ¼ to ½).

(56) FIGS. 10A and 10B depict embodiments in which subframes corresponding to the greater significant bits are arranged after the subframes corresponding to the less significant bits. For simplicity, the n-bit image data is assumed to be a 6-digit image data and defined to have 2 greater significant bits and 4 lesser significant bits.

(57) In one embodiment, the subframes corresponding to the n1 number of greater significant bits may be arranged in a descending order (with durations arranged from the longest to the shortest). As shown in FIG. 10A, the subframes SF5 and SF4 corresponding to the 2 greater significant bits b5 and b4 are arranged in the order of SF5-SF4 (with durations arranged from ½ to ¼).

(58) In another embodiment, the subframes corresponding to the n1 number of greater significant bits may be arranged in an ascending order (with durations arranged from the shortest to the longest). As shown in FIG. 10B, the subframes SF5 and SF4 corresponding to the 2 greater significant bits b5 and b4 are arranged in the order of SF4-SF5 (with durations arranged from ¼ to ½).

(59) FIG. 11 depict embodiments in which the subframes corresponding to the n1 number of greater significant bits are grouped into a first group and a second group; the first group are arranged before the subframes corresponding to the n2 number of less significant bits; and the second group are arranged after the subframes corresponding to the n2 number of less significant bits. For simplicity, the n-bit image data is assumed to be an 8-digit image data and defined to have 4 greater significant bits and 4 lesser significant bits.

(60) As shown in FIG. 11, the subframes SF7, SF5 and SF4 corresponding to the first group of 3 greater significant bits b7, b5 and b4 are arranged before the subframes corresponding to the 4 number of less significant bits b3-b0, and the subframes SF6 corresponding to the second group of 1 greater significant bit b6 is arranged after the subframes corresponding to the 4 number of less significant bits b3-b0.

(61) It should be apparent to practitioner skilled in the art that the foregoing examples of digital driving methods are only for the purposes of illustration of working principle of the present invention. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed.

(62) The embodiments disclosed herein may be implemented using general purpose or specialized computing devices, computer processors, or electronic circuitries including but not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software codes running in the general purpose or specialized computing devices, computer processors, or programmable logic devices can readily be prepared by practitioners skilled in the software or electronic art based on the teachings of the present disclosure.

(63) In some embodiments, the present invention includes computer storage media having computer instructions or software codes stored therein which can be used to program computers or microprocessors to perform any of the processes of the present invention. The storage media can include, but are not limited to ROMs, RAMS, flash memory devices, or any type of media or devices suitable for storing instructions, codes, and/or data.

(64) The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

(65) The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalence.