Abstract
A system for converting an optical signal into an electrical signal includes at least one differential Trans-Impedance Amplifier (TIA). To minimize (preferably eliminate) DC offset issues at the TIA output, an Input Counter-Offset (ICO) circuit is provided to remove the DC component of the initial optical signal from the input to the TIA. To further maximize the removal of DC offset at the TIA output, an Output Counter-Offset circuit is provided to take DC offset from the TIA output for use as a negative feedback directly to the input of the TIA. Modifications of the present invention are also intended for use with two TIA terminations and with a travelling wave photodiode.
Claims
1. A system for converting an optical signal into an electrical signal which comprises: a photodiode responsive to an optical signal for generating a photocurrent having an AC component I.sub.pd(AC) and a DC component I.sub.pd(DC); an Input Counter-Offset (ICO) circuit for removing the DC component I.sub.pd(DC) from the photocurrent to establish an ICO output including the AC component I.sub.pd(AC); a differential Trans-impedance Amplifier (TIA) having a first input port and a second input port, wherein the ICO output is received as an input to the first input port of the TIA; and an Output Counter-Offset (OCO) circuit for receiving a differential DC output from the TIA to detect any DC offset therein, wherein any DC offset in the TIA output is employed as a negative feedback to the second input port of the TIA to cancel the output DC offset.
2. The system of claim 1 wherein the output DC offset is caused by circuit unbalancing due to process-voltage-temperature variations in the TIA.
3. The system of claim 1 further comprising an AC shunt capacitor located between the OCO and the second input port of the TIA to filter AC noise from the DC output of the TIA.
4. The system of claim 1 wherein the differential TIA has a first DC output and a second DC output, and wherein the OCO comprises: a first low pass filter for receiving the first DC output from the TIA; a second low pass filter for receiving the second DC output from the TIA; and an Operational Amplifier (OPA) for receiving the first DC output from the first low pass filter and the second DC output from the second low pass filter to quantify a voltage difference, ΔV, for the DC offset to be used as a negative feedback to the second input port of the TIA to counter the output DC offset.
5. The system of claim 4 wherein the Operational Amplifier (OPA) has a differential output, and wherein a first OPA output is established with a negative feedback to the second input port of the TIA, and a second OPA output is established with a negative feedback via the ICO to the first input port of the TIA.
6. The system of claim 1 wherein the TIA provides a bias voltage for the ICO.
7. A system for converting an optical signal into an electrical signal having an improved broader bandwidth which comprises: a photodiode responsive to an optical signal for generating a photocurrent which splits into a first photocurrent having an AC component I.sub.pd(AC) and a DC component I.sub.pd(DC) and a second photocurrent having an AC component I.sub.pd(AC) and a DC component I.sub.pd(DC); a first differential Trans-impedance Amplifier (TIA) having a first input port for receiving the first photocurrent from the photodiode, and having a second input port, a first output port and a second output port; a second differential Trans-Impedance Amplifier (TIA) having a first input port for receiving the second photocurrent from the photodiode, and having a second input port, a first output port and a second output port; a first Input Counter-Offset (ICO) circuit for removing the DC component I.sub.pd(DC) from the first photocurrent to establish a first ICO output including its AC component I.sub.pd(AC) wherein the first ICO output is received as an input to the first input port of the first differential TIA; a second Input Counter-Offset (ICO) circuit for removing the DC component I.sub.pd(DC) from the second photocurrent to establish a second ICO output including its AC component I.sub.pd(AC) wherein the second ICO output is received as an input to the first input port of the second differential TIA; and a differential summer for receiving the output from the first DC-coupled output port of the first differential TIA and the output from the second DC-coupled output port of the first differential TIA, and for simultaneously receiving the output from the first DC-coupled output port of the second differential TIA and the output from the second DC-coupled output port of the second differential TIA to establish the electrical signal.
8. The system of claim 7 further comprising: a first Output Counter-Offset (OCO) circuit for receiving the first output and the second output from the first differential TIA to detect any DC offset therebetween, wherein any DC offset in the output of the first differential TIA is employed as a negative feedback to the second input port of the first differential TIA to cancel the output DC offset; and a second Output Counter-Offset (OCO) circuit for receiving the first output and the second output from the second differential TIA to detect any DC offset therebetween, wherein any DC offset in the output of the second differential TIA is employed as a negative feedback to the second input port of the second differential TIA to cancel the DC offset.
9. The system of claim 8 wherein the output DC offset of the first differential TIA and the DC offset of the second differential TIA are caused by circuit unbalancing due to process-voltage-temperature variations in the TIA.
10. The system of claim 8 further comprising: a first AC shunt capacitor located between the first OCO and the second input port of the first TIA to filter AC noise from the DC output of the first TIA; and a second AC shunt capacitor located between the second OCO and the second input port of the second TIA to filter AC noise from the DC output of the second TIA.
11. The system of claim 8 wherein the first and second differential TIAs respectively have a first DC output and a second DC output, and wherein the respective OCOs of the first and second differential TIAs each comprises: a first low pass filter for receiving the first DC output from the TIA; a second low pass filter for receiving the second DC output from the TIA; and an Operational Amplifier (OPA) for receiving the first DC output from the first low pass filter and the second DC output from the second low pass filter to quantify a voltage difference, ΔV, for the DC offsets to be used as a negative feedback to the second input port of the respective TIA.
12. The system of claim 11 wherein the Operational Amplifier (OPA) of each TIA has a differential output, and wherein a first OPA output is established with a negative feedback to the second input port of the respective TIA, and a second OPA output is established with a negative feedback via the respective ICO to the first input port of the respective TIA.
13. The system of claim 7 wherein at least one differential TIA provides a photodiode bias voltage through the ICO.
14. The system of claim 7 further comprising: a first inductor positioned between the photodiode and the first input port of the first differential TIA; and a second inductor positioned between the photodiode and the first input port of the second differential TIA.
15. A system for converting a traveling wave photocurrent into an electrical signal which comprises: a traveling wave photodiode responsive to an optical signal for generating a photocurrent which splits into a first photocurrent and a second photocurrent; a first differential Trans-Impedance Amplifier (TIA) having a first input port for receiving the first photocurrent from the traveling wave photodiode, and having a second input port, a first DC output port and a second DC output port; a second differential Trans-Impedance Amplifier (TIA) having a first input port for receiving the second photocurrent from the traveling wave photodiode, and having a second input port, a first DC output port and a second DC output port; a first transmission line for transmitting the first photocurrent from the traveling wave diode to the first differential TIA; and a second transmission line for transmitting the second photocurrent from the traveling wave diode to the second differential TIA.
16. The system of claim 15 wherein a characteristic impedance of the traveling wave photodiode, an impedance of the first and second transmission lines, and an impedance of the inputs to the first and second differential TIM have the same value.
17. The system of claim 15 further comprising: A first Output Counter-Offset (OCO) circuit for receiving a differential DC output from the first differential TIA to detect any DC offset therein, wherein any DC offset in the first differential TIA output is employed as a negative feedback to the second input port of the first differential TIA to cancel the output DC offset; and a second Output Counter-Offset (OCO) circuit for receiving a differential DC output from the second differential TIA to detect any DC offset therein, wherein any DC offset in the second differential TIA output is employed as a negative feedback to the second input port of the second differential TIA to cancel the output DC offset.
18. The system of claim 17 wherein the output DC offset of the first differential TIA and the DC offset of the second differential TIA are caused by circuit unbalancing due to process-voltage-temperature variations in the TIA.
19. The system of claim 18 wherein the first and second differential TIM respectively have a first DC output and a second DC output, and wherein the respective OCOs of the first and second differential TIAs each comprises: a first low pass filter for receiving the first DC output from the TIA; a second low pass filter for receiving the second DC output from the TIA; and an Operational Amplifier (OPA) for receiving the first DC output from the first low pass filter and the second DC output from the second low pass filter to quantify a voltage difference, ΔV, for the DC offsets to be used as a negative feedback to the second input port of the respective TIA.
20. The system of claim 19 wherein the Operational Amplifier (OPA) of each TIA has a differential output, and wherein a first OPA output is established with a negative feedback to the second input port of the respective TIA, and a second OPA output is established with a negative feedback via the respective ICO to the first input port of the respective TIA.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The novel features of this invention, as well as the invention itself, both as to its structure and its operation, will be best understood from the accompanying drawings, taken in conjunction with the accompanying description, in which similar reference characters refer to similar parts, and in which:
[0020] FIG. 1 is a schematic diagram of the general circuitry for the present invention;
[0021] FIG. 2A is a schematic diagram showing components of the circuitry connected, in combination, with the input port and the diode bias port of the TIA, when the circuitry is configured with the anode of the diode connected to the input port of the TIA, and the circuitry includes a current sensor;
[0022] FIG. 2B is a schematic of a cancellation circuit having a current mirror sensor for the configuration of the circuitry shown in FIG. 2A;
[0023] FIG. 2C is a schematic of a cancellation circuit, having a current mirror sensor and an auxiliary circuit to enhance the mirroring accuracy and stability, for the configuration of the circuitry shown in FIG. 2A;
[0024] FIG. 3A is a schematic diagram showing components of the circuitry connected, in combination, with the input port and the diode bias port of the TIA, when the circuitry is configured with the cathode of the diode connected to the input port of the TIA, and the circuitry includes a current sensor;
[0025] FIG. 3B is a schematic of a cancellation circuit having a current mirror sensor for the configuration of the circuitry shown in FIG. 3A;
[0026] FIG. 3C is a schematic of a cancellation circuit, having a current mirror sensor and an auxiliary circuit to enhance the mirroring accuracy and stability, for the configuration of the circuitry shown in FIG. 3A;
[0027] FIG. 4 is a schematic diagram of a representative feedback function for a current correction controller which is used when a voltage sensor is included in the circuit element of the present invention;
[0028] FIG. 5 is a schematic diagram of the present invention employing a voltage sensor when the anode of a photodiode is connected to the input port of a TIA;
[0029] FIG. 6 is a schematic diagram of the present invention employing a voltage sensor when the cathode of a photodiode is connected to the input port of a TIA;
[0030] FIG. 7 is a schematic diagram of a differential TIA employing an Input Counter-Offset (ICO) circuit and an Output Counter-Offset (OCO) circuit for opto-electrical signals;
[0031] FIG. 8 is a schematic diagram of a differential TIA showing details of the ICO and OCO circuits referred to in FIG. 7;
[0032] FIG. 9 is a schematic diagram of a differential TIA employing differential feedback elements;
[0033] FIG. 10 is a schematic diagram of an optical receiver with two TIA terminations; and
[0034] FIG. 11 is a schematic diagram of a travelling wave optical receiver with two TIA terminations.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] Referring initially to FIG. 1, a circuitry in accordance with the present invention is shown and is generally designated 10. As shown, the circuitry 10 includes a circuit element 12 that is connected between a photodiode (PD) 14 and a Trans-Impedance Amplifier (TIA) 16. Also, as shown, the photodiode 14 has two nodes, an anode 18 and a cathode 20. Further, the TIA 16 includes an input port 22 and a diode bias port 24. In accordance with the present invention the anode 18 and the cathode 20 of the photodiode 14 are connected to the circuit element 12. Also, the input port 22 and the diode bias port 24 of the TIA 16 are connected to the circuit element 12.
[0036] Still referring to FIG. 1 it will be appreciated that the circuit element 12 includes a low pass filter (LPF) 26 and a sensor 28 that work together to control a current source 30. For purposes of the present invention, it is this current source 30 which outputs a cancellation current that cancels the unwanted offset issues that are mentioned above in the Background of the Invention, which would otherwise arise at the input port 22 of the TIA 16.
[0037] As disclosed in greater detail below, there are several embodiments for the present invention. Individually, these embodiments differ structurally from each other in two important respects. In one, the orientation of the anode 18 and cathode 20 of the photodiode 14 with the circuit element 12 can be reversed. In the other, the sensor 28 that is used for the circuit element 12 can be either a current sensor or a voltage sensor. Thus, there are essentially four different embodiments of the present invention (FIGS. 2A, 3A, 5 and 6, respectively).
[0038] FIG. 2A shows an embodiment of the circuit element 12 wherein the anode 18 of the photodiode 14 is connected to the input port 22 of the TIA 16 and the cathode 20 is connected to its diode bias port 24 through a current sensor 32. For the embodiment shown in FIG. 2A, a cancellation circuit 34 includes a current sensor 32 (the sensor 28 in FIG. 1) that interacts with a current source 30. Also, an AC bypass capacitor 36 is connected between the cathode 20 of the photodiode 14 and the current sensor 32. With reference to FIG. 2B it will be seen that the cancellation circuit 34 for this embodiment includes a first filtering mirror 38a that is biased by a voltage V.sub.b+. In detail, the first filtering mirror 38a, having a current sensor 32 and a low pass filter 26a, is connected to the cathode 20 of the photodiode 14 with the AC bypass capacitor 36 connected therebetween. The second filtering mirror 38b, having a second low pass filter 26b and a current source 30, is then connected to the anode 18 of the photodiode 14, with the input port 22 of the TIA 16 connected therebetween. The function of AC bypass capacitor 36 is to direct an AC portion I.sub.pd(AC) of the photocurrent from cathode 20 to ground, and to direct a DC portion I.sub.pd(DC) of the photocurrent to go through the current sensor 32. Further rejection of the AC portion I.sub.pd(AC) in the current sensor 32 is accomplished with the low pass filter 26, e.g., connecting a resistor between the drain and the gate of a metal-oxide-semiconductor current sensor 32 together with a shunt capacitor connecting the sensor's gate to ground. In this invention, a low pass filter having a large RC time constant can be monolithically integrated with an ultra-low leakage metal-oxide gate. In a cooperation well known in the pertinent art, the current I.sub.pd(DC) (referring to FIGS. 2A and 2B) sensed by the first filtering mirror 38a will be imaged by the second filtering mirror 38b to thereby create a cancellation current which will cancel the DC portion I.sub.pd(DC) of the photocurrent prior to inputting the AC portion I.sub.pd(AC) into the TIA. The second low pass filter 26b in the second filtering mirror is used to reduce the current noise generated by the current source 30. An alternative cancellation circuit 34 can comprise an auxiliary circuit 48 between filtering mirrors 38a and 38b, as shown in FIG. 2C. This alternative cancellation circuit 34 is provided to improve the current mirroring accuracy and stability over a wide photocurrent operational range.
[0039] As a generalized mirror image of the circuit element 12 shown in FIG. 2A, FIG. 3A shows an embodiment of the circuit element 12 wherein the cathode 20 of the photodiode 14 is connected to the input port 22 of the TIA 16, and the anode 18 is connected to the diode bias port 24 of the TIA 16. Again, the sensor 28 (in FIG. 1) is a current sensor 32 that interacts with a current source 30. In this embodiment, however, the AC bypass capacitor 36 is connected between the anode 18 of the photodiode 14 and the current sensor 32. Further, with reference to FIG. 3B it will be seen that the first filtering mirror 38a is biased by a voltage V and is connected to the anode 18 of the photodiode 14, with the AC bypass capacitor 36 connected therebetween. The second filtering mirror 38b is then connected to the cathode 20 of the photodiode 14 and is biased with a voltage V.sub.b+, with the input port 22 of the TIA 16 connected therebetween. Thus, similar to the embodiment shown in FIG. 2A, the current I.sub.pd(DC) in the first filtering mirror 38a will be imaged by the second filtering mirror 38b to thereby create a cancellation current which will cancel the DC portion I.sub.pd(DC) in the photocurrent prior to inputting the AC portion I.sub.pd(AC) into the TIA. The current mirroring accuracy and stability, over a wide photocurrent operational range, can be improved with an alternative cancellation circuit 34 comprising an auxiliary circuit 48 between filtering mirrors 38a and 38b shown in FIG. 3C.
[0040] FIG. 4 shows a configuration for the present invention wherein voltage measurements function in combination with a current source 30. Further, for this configuration using a voltage sensor 40 (see FIG. 5), the circuit element 12 receives a bias voltage V.sub.b+ from the diode bias port 24 of the TIA 16 that depends on the orientation to the anode 18 and the cathode 20 of the photodiode 14 with the circuit element 12.
[0041] As shown in FIG. 5, the anode 18 of the photodiode 14 is connected to the input port 22 of the TIA 16. On the other hand, the cathode 20 of the photodiode 14 is connected to an AC bypass capacitor 36. Further, the circuit element 12 is connected to the diode bias port 24 with a bias voltage V.sub.b+. Within the cancellation circuit 42 of the circuit element 12, the voltage sensor 40 is connected to a correction processor 44. Further, the voltage sensor 40 is connected via a high impedance low pass filter 26a to the anode 18 of the photodiode 14 and also to the input port 22 of the TIA 16.
[0042] In combination, the voltage sensed by the voltage sensor 40 from the anode 18 of the photodiode 14 is provided as an output 46 that is sent to the correction processor 44, where a reference voltage, V.sub.ref, is also received by the correction processor 44. In the correction processor 44, the difference between the output 46 from the voltage sensor 40 and the reference voltage V.sub.ref is identified as a differential ΔV. This ΔV then generates a correction voltage, connected through a low pass filter 26b, for adjusting a cancellation current output from the current source 30. As in the other embodiments for the present invention, the resultant cancellation current is used for controlling any offset issues occurring at the input port 22 of the TIA 16.
[0043] FIG. 6 shows a comparable configuration for a voltage sensor 40 version of the circuit element 12. In the configuration shown in FIG. 6, however, the cathode 20 of the photodiode 14 is connected to the input port 22 of the TIA 16, while the anode 18 of the photodiode 14 is connected to the AC bypass capacitor 36. Further, the circuit element 12 is connected to the diode bias port 24 with a bias voltage V.sub.b−. In all other respects the embodiments of the present invention disclosed in FIGS. 5 and 6 function similarly.
[0044] In an operation of the present invention, the photodiode 14 generates a photocurrent in response to an optical signal. As a consequence, the photocurrent has an AC portion I.sub.pd(AC) and a DC portion I.sub.pd(DC). As noted above, the purpose of the present invention is to eliminate the DC portion I.sub.pd(DC) from the photocurrent as it enters the input port 22 of the TIA 16. As also noted above, this can be done in accordance with the operation of any one of four different configurations for a circuit element 12.
[0045] A simplified operation of the embodiments for the circuit element 12 shown in FIGS. 2A and 3A which use a current sensor 32, can be explained by considering the photocurrent I.sub.pd(AC)+I.sub.pd(DC) that is generated by the photodiode 14. For these embodiments filtering mirrors 38a and 38b are used to create an image of the DC portion I.sub.pd(DC) of the photocurrent from one node of the diode 14. This image current is then fed back into the other node of the diode 14 to cancel (suppress) the DC portion I.sub.pd(DC) of the photocurrent prior to its input into the TIA.
[0046] Similarly, an operation of embodiments for the circuit element 12 shown in FIGS. 5 and 6 which use a voltage sensor 40, can be explained by again considering the photocurrent I.sub.pd(AC)+I.sub.pd(DC) that is generated by the photodiode 14. For these embodiments, low pass filters 26a and 26b are used to isolate the voltage sensor 40 and the correction processor 44 from the AC portion I.sub.pd(AC) of the photocurrent. In this isolation, the output 46 of the voltage sensor 40 is compared with a reference voltage V.sub.ref to identify a differential voltage ΔV. This differential voltage ΔV is then used to adjust a cancellation current until the DC portion I.sub.pd(DC) of the photocurrent is suppressed and only the AC portion I.sub.pd(AC) of the photocurrent is provided for input to the input port 22 of the TIA 16.
[0047] Prior disclosure has pertained generally to TIAs having a single input for a photocurrent and a single output for an electrical current. The use of a differential TIA 50 for a similar purpose is now disclosed. With reference to FIG. 7 it will be seen that a differential TIA has a bias port 52, a first input port 54, and a second input port 56. Also, in addition to gain amplifiers, the driver amplifier of differential TIA 50 has a first output port 58 and a second output port 60.
[0048] FIG. 7 also shows that the bias port 52 and first input port 54 of the differential TIA 50 are connected to an Input Counter-Offset (ICO) circuit 62 which, in turn, is connected to the photodiode 14. It is also important to note that the ICO 62 is essentially the same as the circuit element 12 disclosed above. FIG. 7 also shows that the output ports 58 and 60 of the differential TIA 50 are connected to an Output Counter-Offset (OCO) circuit 64. Importantly, the output of the OCO 64 is connected via a shunt capacitor 66 to the second input port 56 of the differential TIA 50.
[0049] Referring now to FIG. 8, it is seen that the first output port 58 of the differential TIA 50 is connected to a first low pass filter 68 and, likewise, the second output port 60 is connected to a second low pass filter 70. The low pass filters 68 and 70 are then connected with an Operational Amplifier (OPA) 72. Output from the OPA 72 is shown connected, in sequence, with a third low pass filter 74, a current source 76 and a shunt capacitor 78 before connecting with the second input port 56 of the differential TIA 50. In combination, the low pass filters 68 and 70, the Operational Amplifier (OPA) 72, the low pass filter 74, current source 76 and shunt capacitor 78 collectively constitute the Output Counter-Offset (OCO) 64 shown in FIG. 7. Thus, the OCO 64 provides a DC current I.sub.bias±I.sub.OCO, to the second input port 56 of the differential TIA 50, where I.sub.bias provides a TIA input bias current and loco is the output DC-offset compensation current.
[0050] In contrast with the circuitry shown in FIG. 8 for separate operations of the ICO 62 and OCO 64, FIG. 9 shows another embodiment of this circuitry wherein the ICO 62 and OCO 64 are combined. In detail, for this embodiment the OPA 72 has an additional differential output 82 which is connected via a fourth low pass filter 84 to the current source 80. The current source 80 then directs a combined bias I.sub.bias and OCO current ∓I.sub.OCO to the ICO 62. In the ICO 62, current from the current source 80 is combined with the AC component I.sub.pd(AC) from the photodiode 14 for feedback to the first input port 54 of the differential TIA 50. Thus, an additional counter-offset is provided for the first input of the differential TIA 50.
[0051] In FIG. 10 an embodiment for an optical receiver is shown and generally designated 86 which includes two differential TIAs 50′ and 50″ for the purpose of providing the optical receiver 86 with a broader bandwidth. Specifically, the photodiode 14 is connected to both an ICO 62′ and an ICO 62″. In this combination, the respective input ports 54′ and 54″ of the ICO 62′ and the ICO 62″ are each respectively connected to the differential TIA 50′ or 50″, to counter DC offset issues. Further, an OCO 64′ interconnects the output ports 58′ and 60′ of the differential TIA 50′ with its second input port 56′. Also, an OCO 64″ interconnects the output ports 58″ and 60″ of the differential TIA 50″ with its second input port 56″. Thus, DC offset issues for both differential TIM 50′ and 50″ are suppressed while providing a collectively wider photo receiver bandwidth for the differential summer 88.
[0052] FIG. 11 shows an optical receiver, generally designated 90, which addresses the issues involved when a pair of differential TIM 50′ and 50″ are connected with a traveling wave photodiode 92. As shown, a transmission line 94′ interconnects the photodiode 92 with ICO 62′ while another transmission line 94″ interconnects the photodiode 92 with ICO 62″. In this arrangement, a critical aspect of the optical receiver 90 is that there be an impedance match between the differential TIM 50′ and 50″. Stated differently when there is an impedance Z.sub.0 for photodiode 92, the impedance of the transmission line 94′ Z.sub.t must equal Z.sub.0, and the impedance of the ICO 62′ Z.sub.in must also equal Z.sub.0. Likewise, the impedance of the transmission line 94′ Z.sub.t must equal Z.sub.0, and the impedance of the ICO 62″ Z.sub.in, must also equal Z.sub.0. Stated differently, in both directions from the photodiode 92 there must be matching impedances: Z.sub.0=Z.sub.ti=Z.sub.in.
[0053] While the particular Differential Trans-Impedance Amplifier Receiver Using Counter-Offset Circuitry as herein shown and disclosed in detail is fully capable of obtaining the objects and providing the advantages herein before stated, it is to be understood that it is merely illustrative of the presently preferred embodiments of the invention and that no limitations are intended to the details of construction or design herein shown other than as described in the appended claims.
