Method and device for on-board detection of potential faults in a system fixed onto the board

Abstract

An electronic assembly includes a board and a system mounted to the board. The system includes an impedance matching circuit coupled to a contactless component. A detection circuit operates to carrying out a process for detecting on the board of potential faults in the system mounted to the board. The detection circuit includes a circuit incorporated into the contactless component itself and configured to carrying out a first part of the process for detecting. A processing circuit of the detection circuit performs a second part of the process for detecting based on results of the first part.

Claims

1. A method for on-board detection of potential faults in a system that is mounted onto a board, wherein the system comprises an impedance matching circuit coupled to a contactless communications component, the method comprising: having the contactless communications component itself perform a first detection process part by applying test signals to the impedance matching circuit which generate test results, wherein the first detection process part comprises: first delivering two first test signals in phase opposition to two output terminals of the contactless communications component connected to the impedance matching circuit; receiving two corresponding first receive signals from two input terminals of the contactless communications component connected to the impedance matching circuit; second delivering a second test signal to one of the output terminals; receiving a corresponding second receive signal from one of the input terminals; third delivering a third test signal to another one of the output terminals; and receiving a corresponding third receive signal from another one of the input terminals; and performing a second detection process part by analyzing results obtained from the first detection process part in order to diagnose the potential faults, wherein the second detection process part comprises identifying physical quantities by: determining a differential level of current flowing in the impedance matching circuit, together with a differential amplitude of the two corresponding first receive signals and/or a phase of one of the two corresponding first receive signals; determining an amplitude and/or phase of the corresponding second receive signal; and determining an amplitude and/or phase of the corresponding third receive signal; wherein the analyzing comprises executing a software application implementing at least one decision tree to analyze levels of said physical quantities with respect to reference levels.

2. The method according to claim 1, wherein the potential faults belong to a group comprising potential faults in components of the impedance matching circuit, potential faults in connection of components to the board, and potential faults in connections of the contactless component to the board.

3. The method according to claim 2, wherein, during performing the first detection process part, the impedance matching circuit is coupled to an antenna.

4. The method according to claim 3, wherein the potential faults in the group further comprise potential faults at coupling points of the board with the antenna.

5. The method according to claim 2, wherein the potential faults comprise a fault of one of a short-circuit type or an open-circuit type.

6. The method according to claim 1, wherein the second detection process part is carried out within the contactless communications component.

7. The method according to claim 1, wherein the second detection process part is carried out by a processing unit, wherein the processing unit is also fixed onto the board but is distinct from the contactless communications component.

8. The method according to claim 1, wherein the second detection process part is carried out by a processing unit, wherein the processing unit is in communication with, but not mounted on, the board.

9. The method according to claim 1, wherein the at least one decision tree comprises three decision levels comprising: at a first decision level, first comparing the differential level of current to at least one reference differential level, then at a second decision level, second comparing the differential amplitude and/or phase to a reference differential amplitude and/or a reference phase, respectively, then at a third decision level, determining a difference between the amplitude and/or phase of the corresponding second received signal and the amplitude and/or phase of the corresponding third received signal and third comparing the difference of amplitude and/or phase to a reference difference amplitude and/or phase.

10. The method according to claim 9, wherein the contactless component comprises two additional output terminals connected to one or more damping resistors and further comprising testing to detect potential faults of a short-circuit type on the two additional output terminals.

11. The method according to claim 10, wherein testing comprises: re-executing the first detection process part after having configured the two additional output terminals in high impedance mode, and performing in the second detection process part additional comparisons respectively of the differential level of current, the differential amplitude and/or phase, and the difference of amplitude and/or phase to at least one additional reference differential level, at least one additional reference differential amplitude and/or at least one additional reference phase, and at least one reference difference of amplitude and/or phase.

12. The method according to claim 9, comprising generating reference levels and/or additional reference levels.

13. The method according to claim 1, wherein the contactless communications component is a controller compatible with near-field communications technology.

14. The method according to claim 1, wherein the method is implemented prior to inserting the board into an apparatus designed to support a contactless communications function.

15. The method according to claim 1, wherein the method is implemented within an apparatus designed to support a contactless communications function and equipped with the board.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of embodiments and of their implementation, which are in no way limiting, and from the appended drawings in which:

(2) FIG. 1 illustrates a block diagram of a communications apparatus;

(3) FIG. 2 illustrates circuit details for an impedance matching circuit;

(4) FIG. 3 illustrates a circuit for carrying out a first part of the detection of potential faults;

(5) FIG. 4 is a flow diagram for the process of carrying out the first part of the detection of potential faults;

(6) FIG. 5 illustrates a decision tree for the process for carrying out a second part of the detection of potential faults;

(7) FIG. 6 illustrates details for an analysis for fault detection;

(8) FIG. 7 illustrates a procedure for carrying out the detection of the potential faults;

(9) FIG. 8 illustrates another procedure for carrying out the detection of the potential faults;

(10) FIG. 9 illustrates a further procedure for carrying out the detection of the potential faults.

DETAILED DESCRIPTION

(11) In FIG. 1, the reference APP denotes a communications apparatus, for example a cellular mobile telephone, in particular of the “smartphone” type, or a tablet, equipped with an antenna ANT3 for the establishment of telephone communications.

(12) In the present case, the apparatus also comprises an NFC system comprising a contactless component CTLR, for example an NFC microcontroller, connected to an impedance matching circuit MTC.

(13) This system with the microcontroller CTLR-impedance matching circuit MTC is fixed in a conventional manner known per se, for example by bead solder joints, onto a printed circuit board CD.

(14) Here, the board CD further carries a microprocessor PROC coupled to the microcontroller CTLR.

(15) The board CD also comprises a power supply module ALM designed to power the board, together with a generator GEN that provides a clock signal CLK to a terminal or pin BCK of the microcontroller CTLR.

(16) Aside from this pin BCK, the microcontroller CTLR notably comprises six other terminals or pins CDMP1, RFI1, RFO1, RFO2, RFI2 and CDMP2 whose functions will be described in more detail hereinafter.

(17) These pins are connected to the impedance matching circuit MTC.

(18) Furthermore, an NFC antenna, referenced ANT, is also coupled to the impedance matching circuit MTC via two connection points ANT1, ANT2.

(19) In the example described here, the antenna ANT is the NFC antenna effectively present in the apparatus APP. It may be connected to the board CD by means of specific connections (for example connections known by those skilled in the art under the terminology of “Pogo pin”).

(20) In order to carry out the detection of potential faults in the system CTLR-MTC fixed onto the board CD, it is possible, as shown in FIG. 1, to couple the antenna ANT effectively present in the telephone on the board CD and to carry out this detection of faults within the telephone itself.

(21) As a variant, it is possible to detect potential faults in the system CTLR-MTC installed on the board CD before inserting the board CD into the apparatus APP. In this case, a circuit emulating the characteristics of the future antenna could then advantageously be connected onto the two terminals ANT1, ANT2. This circuit emulating the antenna may, for example, be a resistive inductive capacitive (RLC) circuit.

(22) As illustrated in FIG. 2, in the example described, the microcontroller CTLR has two output terminals RFO1, RFO2 usable in reader mode or for the generation of the active or passive load modulation in card mode and two other terminals RFI1 and RFI2 usable in reader mode and in card mode.

(23) For this purpose, the microcontroller CTRL may be equipped with an internal switch allowing the terminals RFO1 and RFO2 to be short-circuited for an operation in card mode or these terminals RFO1 and RFO2 not to be short-circuited in order to allow an operation in reader mode or during the generation of the active or passive load modulation in card mode.

(24) The external impedance matching circuit MTC is connected between the two coupling points ANT1, ANT2 and the various terminals RFI1, RFO1, RFO2, RFI2, together with the additional terminals CDMP1 and CDMP2.

(25) The structure of such an impedance matching circuit MTC is conventional and known per se.

(26) This impedance matching circuit here comprises a filter designed to filter electromagnetic interference (EMI filter).

(27) This filter is conventionally a filter of the LC type here comprising a coil L1 connected in series between the terminal RFO1 and ground GND with a capacitor CEMI1.

(28) The filter EMI also comprises a coil L2 connected in series between the terminal RFO2 and ground with a capacitor CEMI2.

(29) The impedance matching circuit MTC further comprises two capacitors CS1, CS2 connected in series respectively between the coils L1 and L2 and the coupling points ANT1 and ANT2.

(30) These capacitors are chosen in order to maximize the current in the antenna so as to increase the amplitude of the electromagnetic field.

(31) The impedance matching circuit MTC also comprises two resistors R_RFI1 and R_RFI2 respectively connected between the terminals RFI1 and RFI2 and the nodes common to the coils L1 and L2 and to the capacitors CS1 and CS2.

(32) Two other capacitors C_CDMP1 and C_CDMP2 are respectively connected between the additional output terminals CDMP1 and CDMP2 and the coupling points ANT1 and ANT2.

(33) Another capacitor CP, of lower capacitive value, is connected in parallel with the terminals of the antenna ANT. Similarly, a resistor RP is connected in parallel between the two coupling points ANT1 and ANT2.

(34) The additional output terminals CDMP1 and CDMP2 allow the impedance matching circuit MTC to be connected to resistors referred to as damping resistors, so as to provide damping for the resonant circuit that the component CMP forms with the antenna ANT1 and the external impedance matching circuit MTC in the card mode.

(35) With reference more particularly to FIG. 3, it can be seen that the microcontroller CTLR comprises a first circuit FM1 configured for carrying out a first part of the detection of potential faults.

(36) This first part here comprises the obtaining of measured levels of physical quantities that will be detailed hereinafter.

(37) The first circuit FM1 here comprises a control logic LG receiving the clock signal CLK from the terminal BCK (FIG. 1).

(38) This control logic LG is notably aimed at the generation of test signals which will be delivered on the various output terminals of the microcontroller CTLR connected to the impedance matching circuit MTC via a transmission “driver” circuit DTX.

(39) These test signals, that will be detailed in more detail hereinafter, will give rise to the receipt of corresponding signals on some of the terminals of the microcontroller CTLR and will allow the determination of certain levels of physical quantities by a receiving circuit ARX.

(40) These circuits DTX and ARX have a conventional structure known per se.

(41) Furthermore, the first circuit FM1 here also comprises an LDO (Low Drop Out) voltage regulator receiving a power supply voltage from the power supply ALM and delivering a regulated voltage VDDRF to the driver circuit DTX.

(42) As illustrated very diagrammatically in FIG. 3, the deliveries of test signals by the contactless component CTLR comprise deliveries in differential modes and/or in single-ended input/output mode.

(43) More precisely, in a differential mode, two test signals in phase opposition STST10 and STST11 are respectively delivered on the output terminals RFO1 and RFO2 and this results in the reception on the two input terminals RFI1 and RFI2 of two corresponding received signals STSTR10 and STSTR11.

(44) In a delivery in single-ended input/output mode, a test signal STST2 may be delivered on the output terminal RFO1 and a corresponding received signal STSTR2 may be received on the corresponding input terminal RFI1.

(45) In another single-ended input/output delivery, a test signal STST3 may be delivered on the output terminal RFO2 and the corresponding signal STSTR3 received on the input terminal RFI2.

(46) As illustrated in FIG. 4, this first part S1 of the detection of a potential fault therefore comprises: the delivery in the step S10 of the test signals STST10, STST11, STST2 and STST3 then, in the step S11, the determination from the corresponding received signals of: the differential level I of the current flowing in the impedance matching circuit, the differential amplitude AM of the two received differential signals corresponding to the two test signals transmitted in differential mode, together with amplitudes SE1 and SE2 of the received test signals STSTR2 and STSTR3 respectively corresponding to the two test signals STST2 and STST3 transmitted in single-ended input/output mode.

(47) Then, in a second part S2 of the detection method, an analysis circuit MAL accommodated here in the microprocessor PROC (FIG. 1) analyzes the levels I, AM, SE1, SE2 of the corresponding physical quantities with respect to reference levels IR, AMR, (SE1−SE2)R by notably carrying out comparisons S20 so as to establish a diagnosis.

(48) These reference levels IR, AMR, (SE1−SE2)R are stored in a memory MM.

(49) By way of non-limiting example, the test signals STST10, STST11, STST2 and STST3 are pulses of the order of 100 to 200 microseconds of a carrier signal, for example at 13.56 MHz, having an amplitude of 2.5 volts.

(50) The differential level I of the current flowing in the impedance matching circuit may, for example, be measured very simply by the measurement of the current delivered by the regulator LDO.

(51) As regards the differential amplitudes AM and the amplitudes SE1 and SE2, they are determined in the receiver circuit ARX in a conventional manner.

(52) However, the circuit ARX also allows a phase calculation.

(53) It would accordingly be possible to use phases in place of the differential amplitudes AM and in place of the amplitudes SE1 and SE2.

(54) For this purpose, whether in a differential mode or in a single-ended input/output mode, the phase of a received signal is the phase difference of this received signal with respect to the corresponding transmitted signal.

(55) It would also be possible to use both differential amplitudes AM and phases and both amplitudes SE1 and SE2 and phases.

(56) As illustrated in FIG. 5, in order to carry out the second part S2 of the detection, the analysis circuit, implemented, for example, by software within the microprocessor, implements a decision tree ARB having several decision levels, here three decision levels LV1, LV2 and LV3.

(57) At each level, the analysis circuit carries out comparisons of the various levels of physical quantities obtained in the first part of the detection, with the reference levels IR, AMR, and (SE1−SE2)R.

(58) More precisely, at the first level LV1 of the tree ARB, the differential level of current is compared with four reference differential levels respectively equal to 10, 100, 200 and 300 milliamps.

(59) At the level LV2 of the tree ARB, the analysis circuit MAL compares the differential amplitude AM with three reference differential amplitudes respectively equal to −50, −250 and −400.

(60) It should be noted here that these reference amplitudes correspond to digital levels at the output of analog-to-digital converters used for the measurement of these amplitudes and whose maximum level corresponds for example to −500.

(61) The median value of the output scale of the converter corresponds, for example, to 2 volts.

(62) At the level LV3 of the tree ARB, the analysis circuit first of all generates the difference Delta=SE1−SE2 and compares this difference Delta with two reference amplitudes respectively equal to −10 and +10.

(63) Here again, these reference amplitudes correspond to differences in output levels of the analog-to-digital converter.

(64) At the end of the latter comparison level, various output states are obtained which correspond either to detected faults or, in the present case, to a state DGOK considered as a state without a detectable fault detected at the output of the tree ARB.

(65) More precisely, the letter “O” following the reference of a component or of a terminal corresponds to a fault of the open-circuit type in this component or this terminal.

(66) The letter “S” following the reference of this component or of this terminal corresponds to a fault of the short-circuit type in this component or this terminal. For a component, a short-circuit connects its 2 terminals together. For a terminal, a short-circuit connects it with the ground of the circuit.

(67) More precisely, at the level LV1, if the differential level I is less than or equal to 10 milliamps, then this means that there is an absence of the signal CLK, in other words probably a fault in the terminal BCK of the microcontroller CTLR configured to receive this clock signal CLK.

(68) If the differential level I is higher than 10 milliamps, then it goes to level LV2, to comparisons of the differential amplitude AM with reference differential amplitudes.

(69) Subsequently, depending on the result of these comparisons, various comparisons are carried out of the difference Delta with the reference amplitudes −10 and +10.

(70) Thus, if the differential level I is greater than 10 and less than or equal to 100, and if the differential amplitude AM is higher than or equal to −250 and if the difference Δ is less than −10, then this leads to the conclusion that there is a fault of the open-circuit type in the output terminal RFO2 and/or in the coil L2.

(71) If, on the other hand, during the latter comparison, the difference Delta is greater than 10, then it may be concluded that there is a fault of the open-circuit type in the output terminal RFO1 and/or in the coil L1.

(72) Still in the scenario where the differential level I is higher than 10 and less than or equal to 100, and in the scenario where the differential amplitude AM is in the range between −400 and −250, then a difference Delta less than or equal to 10 and greater than or equal to −10 characterizes a fault of the short-circuit type within the capacitors CS1 and/or CS2 and/or a fault of the open-circuit type at the coupling points ANT1 and/or ANT2 and/or a fault of the short-circuit type at or in the antenna ANT itself.

(73) For the sake of simplification of the description, the other paths of the tree ARB leading to the detection of potential faults will not be described in more detail, FIG. 5 being explicit in itself for this purpose.

(74) On the other hand, it can be seen that the tree ARB comprises a path CH ending up at the state DGOK.

(75) This path CH is followed when the differential level of current I is higher than 200 and less than or equal to 300 milliamps, when the differential amplitude AM is in the range between −400 and −250 and when the difference Delta is less than or equal to 10 and higher than or equal to −10.

(76) The state DGOK is representative of the absence of any fault detected in the majority of the components and of the terminals of the NFC microcontroller-impedance matching circuit system and is also representative of potential, but undetectable, faults of the short-circuit type at or in the resistors R_RFI1, R_RFI2, at or in the auxiliary terminals CDMP1 and CDMP2, between these two terminals (such a short-circuit between the two terminals CDMP1 and CDMP2 being referenced CDMP S), and also including a fault of the open-circuit type at or in the capacitor CP.

(77) Although it is possible to halt the analysis at the output of the tree ARB, because the majority of the potential faults have been detected, it is possible, if desired, to continue with the analysis once the state DGOK has been reached.

(78) In this case, as illustrated in FIG. 6, the analysis comprises a second step S22 in which the two terminals CDMP are placed in high impedance mode (step S60) and the first part of the detection is re-executed, in other words the test signals which have previously been used are again delivered.

(79) The levels I, AM, SE1 and SE2 are then re-measured.

(80) The analysis circuit then proceeds, in the step S61, to a series of comparisons, as illustrated in FIG. 6. These comparisons are aimed at comparing the measured levels I, AM, SE1 and SE2 with additional reference levels, also stored in the memory MM.

(81) More precisely, if the differential level I is higher than 240 milliamps, and if the differential amplitude AM is less than −400 and if the difference SE1−SE2 is positive, then this is representative of a short-circuit fault at or in the additional terminal CDMP1.

(82) If the differential level is higher than 240 milliamps, the differential amplitude lower than −400 and the difference SE1−SE2 is negative, then there is a fault of short-circuit at or in the terminal CDMP2.

(83) If the level I is higher than 240 milliamps and the differential amplitude higher than −400, then there is a fault of the short-circuit type CDMP S between the two additional terminals CDMP1 and CDMP2.

(84) If, on the other hand, the level I is lower than or equal to 240 milliamps and the differential amplitude AM is less than or equal to −400, then this corresponds to a state DGOK2 representative of the absence of any detected fault with the proviso that a fault of the short-circuit type at or within the resistors R_RFI1 and R_RFI2 is not detectable just like a fault of the open-circuit type at or in the capacitor CP.

(85) In this case, and if the system is still defective, then other investigations using other conventional means may be undertaken with regard to these resistors and this capacitor CP.

(86) As indicated hereinbefore and as illustrated in FIG. 7, it is possible to carry out the detection of the potential faults (parts S1 and S2) by coupling the board CD to an antenna emulating the future antenna, before inserting the board CD into the apparatus APP (step S70).

(87) As a variant, as illustrated in FIG. 8, it is possible to carry out the detection of the potential faults (parts S1 and S2) when the board CD is inserted into the apparatus APP and coupled to the antenna, for example for a customer return when a fault has been observed.

(88) As illustrated diagrammatically in FIG. 9, the various reference levels IR, AMR, (SE1−SE2)R and/or the various additional reference levels may for example have been generated during a preliminary part SPR.

(89) This preliminary part SPR uses the same values of test signals as those used in the first part S1 of the detection. It may, for example, comprise simulations and/or intentional creations of faults in the impedance matching circuit. This preliminary part may also be carried out on several boards equipped with impedance matching circuits in order to take into account potential variations in the methods of fabrication, and to subsequently apply averages of the various reference levels obtained from these various boards.