Method for diagnosing a bias supply for an acquiring system comprising a matrix-array interface device

Abstract

A method for diagnosing a bias power supply for an acquisition system including a matrix-array interface device having conductive rows and columns, each row being connected to an input port and to a bias power supply, each column being selectively connected to ground by controlling an output port, and at each intersection either a circuit or a shunt, connected between the intersected row and the intersected column, including the following steps: controlling an output port so as to ground a shunt, reading the input port corresponding to the shunt, a low state indicating a normal presence of the power supply, a high state indicating an abnormal absence.

Claims

1. A method for diagnosing a bias power supply for an acquisition system comprising a processing unit and a matrix-array interface device comprising a first number of conductive rows, a second number of conductive columns, each row being connected to an input port of the processing unit and to a bias power supply, each column being selectively connected to ground by controlling an output port of the processing unit, each row intersecting a respective one of each column to form a plurality of intersections, a respective circuit of a plurality of circuits at each of the plurality of intersections, one terminal of each respective circuit is connected to the intersected row and another terminal of each respective circuit is connected to the intersected column, and a respective shunt of a plurality of shunts connecting the intersected row and the intersected column, so as to have one shunt per row and per column, the method comprising: controlling an output port so as to ground a selected column of the columns via a selected shunt of the plurality of shunts; and reading the input port corresponding to said selected shunt: a low state reading at the input port indicating a normal presence of the power supply associated with the row including the selected shunt, and a high state reading at the input port indicating an abnormal absence of the power supply.

2. The method as claimed in claim 1, further comprising: stopping the control of said output port, and reading the input port corresponding to said selected shunt, a low state indicating an abnormal presence of the power supply associated with the row including the selected shunt, a high state indicating a normal absence.

3. The method as claimed in claim 1, wherein the controlling and reading steps are repeated for each of the columns.

4. The method as claimed in claim 1, wherein at least two rows of the rows are connected to one and the same power supply, and the method also comprises comparing the readings of the input port corresponding to one of the two rows and the readings of the input port corresponding to the other of the two rows, a match indicating normal operation of the power supply, a mismatch indicating short-circuiting of the power supply.

5. The method as claimed in claim 1, wherein each respective circuit and each respective shunt is connected to its column via a diode oriented so as to prevent a current from flowing from ground.

6. The method as claimed in claim 1, wherein each row is connected to its input port via a resistor.

7. The method as claimed in claim 1, wherein each power supply is connected to its row via a resistor.

8. The method as claimed in claim 1, wherein each column is selectively connected to ground via a transistor controlled by an associated output port.

9. The method as claimed in claim 2, wherein the stopping and reading steps are repeated for each of the columns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The detailed description is given with reference to the drawings, in which:

(2) The FIGURE illustrates the interface between a plurality of circuits to be acquired and a processing unit via a 5×5 matrix-array device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(3) Other features, details and advantages of aspects of the invention will become more clearly apparent from the detailed description below.

(4) It is possible to perform a diagnosis that checks the presence and the correct operation of a bias power supply Ak for such an acquisition system comprising a processing unit U and a matrix-array device M.

(5) To this end, the input port Ink corresponding to a shunt Skl is read. If, as is the case in one advantageous configuration of the matrix-array device M, a shunt Skl is present on the row k, it is necessarily a single shunt and it is positioned on a column that will be denoted as the Ith one, that is to say Coll.

(6) Therefore, if the Ith output port Outl is controlled during reading of the input port Ink corresponding to the shunt Skl, the shunt Skl is grounded via its column Coll and connected to the power supply Ak via its row Ligk. Therefore, if the power supply Ak is normally present, the input port Ink should see a low state. If a high state is seen, it is indicative of a fault, and indicates an absence of the power supply Ak.

(7) This may be performed for each of the shunts Sij, and thus provide a diagnosis of the presence of each of the power supplies Ai connected to a row Ligi comprising a shunt Sij.

(8) Additionally, after stopping the control of said output port Outl, the input port Ink corresponding to a shunt Skl may be read. For this reading, a high state indicates a presence of the power supply Ak associated with the row Ligk including the shunt Skl, and therefore a fault possibly being linked to a short circuit, whereas, by contrast, a low state indicates a normal absence of said power supply Ak.

(9) The acquisition method according to the prior art, as described above, performs the acquisitions in series for the input ports Ini, when an output port Outl is controlled. However, according to the prior art, the acquisition of the input port Ink corresponding to a shunt Skl, since it does not correspond to a circuit Cij, was either not performed or unused.

(10) It may be noted that the acquisition method, as described above, controls and then stops each of the output ports Outj in sequence, one at a time. Therefore, according to one advantageous embodiment, this control and stoppage of the output ports Outj may be exploited by reusing them for the diagnostic method by inserting the readings of the input ports Ink corresponding to a shunt Skl, the diagnostic method then benefiting from the times at which an output port Outk is either controlled or not controlled.

(11) Therefore, during the acquisitions performed in series for the input ports Ini when the output port Outl is controlled, the acquisition of the input port Ink corresponding to the shunt Skl, which, since it does not correspond to a circuit Cij, was either not performed or unused before, becomes relevant according to the invention in that it allows a diagnosis of the presence of the corresponding power supply Ak.

(12) Thus, when a column Coll is connected to ground G, the reading of the input port Ink corresponding to a shunt Skl may advantageously be performed at the same time as the reading of the other input ports Ini, for i=1 . . . k−1, k+1 . . . n corresponding to a circuit Cil, for i=1 . . . k−1, k+1 . . . n.

(13) Therefore, the acquisitions may be performed for all of the input ports Ini, for i=1 . . . n, which may be advantageous on certain processing units U that prefer grouped readings.

(14) Reading of the input port Ink corresponding to a shunt Skl when the corresponding column Coll is not connected to ground G should be performed at another time, typically during the acquisition of another column.

(15) According to one common embodiment, one and the same power supply Ai may be used to bias several rows Ligi. There is thus no particular need for separation, and one and the same power supply Ak may bias all of the rows Ligi. As an alternative, one common embodiment consists in using a first power supply for biasing the circuits Cij that are able to awake the processing unit U and a second power supply for biasing the circuits Cij that do not awake the processing unit U. The circuits Cij are then grouped together on one and the same row Ligi, according to their type in relation to the awakening operation. Given the number of circuits, there are more often than not at least two rows for each of the two power supplies.

(16) Provided that one and the same power supply Ak is used to bias at least two rows Ligk1, Ligk2 of the matrix-array device M, it is possible to add another diagnosis of this common power supply Ak. Specifically, the above diagnostic test or tests may be performed for the first row Ligk1. The reading of the input port Ink1 associated with the row Ligk should normally indicate a low state when the column l comprising a shunt Sk1l for said row Ligk1 is grounded G, and a high state if not. Likewise, the reading of the input port Ink2 associated with the row Ligk2 should normally indicate a low state when the column l comprising a shunt Sk2l for said row Ligk2 is grounded G, and a high state if not. The two rows Ligk1 and Ligk2 connected to one and the same power supply Ak should match in that they have comparable states depending on the controls of their associated output port Outl. If such a match is present, it may be considered that the power supply Ak is operating normally. If a mismatch is detected, the power supply exhibits faulty operation, probably linked to a short circuit in relation to one or the other of the rows Ligk1, Ligk2, typically at ground G.

(17) To protect the output ports Outj, the matrix-array device M comprises, for each circuit Cij or shunt Sij, a diode d positioned between said circuit Cij or said shunt Sij and its associated column Colj. Said diode d is oriented so as to prevent a current from flowing from ground G. This is illustrated the FIGURE.

(18) According to another feature, each row Ligi, for i=1 . . . n, is connected to its input port Ini, for i=1 . . . n, via a first resistor Rai, for i=1 . . . n. This is illustrated in the FIGURE.

(19) According to another feature, each power supply Ai, for i=1 . . . n, is connected to its row Ligi, for i=1 . . . n, via a second resistor Rbi, for i=1 . . . n. This is illustrated in the FIGURE.

(20) The connection of a column Colj, for j=1 . . . m, may be selectively connected to ground G by way of a transistor Tj, for j=1 . . . m. This transistor Tj is controlled by the associated output port Outj, for j=1 . . . m. This is illustrated in the FIGURE.