Transistor comprising a lengthened gate

Abstract

A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

Claims

1. A process, comprising: producing a metal oxide semiconductor (MOS) transistor on and in an active zone of an integrated circuit, wherein producing comprises: depositing a layer of gate material over said active zone; defining a first mask over the layer of gate material, said first mask having a first length dimension in a source-drain direction corresponding to a central zone of a conductive gate region for said MOS transistor; performing a first etch of the layer of gate material using the first mask to define a length of the central zone, wherein the first etch leaves behind a residual portion of the gate material that extends from a foot of the central zone; defining a second mask on a top and sides of the central zone and on a part of the residual portion, said second mask having a second length dimension in the source-drain direction corresponding to the central zone and at least one stair that extends from the foot of the central zone; and performing a second etch of the layer of gate material using the second mask to define a length of the at least one stair that extends from the foot of the central zone.

2. The process of claim 1, wherein performing the second etch comprises: performing an etch of the residual portion of the gate material to define a top stair and leave behind a further residual portion of the gate material; and performing an etch of the further residual portion of the gate material to define a bottom stair.

3. The process of claim 2, wherein the central zone has a first height, the top stair has a second height and the bottom stair has a third height, said first height being greater than the second height and the second height being greater than the third height.

4. The process of claim 1, further comprising forming lateral insulating spacers which cover sides and a top surface of said at least one stair, and which cover sides of the central zone, but which do not cover a top surface of the central zone.

5. The process of claim 1, wherein the active zone of an integrated circuit is surrounded by an insulating region, and wherein forming the conductive gate region further comprises defining the conductive gate region to extend to cover at least part of the insulating region.

6. The process according to claim 1, further comprising: performing a first dopant implant into the active zone using the central zone and the at least one stair as an implant mask; then forming an insulating lateral spacer that covers sides of the central zone and sides and a top surface of the at least one stair, but does not cover a top of the central zone; and then performing a second dopant implant into the active zone using the insulating spacer as an implant mask.

7. A process, comprising: producing a metal oxide semiconductor (MOS) transistor on and in an active zone of an integrated circuit, wherein producing comprises: depositing a layer of gate material over said active zone; defining a first mask over the layer of gate material, said first mask having a first length dimension in a source-drain direction corresponding to a central zone of a conductive gate region for said MOS transistor; performing a first etch of the layer of gate material using the first mask to define a length of the central zone, wherein the first etch leaves behind a residual portion of the gate material that extends in the source-drain direction from a foot of the central zone; defining a second mask on a top and sides of the central zone and on a part of the residual portion, said second mask having a second length dimension in the source-drain direction corresponding to the central zone and an upper stair that extends from the foot of the central zone; performing a second etch of the layer of gate material using the second mask to define a length of the upper stair that extends from the central zone, wherein the second etch leaves behind a further portion of the gate material that extends in the source-drain direction from the upper stair; defining a third mask over a top and sides of the central zone, the upper stair and on the further portion, said third mask having a third length dimension corresponding to the central zone, the upper stair and a lower stair that extends in the source-drain direction from the foot of the central zone; performing a third etch of the layer of gate material using the third mask to define a length of the lower stair that extends from the upper stair.

8. The process of claim 7, wherein the central zone has a first height, the top stair has a second height and the bottom stair has a third height, said first height being greater than the second height and the second height being greater than the third height.

9. The process of claim 7, further comprising forming lateral insulating spacers which cover sides and a top surface of said at least one stair, and which cover sides of the central zone, but which do not cover a top surface of the central zone.

10. The process of claim 7, wherein the active zone of an integrated circuit is surrounded by an insulating region, and wherein forming the conductive gate region further comprises defining the conductive gate region to extend to cover at least part of the insulating region.

11. The process according to claim 7, further comprising: performing a first dopant implant into the active zone using the central zone and the upper and lower stairs as an implant mask; then forming an insulating lateral spacer that covers sides of the central zone and sides and a top surface of the upper and lower stairs, but does not cover a top of the central zone; and then performing a second dopant implant into the active zone using the insulating spacer as an implant mask.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting embodiments and the appended drawings, in which:

(2) FIG. 1 illustrates an integrated circuit comprising a MOS transistor according to the prior art;

(3) FIGS. 2-3 show an example of one embodiment of an integrated circuit comprising a MOS transistor;

(4) FIGS. 4-6 illustrate various stair configurations for the gate;

(5) FIG. 7-13 illustrate process steps for fabricating a transistor;

(6) FIGS. 14-15 illustrate doping profiles for MOS transistors.

DETAILED DESCRIPTION

(7) Reference is now made to FIGS. 2-3 which show an example of one embodiment of an integrated circuit comprising a MOS transistor.

(8) FIG. 3 is a cross-sectional view of the integrated circuit CI of FIG. 2, taken along the section line A-A.

(9) The integrated circuit CI comprises a MOS transistor T1 produced on and in an active zone ZA that is surrounded by an isolating region 10, for example of the shallow trench isolation (STI) type.

(10) The active zone ZA includes a doped drain region 11 and a doped source region 13 that are separated by a channel region 12, all thereof being produced in a semiconductor substrate SB.

(11) The substrate SB may be a bulk substrate or indeed a semiconductor well, or even a semiconductor film of a silicon-on-insulator (SOI) substrate.

(12) In the case of an nMOS transistor, the source and drain regions are n-doped. The source and drain regions are instead p-doped for a pMOS transistor.

(13) Conventionally, the source and drain regions are silicided in order to allow contacts CTS, CTD to be formed.

(14) The references 110 and 130 designate the silicided portions of the drain and source regions 11, 13.

(15) The transistor T1 also includes a gate region 14, which is insulated from the active zone by a dielectric layer 15, including a central zone 16 having a width W and a length L.

(16) This length L is advantageously equal to the length L of a gate of a conventional transistor produced in an L-nm technology relating to the process node dimension.

(17) L is for example equal to 40 nm.

(18) The gate region 14 also includes an extension 160 that protrudes beyond the active zone ZA and rests on the isolating region 10 in order to allow a contact to be made to the gate region 14. With this in mind, the extension 160, and in practice all of the gate region 14, is silicided.

(19) The gate region 14 includes, at its foot (also referred to herein as the base portion or bottom portion that is adjacent the gate insulating layer), on both sides, i.e. on the drain side and on the source side, a stair (also referred to herein as a step or protrusion) 17 that has a width L17 and a height h.

(20) Each stair 17 extends at least the entire width W of the active zone and in practice may protrude onto the peripheral isolating region 10 in order to extend the entire width of the gate region 14 (central zone 16 and extension 160) for the sake of simplification of the gate etching mask.

(21) The gate region 14 includes flanks FLA and FLB on which insulating lateral regions or spacers 18 completely cover sides and a top surface of each stair 17.

(22) As will be seen in detail below, these stairs 17 will allow, during the doping of the drain and source regions, the doping profile of these regions to be modified and thus the electrical characteristics of the transistor T1, in particular its threshold voltage and the ratio Ion/Ioff of on-state current to leakage current, to be modified because the stair 17 forms an additional thickness for the dopants to pass through.

(23) Advantageously, a modification of certain electrical parameters of the transistor T1 is obtained whatever the values of h and L17. It is within the ability of a person skilled in the art to adjust the values of h and L17 depending on the modifications desired for the parameters in question.

(24) Preferably, the stair 17 has a length L17 larger than the roughness of the flanks FLA, FLV of the gate region 14, this making it possible to obtain a stair of uniform length L17 that is distinguishable from the intrinsic roughness of the gate material. For example, for a gate length L of 40 nm, the roughness is about 3 nm.

(25) The inventors have observed that it is preferable for the height h to be larger than 3 nm, for example for h to be equal to 10 nm, and for L17 to be equal to 15 nm, for a 40 nm technology.

(26) Although in the embodiment illustrated in FIGS. 2 and 3 the stairs 17 shown lie on both sides of the gate region 14, it is possible, as illustrated in FIG. 4, to make provision to produce only a single stair 17 on only one side.

(27) This single stair 17 then preferably lies on the side of the region of the drain 11. Specifically, the drain region 11 is by convention biased differently from ground and it is therefore drain-side that the drain/substrate junction has a significant electrical impact under normal operating conditions.

(28) It is also possible, as illustrated in FIG. 5, to produce a plurality of stairs so as to form a staircase, preferably on the side of the drain region 11, or even to produce a staircase on each side of the gate region 14 as illustrated in FIG. 6.

(29) In the case of a staircase, all the stairs of the staircase may have identical dimensions (i.e. parameters L17 and h that are identical) or indeed some thereof at least may have different dimensions.

(30) An example of a process for fabricating a MOS transistor produced on and in an active zone and having a gate comprising on both sides, at its foot, a stair is now described. For example, the length L of the central gate zone of the MOS transistor is 40 nm and the stair has a length L17 of 15 nm and a height h of 3 nm. The gate is here made of polysilicon.

(31) The critical dimension CD of the transistor is here equal to 40 nm. This transistor technology is still used, and the doping masks used in the fabrication of these transistors are the same as those of conventional transistors conventionally produced in this technology.

(32) Elements that are identical to those described above have been identified by the same reference numbers.

(33) FIG. 7 illustrates a first step in which a first etch of a resist layer for a CD equal to 40 nm is carried out.

(34) More precisely, on the substrate SB a silicon-dioxide layer 20, surmounted by a polysilicon layer 21, itself surmounted with a hard-masking layer 22, which is surmounted with a resist layer 23, is formed in a conventional and known way. The resist 23 is etched by photolithography using an etching mask of CD equal to 40 nm, so as to leave behind only a resist block 230.

(35) The polysilicon layer 21 here has a height H of 80 nm.

(36) In a second step, which is illustrated in FIG. 8, a first conventional etch GR1 is carried out using the resist block 230 as etching mask. The polysilicon layer 21 is etched in the plasma and in time so as to leave behind, at the foot of the central zone 16 and optionally of the extension 160, a layer 170 of polysilicon of height h.

(37) Next in step 3, which is illustrated in FIG. 9, a second resist mask MSK2 having a length CD2 of 70 nm is produced in a conventional way. The resist mask MSK2 protrudes on each side from the central zone 16 of the gate and by a length L17 here equal to 15 nm, which will define the length of the stair.

(38) In step 4, which is illustrated in FIG. 10, a selective plasma etch GR2 is carried out. The gate 14 comprising the central zone 16 of height equal to H minus h and the stair 17 of height h and of length L17 are obtained.

(39) It will be noted that any suitable number of etch steps can be performed to define the central zone 16 and the one or more included steps. For example, for the structure of FIGS. 5 and 6, the first etch GR1 is performed to define central zone 16 and leave sufficient residual gate material to support formation of the steps 17. The steps may then be formed using two successive second etches GR2, using two distinct masks, with the first one of the second etches GR2 defining the top step and leaving sufficient residual gate material to support formation of the bottom step and with the second one of the second etches GR2 delimiting the bottom step.

(40) In step 5 of the process, which is illustrated in FIG. 11, a silicon-dioxide layer 24 is deposited on the gate 14 and the surface of the substrate SB, followed by a first implantation IMP1 of dopants, so as to obtain implanted regions 11a and 13a on both sides of the channel region 12 (FIG. 12).

(41) In step 6, the spacers 18 are produced in a conventional way. They in particular cover the stairs 17.

(42) In step 7, as illustrated in FIG. 13, a second implantation IMP2 of dopants is carried out so as to obtain the transistor T1 as illustrated in FIG. 14 with a dopant profile PFI that is different from a conventional dopant profile PFC such as that illustrated in FIG. 15.

(43) The references 110 and 130 designate the silicided portions of the drain and source regions 11, 13.

(44) It will be noted that under the stairs 17 the dopant profile PFI is different from the conventional profile PFC.

(45) Under the stairs 17 the dopant profile PFI extends less deeply than the conventional profile PFC.

(46) By way of example, for L equal to 40 nm and a stair on either side of the gate region of L17 equal to 15 nm and h equal to 3 nm, the threshold voltage of the transistor is increased by 100 mV, and the Ion/Ioff ratio is higher than 5.

(47) Advantageously, the one or more stairs on one side or on both sides of the foot of the gate modify the distribution of the dopants implanted in the gate, drain and source regions in the doping step of the fabricating process of the transistors.

(48) This modification of the doping profile leads to a modification of the electrical properties of the transistor T1, in particular its threshold voltage Vt and the ratio Ion/off of on-state current to leakage current. The Ion/Ioff ratio is improved.

(49) Moreover, an increase in the Ion to Ioff ratio is obtained. This is particularly advantageous for ultra-low-power (ULP) applications.

(50) These improvements lead to the creation of only a single additional gate etching mask and to the addition of two steps to the process for fabricating the transistor, no modification of the conventional steps of MOS transistor fabrication being required. In addition, the critical dimension CD of the transistor is preserved, and the doping masks used in conventional transistor fabrication steps are also preserved. In addition, stairs may be produced in the two types of MOS transistors (pMOS and nMOS) with a single mask. In other words, the threshold voltage of pMOS and nMOS transistors may be modified with a single mask.