Stacked high-blocking III-V power semiconductor diode

Abstract

A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p− layer, an n− region with a layer thickness of 10 μm-150 μm, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p− layer, the n− region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n− region within the seed opening is integrally bonded to the p− layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

Claims

1. A stacked high-blocking III-V power semiconductor diode comprising: a p+ substrate layer with a top side and a bottom side and comprising a GaAs compound or consisting of GaAs; a p− layer with a top side and a bottom side and comprising a GaAs compound or consisting of GaAs; an n− region with a top side, a bottom side, a layer thickness of 10 μm-150 μm and comprising a GaAs compound or consisting of GaAs; an n+ layer with a top side and a bottom side and comprising a GaAs compound or consisting of GaAs; a first metallic contact layer and a second metallic contact layer, the first metallic contact layer being integrally bonded to the bottom side of the p+ substrate layer, the second metallic contact layer being integrally bonded to the top side of the n+ layer, a hard mask layer with a top side, a bottom side, and at least one seed opening, the bottom side of the hard mask layer being integrally bonded to the top side of the p+ substrate layer or integrally bonded to the top side of the p− layer, wherein the n− region extends over an edge region, adjacent to the seed opening of the top side of the hard mask layer and above or within the seed opening, and wherein the n− region is arranged within the seed opening and arranged in the edge region on the top side of the hard mask layer.

2. A stacked high-blocking III-V power semiconductor diode comprising: an n+ substrate layer with a top side and a bottom side and comprising a GaAs compound or consisting of GaAs; an n− region with a top side, a bottom side, a layer thickness of 10 μm-150 μm and comprising a GaAs compound or consisting of GaAs; a p− layer with a top side and a bottom side and comprising a GaAs compound or consisting of GaAs; a p+ layer with a top side and a bottom side and comprising a GaAs compound; a first metallic contact layer and a second metallic contact layer, the first metallic contact layer being integrally bonded to the bottom side of the n+ substrate layer, the bottom side of the n− region being arranged above the top side of the n+ substrate layer, the second metallic contact layer being integrally bonded to the top side of the p+ layer; and a hard mask layer with a top side, a bottom side, and at least one seed opening, the bottom side of the hard mask layer being integrally bonded to the top side of the n+ layer, wherein the n− region extends within the seed opening and over an edge region adjacent to the seed opening of the top side of the hard mask layer, and wherein the n− region within the seed opening is integrally bonded to the top side of the n+ substrate layer and in the edge region of the top side of the hard mask to the hard mask layer.

3. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the p+ substrate layer has a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 cm.sup.−3 and a layer thickness of 5 μm-300 μm.

4. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the n+ layer has a dopant concentration of at least 1.Math.10.sup.18 cm.sup.−3 and a layer thickness of less than 30 μm.

5. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the n+ layer covers the n− region completely or at least up to 95% and the second metallic contact layer covers the n+ layer completely or at least up to 10%.

6. The stacked high-blocking III-V power semiconductor diode according to claim 2, wherein the n+ substrate layer has a dopant concentration of at least 1.Math.10.sup.18 cm.sup.−3 and a layer thickness of 5 μm-300 μm.

7. The stacked high-blocking III-V power semiconductor diode according to claim 2, wherein the p+ layer has a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 cm.sup.−3 and a layer thickness of less than 30 μm.

8. The stacked high-blocking III-V power semiconductor diode according to claim 2, wherein the p+ layer covers the n− region completely or at least up to 95% and the second metallic contact layer covers the p+ layer completely or at least up to 95%.

9. The stacked high-blocking III-V power semiconductor diode according to claim 2, wherein the n− region above the hard mask layer has a first diameter and the seed opening has a second diameter, wherein the first diameter is larger than the second diameter by at least a factor of 1.5.

10. The stacked high-blocking III-V power semiconductor diode according to claim 2, wherein the seed opening is formed rectangular and has a width and a length.

11. The stacked high-blocking III-V power semiconductor diode according to claim 6, wherein the width of the seed opening runs parallel to the direction <011> or <001> or <111> or at an angle of 15° or 30° to the direction <011> or to the direction <001> or to the direction <111> of the substrate layer.

12. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the top side of the substrate layer is formed as a GaAs.

13. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein at least one of the p-doped layers comprises zinc.

14. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the n-doped layer comprises silicon and/or chromium and/or palladium and/or tin.

15. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein, apart from the substrate layer, all layers of the stacked III-V semiconductor diode are produced epitaxially on the respective preceding layer.

16. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the hard mask layer is formed of SiO2 and/or Si3N4.

17. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the hard mask layer has a layer thickness of 0.1 μm-5 μm.

18. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein a trace is arranged on the top side of the hard mask layer and the trace is connected to the second metallic contact layer.

19. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the p− layer has a dopant concentration of 1.Math.10.sup.14-1.Math.10.sup.17 cm.sup.−3 and a layer thickness of 1 μm-20 μm.

20. The stacked high-blocking III-V power semiconductor diode according to claim 1, wherein the n− region has a dopant concentration of 8.Math.10.sup.13-1.Math.10.sup.16 cm.sup.−3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a layer view of an exemplary embodiment of a stacked III-V semiconductor diode;

(3) FIG. 2 shows a sectional view of an exemplary embodiment of a stacked III-V semiconductor diode;

(4) FIG. 3 shows a sectional view of an exemplary embodiment of a stacked III-V semiconductor diode; and

(5) FIGS. 4a to 4c show sectional views of metallization variants of the stacked III-V semiconductor diode according to the exemplary embodiments shown in connection with FIGS. 1 to 3.

DETAILED DESCRIPTION

(6) For reasons of clarity, only a sectional view or cross-sectional view of a III-V semiconductor diode 10 is shown in all figures. It should be noted, however, that all III-V semiconductor diodes 10 shown in the sectional view have either a square or a rectangular or a round perimeter in a plan view.

(7) In other words, in the plan view the III-V semiconductor diodes have the same layer sequences as in the respective cross-sectional view. Furthermore, it applies to all of the illustrated embodiments that III-V semiconductor diode 10 has a top side and a bottom side, wherein the III-V semiconductor diodes are arranged as a so-called “DIE” on a pad as a metal frame or metal carrier, also called a “lead frame,” preferably by means of a metallic connecting contact layer formed on the bottom side. The largest possible, in particular full-surface formation of the metallic connection contact layer improves the thermal coupling to the pad.

(8) Furthermore, it should be noted that, starting from the bottom side of the III-V semiconductor diode, all of the semiconductor layers formed are planar.

(9) It should also be noted that a substrate layer, i.e., either a p+ substrate layer or an n+ substrate layer, is formed on the bottom side of the III-V semiconductor diodes in all embodiments shown. It is understood that the substrate layer in the initial state has a thickness between 400 μm and 700 μm, depending on the size of the initial semiconductor substrate wafer. In other words, a 3-inch semiconductor substrate wafer generally has a smaller thickness than a 6-inch semiconductor substrate wafer.

(10) In order to reduce the series resistance in the forward direction, the semiconductor substrate wafer is thinned before the formation of the metallic connection contact layer, wherein, for reasons of mechanical stability, the residual thickness is preferably in a range between 80 μm and 200 μm or preferably in a range between 120 μm and 150 μm.

(11) The illustration in FIG. 1 shows a first embodiment of stacked III-V semiconductor diode 10 with an n-on-p structure. Here, the n-doped semiconductor layers are formed above the p-doped semiconductor layers.

(12) A p− layer 14 with a layer thickness D14 is arranged over the entire surface on a top side of a p+ substrate layer 12 with a layer thickness D12. A hard mask layer 16 with a layer thickness D16 and a seed opening 18 with a width D18 and a length (not shown) (in or out of the image plane) is arranged on a top side of p− layer 14.

(13) An n− region 20 with a height D20 is arranged within seed opening 18 on the top side of p− layer 14, wherein n− region 20 also extends over an edge region 22, adjacent to the seed opening, of a top side of hard mask layer 18 [sic, should be 16]. It is understood that edge region 22 extends around seed opening 18, and n− region 20 extends in all directions beyond seed opening 18 over part of the top side of hard mask layer 16.

(14) A surface, adjoining hard mask layer 16, of n− region 20 is covered or enclosed by an n+ layer 22 with a layer thickness D22. The n+ layer 22 is in turn completely covered or enclosed by a second metallic contact layer 24 with a layer thickness D24.

(15) A first metallic contact layer 26 with a layer thickness D26 is formed flat on a bottom side of p+ substrate layer 12. Metallic contact layer 26 preferably covers the bottom side of p+ substrate layer 12 over the entire area or at least up to more than 90% of the area. This improves the heat dissipation at high current loads.

(16) A trace 28 is arranged peripherally around seed opening 18 and at a distance from seed opening 18 and second metallic contact layer 24, wherein trace 28 is electrically operatively connected to second metallic contact layer 24 via at least one contact wire 30. For this purpose, a bonding surface 32 for the connection of contact wire 30 is formed on trace 28 and on the second contact layer.

(17) A second embodiment of semiconductor diode 10 is shown in the illustration of FIG. 2. Only the differences from the illustration in FIG. 1 will be explained below.

(18) The p− layer 14 of semiconductor diode 10 extends only over the region of the top side of p+ substrate layer 12, the region which is recessed from hard mask layer 16. The n− layer 14 is therefore formed within seed opening 18.

(19) A third embodiment is shown in the illustration of FIG. 3. Only the differences from the illustration in FIG. 1 will be explained below.

(20) Stacked III-V semiconductor diode 10 has a p-on-n structure; i.e., n+ layer 22 is formed as n+ substrate layer 22 with a layer thickness D22, and hard mask layer 16 with a layer thickness D16 is arranged on the top side of n+ substrate layer 22.

(21) The p− layer 14 with layer thickness D14 covers the top side of n− region 20, followed by p+ layer 12 with layer thickness D12 and second metallic contact layer 24 with layer thickness D24.

(22) An advantage of implementing the p-on-n structure is that the electrical properties of III-V semiconductor diode 10 improve in that the electrical resistance of the n+ layer is lower at least by a factor of 5 to a factor of 10 than that of the p+ layer. In particular, the effect can be attributed to the large differences in the effective mass of the holes compared with the electrons.

(23) FIGS. 4a-c each show sectional views of a total of three different designs of second contact layer 24 of stack-shaped III-V semiconductor diode 10. For reasons of clarity, only part of the semiconductor layers are shown in each case. A semiconductor contact layer HLK with a top side and a bottom side is formed to represent the n+ layer or the p+ layer.

(24) The top side of the semiconductor contact layer HLK is integrally bonded to second metallic contact layer 24 in all three designs.

(25) At least one bonding surface 32 is formed on the top side of second contact layer 24. A contact wire, which is also referred to as a bonding wire, can be attached to the bonding surfaces (not shown).

(26) In the embodiment of FIG. 4a, second contact layer 24 not only completely surrounds semiconductor contact layer HLK in a first region but is also formed in an encircling manner in a second region on the top side of hard mask layer 16. In the second region, two bonding surfaces 32 are formed on the top side of second contact layer 24. A contact wire, which is also referred to as a bonding wire, can be attached to the bonding surfaces (not shown).

(27) In the embodiment in FIG. 4b, second contact layer 24 encloses the semiconductor contact layer HLK in a first region. Bonding surface 32 is formed on the top side of second contact layer 24.

(28) In the embodiment of FIG. 4c, second contact layer 24 is formed in a first region only on the cover surface of the semiconductor contact layer HLK; i.e., second contact layer 24 is not formed on the side surfaces of the semiconductor contact layer HLK. Bonding surface 32 is formed on the top side of second contact layer 24 formed on the cover surface.

(29) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.