POWER MANAGEMENT CIRCUIT OPERABLE TO ADJUST VOLTAGE WITHIN A DEFINED INTERVAL(S)

Abstract

A power management circuit operable to adjust voltage within a defined interval(s) is provided. The power management circuit is configured to generate a time-variant voltage for amplifying an analog signal based on a target voltage. In embodiments disclosed herein, the power management circuit can be configured to generate a lower initial target voltage at a start of the defined interval(s), such as during a cyclic prefix (CP) of an orthogonal frequency division multiplexing (OFDM) symbol, and dynamically adjust the initial target voltage, if necessary, within the defined interval(s) based on a time-variant power envelope of the analog signal. By generating the lower target voltage, in contrast to a conventional method of generating a maximum target voltage, at the start of the defined interval(s), it is possible to reduce energy waste and help improve efficiency in a power amplifier configured to amplify the analog signal based on the time-variant voltage.

Claims

1. A power management circuit comprising: a target voltage circuit configured to: generate a target voltage at a start of each of a plurality of defined intervals for generating a time-variant voltage during each of the plurality of defined intervals to amplify an analog signal; determine, based on a detected time-variant power envelope of the analog signal, whether to change the target voltage during each of the plurality of defined intervals; and adjust the target voltage during each of the plurality of defined intervals in response to determining to change the target voltage.

2. The power management circuit of claim 1 wherein the target voltage circuit is further configured to maintain the target voltage during each of the plurality of defined intervals in response to determining not to change the target voltage during each of the plurality of defined intervals.

3. The power management circuit of claim 1 wherein: the plurality of defined intervals each corresponds to a respective one of a plurality of orthogonal frequency division multiplexing (OFDM) symbols, the plurality of OFDM symbols each comprising a cyclic prefix (CP); and the target voltage circuit is further configured to: generate the target voltage during the CP of each of the plurality of OFDM symbols; and adjust the target voltage after the CP of each of the plurality of OFDM symbols in response to determining to change the target voltage.

4. The power management circuit of claim 1 further comprising a power management integrated circuit (PMIC) configured to generate the time-variant voltage in each of the plurality of defined intervals based on the target voltage.

5. The power management circuit of claim 1 wherein the target voltage circuit comprises a voltage processing circuit configured to: generate the target voltage at the start of each of the plurality of defined intervals; determine, based on the detected time-variant power envelope of the analog signal, whether to change the target voltage during each of the plurality of defined intervals; and adjust the target voltage during each of the plurality of defined intervals in response to determining to change the target voltage.

6. The power management circuit of claim 5 wherein the target voltage circuit further comprises an envelope detector circuit configured to detect a time-variant power envelope of the analog signal and provide the detected time-variant power envelope to the voltage processing circuit.

7. The power management circuit of claim 5 wherein the voltage processing circuit is further configured to: determine, based on the detected time-variant power envelope of the analog signal, whether to increase the target voltage during each of the plurality of defined intervals; and adjust the target voltage to a higher level during each of the plurality of defined intervals in response to determining to increase the target voltage.

8. The power management circuit of claim 7 wherein the voltage processing circuit is further configured to maintain the target voltage at the higher level during each of the plurality of defined intervals.

9. The power management circuit of claim 7 wherein the voltage processing circuit is further configured to decay the target voltage from the higher level at a defined rate during each of the plurality of defined intervals.

10. The power management circuit of claim 7 wherein the target voltage generated at the start of each of the plurality of defined intervals is equal to a root-mean-square (RMS) voltage in each of the plurality of defined intervals.

11. The power management circuit of claim 10 wherein the voltage processing circuit is further configured to receive the RMS voltage prior to the start of each of the plurality of defined intervals.

12. The power management circuit of claim 10 wherein, in response to determining to increase the target voltage, the voltage processing circuit is further configured to increase the target voltage to the higher level that equals V.sub.TGT*10.sup.(x/20), wherein: V.sub.TGT represents the target voltage prior to being increased; and x represents a peak-to-average ratio (PAR) of the target voltage in decibel (dB) term.

13. The power management circuit of claim 7 wherein the target voltage generated at the start of each of the plurality of defined intervals is equal to a reduced target voltage relative to a maximum target voltage in each of the plurality of defined intervals.

14. The power management circuit of claim 13 wherein the voltage processing circuit is further configured to determine the reduced target voltage in each of the plurality of defined intervals based on a statistical model.

15. The power management circuit of claim 13 wherein, in response to determining to increase the target voltage, the voltage processing circuit is further configured to increase the target voltage to the higher level based on an analog lookup table (LUT).

16. The power management circuit of claim 7 wherein, in response to determining to increase the target voltage in each of the plurality of defined intervals, the voltage processing circuit is further configured to adjust the target voltage to the higher level that equals a highest one of: a previous target voltage generated in a previous one of the plurality of defined intervals immediately preceding a present one of the plurality of defined intervals; the target voltage generated in the present one of the plurality of defined intervals; and a root-to-mean-square (RMS) voltage received prior to the start of the present one of the plurality of defined intervals.

17. A power management circuit comprising: a target voltage circuit configured to: generate a target voltage at a start of each of a plurality of defined intervals for generating a time-variant voltage during each of the plurality of defined intervals to amplify an analog signal; determine, based on a detected time-variant power envelope of the analog signal, whether to change the target voltage during each of the plurality of defined intervals; and adjust the target voltage after the start of each of the plurality of defined intervals in response to determining to change the target voltage; and a power management integrated circuit (PMIC) configured to generate the time-variant voltage based on the target voltage in each of the plurality of defined intervals.

18. The power management circuit of claim 17 wherein: the plurality of defined intervals each corresponds to a respective one of a plurality of orthogonal frequency division multiplexing (OFDM) symbols, the plurality of OFDM symbols each comprising a cyclic prefix (CP); and the target voltage circuit is further configured to: generate the target voltage during the CP of each of the plurality of OFDM symbols; and adjust the target voltage after the CP of each of the plurality of OFDM symbols in response to determining to change the target voltage.

19. The power management circuit of claim 17 wherein the target voltage circuit comprises a voltage processing circuit configured to: generate the target voltage at the start of each of the plurality of defined intervals; determine, based on the detected time-variant power envelope of the analog signal, whether to change the target voltage during each of the plurality of defined intervals; and adjust the target voltage during each of the plurality of defined intervals in response to determining to change the target voltage.

20. The power management circuit of claim 19 wherein the target voltage circuit further comprises an envelope detector circuit configured to detect a time-variant power envelope of the analog signal and provide the detected time-variant power envelope to the voltage processing circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] FIG. 1A is a schematic diagram of an exemplary existing power management circuit;

[0011] FIG. 1B is a graphic diagram providing an exemplary illustration of a target voltage(s) generated by the existing power management circuit of FIG. 1A in a defined interval(s);

[0012] FIG. 2 is a schematic diagram of an exemplary power management circuit configured according to embodiments of the present disclosure to dynamically adjust a target voltage(s) during a defined interval(s) when determined as necessary;

[0013] FIGS. 3A-3B are graphic diagrams providing exemplary illustrations as to how the power management circuit of FIG. 2 can be configured to dynamically adjust the target voltage(s) during the defined interval(s);

[0014] FIG. 4 is a graphic diagram providing an exemplary illustration of a statistical model that may be utilized by the power management circuit of FIG. 2 to determine the target voltage(s) at a start of the defined interval(s); and

[0015] FIG. 5 is a graphic diagram providing an exemplary illustration of an analog lookup table (LUT) that can be employed by the power management circuit of FIG. 2 to increase the target voltage(s) from one level to another during the defined interval(s).

DETAILED DESCRIPTION

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0019] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Aspects disclosed in the detailed description include a power management circuit operable to adjust a voltage within a defined interval(s). The power management circuit is configured to generate a time-variant voltage for amplifying an analog signal based on a target voltage. In embodiments disclosed herein, the power management circuit can be configured to generate a lower initial target voltage at a start of the defined interval(s), such as during a cyclic prefix (CP) of an orthogonal frequency division multiplexing (OFDM) symbol, and dynamically adjust the initial target voltage, if necessary, within the defined interval(s) based on a time-variant power envelope of the analog signal. By generating the lower target voltage, in contrast to a conventional method of generating a maximum target voltage, at the start of the defined interval(s), it is possible to reduce energy waste and help improve efficiency in a power amplifier configured to amplify the analog signal based on the time-variant voltage.

[0023] Before discussing a power management circuit of the present disclosure, starting at FIG. 2, a brief overview of an existing power management that generates an initial target voltage based on a maximum target voltage as expected in a defined interval(s) is first provided with reference to FIGS. 1A-1B.

[0024] FIG. 1A is a schematic diagram of an exemplary existing power management circuit 10. The existing power management circuit 10 is configured to provide a time-variant voltage V.sub.CC to a power amplifier 12 for amplifying an analog signal 14. The analog signal 14 may be generated by a transceiver circuit 16 and provided to a signal processing circuit 18 in an intermediate frequency (IF). The signal processing circuit 18 may upconvert the analog signal 14 from the IF to a carrier frequency and provide the analog signal 14 to the power amplifier 12 for amplification.

[0025] The analog signal 14 is associated with a time-variant power envelope 20 that rises and falls over multiple defined intervals, such as the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 as shown. Thus, to prevent potential amplitude distortion in the analog signal 14 and ensure higher operating efficiency of the power amplifier 12, the time-variant voltage V.sub.CC needs to closely track (rises and falls) the time-variant power envelope 20 across the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0026] As such, the existing power management circuit 10 is configured to include a target voltage circuit 22 and a power management integrated circuit (PMIC) 24. The target voltage circuit 22 is configured to detect the time-variant power envelope 20 of the analog signal 14 and generate a target voltage V.sub.TGT based on the detected time-variant power envelope 20. The PMIC 24, in turn, generates the time-variant voltage V.sub.CC based on the target voltage V.sub.TGT.

[0027] FIG. 1B is a graphic diagram providing an exemplary illustration of the target voltage V.sub.TGT generated by the existing power management circuit 10 of

[0028] FIG. 1A in the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.

[0029] As shown in FIG. 1B, the existing power management circuit 10 generates the target voltage V.sub.TGT at a start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 based on a maximum target voltage V.sub.TGT-MAX corresponding to a peak of the time-variant power envelope 20 in a respective one of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. In addition, the existing power management circuit 10 is configured to keep the target voltage V.sub.TGT constant in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0030] For example, the existing power management circuit 10 generates the target voltage V.sub.TGT for the defined interval T.sub.N−1 at the start time t.sub.0 of the defined interval T.sub.N−1 based on a peak of the time-variant power envelope 20 at time t.sub.1, and keeps the target voltage V.sub.TGT constant until the start time t.sub.2 of the defined interval T.sub.N. At time t.sub.2, the existing power management circuit 10 generates the target voltage V.sub.TGT for the defined interval T.sub.N based on a peak of the time-variant power envelope 20 at time t.sub.3 and keeps the target voltage V.sub.TGT constant until the start time t.sub.4 of the defined interval T.sub.N+1. At time t.sub.4, the existing power management circuit 10 generates the target voltage V.sub.TGT for the defined interval T.sub.N+1 based on a peak of the time-variant power envelope 20 at time t.sub.5 and keeps the target voltage V.sub.TGT constant until the end of the defined interval T.sub.N+1.

[0031] However, as shown in FIG. 1 B, the target voltage V.sub.TGT generated by the existing power management circuit 10 is higher than actually needed from time t.sub.0 to t.sub.1, t.sub.2 to t.sub.3, and t.sub.4 to t.sub.5. Accordingly, the PMIC 24 will generate the time-variant voltage V.sub.CC higher than what is needed for amplifying the analog signal 14 in accordance with the time-variant power envelope 20. Notably, the excessive time-variant voltage V.sub.CC generated by the PMIC 24 can lead to energy waste and reduce operating efficiency of the power amplifier 12. As such, it is desirable to optimize target voltage generation in the existing power management circuit 10 to help reduce energy waste and improve operating efficiency of the power amplifier 12.

[0032] In this regard, FIG. 2 is a schematic diagram of an exemplary power management circuit 26 configured according to embodiments of the present disclosure to dynamically adjust a target voltage V.sub.TGT during each of a number of defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 when determined as necessary. In examples discussed herein, the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 each corresponds to a respective one of a number of orthogonal time division multiplexing (OFDM) symbols. However, it should be appreciated that the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 can correspond to different time intervals, such as time slot, mini time slot, and so on. Further, the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 as illustrated herein are merely examples to help explain the embodiments of the present disclosure. It should be understood that the embodiments described with reference to the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 are applicable to an unlimited number of defined intervals.

[0033] The power management circuit 26 is configured to provide a time-variant voltage V.sub.CC to a power amplifier 28 for amplifying an analog signal 30. The analog signal 30 may be generated by a transceiver circuit 32 and provided to a signal processing circuit 34 in an IF. The signal processing circuit 34 may upconvert the analog signal 30 from the IF to a carrier frequency and provide the analog signal 30 to the power amplifier 28 for amplification.

[0034] The analog signal 30 is associated with a time-variant power envelope 36 that rises and falls over the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Thus, to prevent potential amplitude distortion in the analog signal 30 and ensure higher operating efficiency of the power amplifier 28, it is necessary to generate the time-variant voltage V.sub.CC to closely track the time-variant power envelope 36 across the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0035] In this regard, the power management circuit 26 is configured to include a target voltage circuit 38 and a PMIC 40. The target voltage circuit 38 is configured to generate the target voltage V.sub.TGT to track the time-variant power envelope 36 of the analog signal 30. The PMIC 40 is configured to generate a time-variant voltage V.sub.CC based on the target voltage V.sub.TGT. Since the target voltage V.sub.TGT is generated to track the time-variant power envelope 36, the time-variant voltage V.sub.CC will likewise track the time-variant power envelope 36. For details on how the PMIC 40 can generate the time-variant voltage V.sub.CC in a timely manner, please refer to U.S. patent application Ser. No. 17/217,654, entitled “POWER MANAGEMENT CIRCUIT FOR FAST AVERAGE POWER TRACKING VOLTAGE SWITCHING.”

[0036] In contrast to the existing power management circuit 10 of FIG. 1A, which keeps the target voltage V.sub.TGT constant in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1, the power management circuit 26 is configured to dynamically adjust the target voltage V.sub.TGT during each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1, when the power management circuit determines that such adjustment is necessary. In this regard, FIG. 3A is a graphic diagram providing an exemplary illustration as to how the power management circuit 26 of FIG. 2 can be configured to dynamically adjust the target voltage V.sub.TGT across the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Common elements between FIGS. 2 and 3A are shown therein with common element numbers and will not be re-described herein.

[0037] The target voltage circuit 38 is configured to generate the target voltage V.sub.TGT at a start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. For the convenience of reference, the target voltage V.sub.TGT that generates at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 is referred to interchangeably as an initial target voltage V.sub.INIT. In a non-limiting example, the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 each represents a respective one of multiple OFDM symbols S.sub.N−1, S.sub.N, S.sub.N+1. As such, each of the OFDM symbols S.sub.N−1, S.sub.N, S.sub.N+1 begins with a respective cyclic prefix (CP). Accordingly, the target voltage circuit 38 is said to generate the initial target voltage V.sub.INIT at the start of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1, it means that the target voltage circuit 38 generates the initial target voltage V.sub.INIT during the CP of each of the OFDM symbols S.sub.N−1, S.sub.N, S.sub.N+1.

[0038] In contrast to the target voltage circuit 22 in the existing power management circuit 10 of FIG. 1A, the target voltage circuit 38 does not always generate the initial target voltage V.sub.INIT based on the maximum target voltage V.sub.TGT-MAX in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Instead, the target voltage circuit 38 can be configured to opportunistically generate the initial target voltage V.sub.INIT lower than the maximum target voltage V.sub.TGT-MAX in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. As such, the target voltage circuit 38 is further configured to determine, based on a detected time-variant power envelope 36′, whether it is necessary to increase the initial target voltage V.sub.INIT during each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. If the target voltage circuit 38 determines that it is necessary to change the initial target voltage V.sub.INIT during any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1, the target voltage circuit 38 will raise the initial target voltage V.sub.INIT to a higher level after the start (e.g., after the CP) of the defined intervals T.sub.N−1, T.sub.N, and/or T.sub.N+1. If the target voltage circuit 38 determines that it is not necessary to change the initial target voltage V.sub.INIT during any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1, the target voltage circuit 38 will maintain the initial target voltage V.sub.INIT in the defined intervals T.sub.N−1, T.sub.N, and/or T.sub.N+1.

[0039] For example, in the defined interval T.sub.N−1 that starts at time to, the peak of the detected time-variant power envelope 36′ will not occur until time t.sub.3. As such, the target voltage circuit 38 can opportunistically generate the initial target voltage V.sub.INIT at time to t.sub.0 be lower than the maximum target voltage V.sub.TGT-MAX associated with the peak of the detected time-variant power envelope 36′. At or prior to time t.sub.1, the target voltage circuit 38 determines, based on the detected time-variant power envelope 36′, it is necessary to increase the initial target voltage V.sub.INIT. Accordingly, the target voltage circuit 38 increases the initial target voltage V.sub.INIT to the target voltage V.sub.TGT that is still below the maximum target voltage V.sub.TGT-MAX. At or prior to time t.sub.2, the target voltage circuit 38 determines, based on the detected time-variant power envelope 36′, it is necessary to increase the target voltage V.sub.TGT again and increases the target voltage V.sub.TGT accordingly. At or prior to time t.sub.3, the target voltage circuit 38 determines, based on the detected time-variant power envelope 36′, it is necessary to increase the target voltage V.sub.TGT to the maximum target voltage V.sub.TGT-MAX and increases the target voltage V.sub.TGT accordingly. Thereafter, the target voltage circuit 38 maintains the target voltage V.sub.TGT at the maximum target voltage V.sub.TGT-MAX for the remainder of the defined interval T.sub.N−1, until the defined interval T.sub.N starts at time t.sub.4.

[0040] In the defined interval T.sub.N, the peak of the detected time-variant power envelope 36′ will not occur until time t.sub.5. As such, the target voltage circuit 38 can opportunistically generate the initial target voltage V.sub.INIT at time t.sub.4 to be lower than the maximum target voltage V.sub.TGT-MAX associated with the peak of the detected time-variant power envelope 36′. At or prior to time t.sub.5, the target voltage circuit 38 determines, based on the detected time-variant power envelope 36′, it is necessary to increase the initial target voltage V.sub.INIT to the maximum target voltage V.sub.TGT-MAX and increases the initial target voltage V.sub.INIT accordingly. Thereafter, the target voltage circuit 38 maintains the target voltage V.sub.TGT at the maximum target voltage V.sub.TGT-MAX for the remainder of the defined interval T.sub.N, until the defined interval T.sub.N+1 starts at time t.sub.6.

[0041] In the defined interval T.sub.N+1, the peak of the detected time-variant power envelope 36′ occurs at time t.sub.6. As such, the target voltage circuit 38 will generate the initial target voltage V.sub.INIT to be equal to the maximum target voltage V.sub.TGT-MAX and maintains the initial target voltage V.sub.INIT at the maximum target voltage V.sub.TGT-MAX until time t.sub.7.

[0042] FIG. 3B is a graphic diagram providing another exemplary illustration as to how the power management circuit 26 of FIG. 2 can be configured to dynamically adjust the target voltage V.sub.TGT across the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Alternative to maintaining the target voltage V.sub.TGT after raising the target voltage V.sub.TGT at times t.sub.1, t.sub.2, t.sub.3, t.sub.5, and t.sub.6, the target voltage circuit 38 allows the target voltage V.sub.TGT to decay at a defined rate.

[0043] With reference back to FIG. 2, in a non-limiting example, the target voltage circuit 38 includes an envelope detector circuit 42 and a voltage processing circuit 44. The envelope detector circuit 42 is configured to detect the time-variant power envelope 36 of the analog signal 30 and provides the detected time-variant power envelope 36′ to the voltage processing circuit 44. The voltage processing circuit 44, which can be a field-programmable gate array (FPGA), as an example, is configured to generate the target voltage V.sub.TGT (a.k.a. the initial target voltage V.sub.INIT) at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. The voltage processing circuit 44 is also configured to determine, based on the detected time-variant power envelope 36′ of the analog signal 30, whether to change the target voltage V.sub.TGT during each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Accordingly, the voltage processing circuit 44 can adjust the target voltage V.sub.TGT during each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 in response to determining to change the target voltage V.sub.TGT.

[0044] In one embodiment, the voltage processing circuit 44 can generate the target voltage V.sub.TGT (a.k.a. the initial target voltage V.sub.INIT) at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 to equal a root-mean-square (RMS) voltage V.sub.RMS determined for each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. In a non-limiting example, the RMS voltage V.sub.RMS can be determined by the transceiver circuit 32 and provided to the voltage processing circuit 44 prior to the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. The transceiver circuit 32 may provide the RMS voltage V.sub.RMS to the voltage processing circuit 44 via a serial interface, such as radio frequency front-end (RFFE), or a parallel interface, such as general-purpose input output (GPIO). Accordingly, the voltage processing circuit 44 can generate the initial target voltage V.sub.INIT that equals the RMS voltage V.sub.RMS (V.sub.INIT=V.sub.RMS) at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0045] When the voltage processing circuit 44 determines to increase the target voltage V.sub.TGT during any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 (e.g., at or prior to times t.sub.1, t.sub.2, t.sub.3, and t.sub.5 in FIGS. 3A and 3B), the voltage processing circuit 44 may be configured to increase the target voltage V.sub.TGT to a higher level V.sub.TGT-NEW as expressed in equation (Eq. 1) below.

V.sub.TGT-NEW=V.sub.TGT*10.sup.(x/20)   (Eq. 1)

[0046] In the equation (Eq. 1) above, V.sub.TGT represents the target voltage V.sub.TGT prior to being increased and x represents a peak-to-average ratio (PAR) of the target voltage V.sub.TGT in decibel (dB) term.

[0047] In another embodiment, the voltage processing circuit 44 can generate the target voltage V.sub.TGT (a.k.a. the initial target voltage V.sub.INIT) at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 to equal a reduced target voltage V.sub.TGT-RDU relative to the maximum target voltage V.sub.TGT-MAX in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. In a non-limiting example, as shown in FIG. 4, the voltage processing circuit 44 can determine the reduced target voltage V.sub.TGT-RDU based on a statistical model. In this regard, FIG. 4 is a graphic diagram providing an exemplary illustration of a statistical model that may be utilized by the target voltage circuit 38 in the power management circuit 26 of FIG. 2 to determine the target voltage V.sub.TGT at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0048] The statistical model shown in FIG. 4 includes a voltage-probability curve 46. According to the voltage-probability curve 46, if the maximum target voltage V.sub.TGT-MAX in each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 corresponds to a 100% probability, then the reduced target voltage V.sub.TGT-RDU will be any voltage on the voltage-probability curve 46 with less than 100% probability. For example, if the maximum target voltage V.sub.TGT-MAX is 5 V, then the reduced target voltage V.sub.TGT-RDU with 90% probability is approximately 3.75 V. In this regard, the voltage processing circuit 44 may generate the target voltage V.sub.TGT (a.k.a. V.sub.INIT) at the start of each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 to equal 3.75 V.

[0049] The voltage processing circuit 44 can be configured to increase the target voltage V.sub.TGT during any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 based on an analog lookup table (LUT) 48. In this regard, FIG. 5 is a graphic diagram providing an exemplary illustration of the analog LUT 48 that can be employed by the voltage processing circuit 44 to increase the target voltage V.sub.TGT from one level to another during any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0050] In a non-limiting example, the analog LUT 48 includes an isogain curve 50 that correlates the detected time-variant power envelope 36′ with the target voltage V.sub.TGT. In this regard, the voltage processing circuit 44 may be configured to increase the target voltage V.sub.TGT to a higher level V.sub.TGT-NEW in accordance with the isogain curve 50 in the analog LUT 48.

[0051] In an alternative embodiment, the voltage processing circuit 44 may be configured to increase the target voltage V.sub.TGT to a higher level V.sub.TGT-NEW in accordance with the equation (Eq. 2) below.

V.sub.TGT-NEW=MAX (V.sub.TGT-PREV, V.sub.TGT-LUT, V.sub.RMS)   (Eq. 2)

[0052] In the equation (Eq. 2) above, V.sub.TGT-PREV represents a previous target voltage generated in a previous one of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 immediately preceding a present one of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. For example, if the present defined interval is T.sub.N, then the V.sub.TGT-PREV represents the target voltage V.sub.TGT generated in the defined interval T.sub.N−1. V.sub.TGT-LUT represents the target voltage V.sub.TGT generated in the present one of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1 based on the analog LUT 48. V.sub.RMS represents the RMS voltage V.sub.RMS determined for each of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1. Accordingly, the voltage processing circuit 44 can increase the target voltage V.sub.TGT to a highest one of the V.sub.TGT-PREV, V.sub.TGT-LUT, and V.sub.RMS in any of the defined intervals T.sub.N−1, T.sub.N, T.sub.N+1.

[0053] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.