High stability gain structure and filter realization with less than 50 ppm/° c. temperature variation with ultra-low power consumption using switched-capacitor and sub-threshold biasing

Abstract

An ultra-low power sub-threshold g.sub.m stage is disclosed where transconductance is very stable with process, temperature, and voltage variations. This technique can be implemented in a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain can achieve a small temperature coefficient of 48.6 ppm/° C. and exhibits small sigma of 75 mdB with process. The second order biquad can achieve temperature stability of 69 ppm/° C. and a voltage coefficient of only 49 ppm/mV.

Claims

1. A method comprising: generating a biasing current (I.sub.0) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, said circuit including a switched capacitor resistor having a first capacitor, wherein the biasing current (I.sub.0) is given by:
I.sub.0=V.sub.T ln(M)/R.sub.1, where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant g.sub.m bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit; and biasing a differential amplifier with the biasing current, the differential amplifier including a load switched capacitor resistor having a second capacitor, wherein the differential amplifier has constant gain (A.sub.v), independent of manufacturing process variation or temperature variation, given by:
A.sub.v=ln(M)f.sub.1C.sub.1/ηf.sub.3C.sub.3, where η is a process constant value for the differential amplifier, C.sub.3 is a capacitance of the second capacitor, and f.sub.3 is a frequency of the load switched capacitor resistor of the differential amplifier.

2. The method of claim 1, wherein the method is implemented in a ultra-low power and lower area Internet of things (IoT) device.

3. A differential amplifier circuit, comprising: (a) a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption generating a biasing current (I.sub.0), said constant gm bias circuit including a switched capacitor resistor having a first capacitor, wherein the biasing current (I.sub.0) is given by:
I.sub.0=V.sub.T ln(M)/R.sub.1, where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant gm bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit; and (b) a differential amplifier biased with the biasing current, the differential amplifier including a load switched capacitor resistor having a second capacitor, wherein the differential amplifier has constant gain (A.sub.v) given by:
A.sub.v=ln(M)f.sub.1C.sub.1/ηf.sub.3C.sub.3 where η is a process constant value for the differential amplifier; C.sub.3 is a capacitance of the second capacitor, and f.sub.3 is a frequency of the load switched capacitor resistor of the differential amplifier.

4. The differential amplifier circuit of claim 3, wherein the differential amplifier circuit is implemented in a ultra-low power and lower area Internet of things (IoT) device.

5. The differential amplifier circuit of claim 3, wherein the constant gm bias circuit includes one or more decoupling capacitors for suppressing ripple originating from the switched capacitor resistor in the constant gm bias circuit.

6. A second-order biquad filter, comprising: (a) a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption generating a biasing current (I.sub.0), said constant gm bias circuit including a switched capacitor resistor having a first capacitor, wherein the biasing current (I.sub.0) is given by:
I.sub.0=V.sub.T ln(M)/R.sub.1, where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant gm bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit; and (b) a second order biquad filter biased with the biasing current to obtain a stable cut-off frequency.

7. The second-order biquad filter of claim 6, wherein the second order biquad filter comprises four operational transconductance amplifiers, each transconductance amplifier having a second capacitor, wherein the unity gain frequency (UGF) of the second order biquad filter given by:
UGF=ln(M)f.sub.1C.sub.1/ηC.sub.2 where η is a constant value for the amplifiers, and C.sub.2 is a capacitance of the second capacitor.

8. The second-order biquad filter of claim 6, wherein the second order biquad filter includes a plurality of third capacitors, and wherein the cut-off frequency of the second order biquad filter is given by
Wo=ln(M)f.sub.1C.sub.1/ηC.sub.4, where η is a constant value for the amplifiers, and where C.sub.4 is a capacitance of the second capacitor.

9. The second-order biquad filter of claim 6, wherein second-order biquad filter is implemented in a ultra-low power and lower area Internet of things (IoT) device.

10. The second-order biquad filter of claim 6, wherein the constant gm bias circuit includes one or more decoupling capacitors for suppressing ripple originating from the switched capacitor resistor in the constant gm bias circuit.

11. A method comprising: generating a biasing current (I.sub.0) using a constant g.sub.m bias circuit operating in the subthreshold region for ultra-low power consumption, said circuit including a switched capacitor resistor having a first capacitor, wherein the biasing current (I.sub.0) is given by:
I.sub.0=V.sub.T ln(M)/R.sub.1, where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant gm bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit, and wherein generating a biasing current (I.sub.0) includes suppressing ripple originating from the switched capacitor resistor in the constant gm bias circuit using one or more decoupling capacitors.

12. A method comprising: generating a biasing current (I.sub.0) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, said circuit including a switched capacitor resistor having a first capacitor, wherein the biasing current (I.sub.0) is given by:
I.sub.0=V.sub.T ln(M)/R.sub.1, where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant gm bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit; and biasing a second order biquad filter with the biasing current to obtain a stable cut-off frequency.

13. The method of claim 12, wherein the second order biquad filter comprises four operational transconductance amplifiers, each transconductance amplifier having a second capacitor, wherein the unity gain frequency (UGF) of the second order biquad filter given by:
UGF=ln(M)f.sub.1C.sub.1/ηC.sub.2 where η is a constant value for the amplifiers, and C.sub.2 is a capacitance of the second capacitor.

14. The method of claim 13, wherein the second order biquad filter includes a plurality of third capacitors, and wherein the cut-off frequency of the second order biquad filter is given by
Wo=ln(M)f.sub.1C.sub.1/ηC.sub.4, where η is a constant value for the amplifiers, and where C.sub.4 is a capacitance of the second capacitor.

15. The method of claim 12, wherein the method is implemented in a ultra-low power and lower area Internet of things (IoT) device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows an exemplary conventional MOS-based current source for constant gm biasing.

(2) FIG. 1B shows an exemplary BJT-based current source for constant gm biasing.

(3) FIG. 2A shows an exemplary RC filter for ripple suppression implemented using transistors.

(4) FIG. 2B shows an exemplary differential amplifier with an SCR and decoupling capacitors in accordance with one or more embodiments.

(5) FIG. 2C shows an exemplary operational transconductance amplifier (OTA) in accordance with one or more embodiments.

(6) FIG. 2D shows an exemplary second order biquad filter in accordance with one or more embodiments.

(7) FIG. 3 shows amplifier output before and after filtering with an ideal filter.

(8) FIGS. 4A and 4B show differential amplifier gain variance with temperature and voltage, respectively.

(9) FIG. 5A shows process variation of differential amplifier gain at 50□, and FIG. 5B shows process variation of cut off frequency of a biquad filter.

(10) FIGS. 6A and 6B show variation of cut off frequency of a biquad LPF with temperature and supply voltage, respectively.

(11) FIGS. 7A and 7B show variation of unity gain frequency of OTA with temperature and process, respectively.

(12) FIG. 8 is a table showing performance comparisons between known constant gm bias circuits and exemplary circuits in accordance with various embodiments.

DETAILED DESCRIPTION

(13) Precision Analog Gain Structure and Filter Implementation

(14) The transconductance, g.sub.m of a transistor in sub-threshold is given by

(15) $\begin{array}{cc}{g}_m=\frac{I_D}{\eta V_T}& \left(1\right)\end{array}$

(16) where I.sub.D is the bias current, η is a process constant, and V.sub.T is the thermal voltage. The transconductance is inversely proportional to temperature. If the transistor is biased with a current source that is proportional to absolute temperature (PTAT), then a constant g.sub.m can be obtained as

(17) $\begin{array}{cc}{g}_m=\frac{I_{\mathrm{PTAT}}}{\eta V_T}& \left(2\right)\end{array}$

(18) PTAT current is obtained using the conventional BJT based current source with a resistor R.sub.1 shown in FIG. 1B, where Q.sub.1 has M times the area of Q.sub.2.
I.sub.0=V.sub.T ln(M)/R.sub.1  (3) where V.sub.T is the thermal voltage of the constant g.sub.m bias circuit, where the thermal voltage is kT/q, where k is the Boltzman's constant, T is the temperature in Kelvin, and q is the unit of charge, M is a multiplication factor relating two transistors in the constant gm bias circuit,
R.sub.1=1/f.sub.1C.sub.1, C.sub.1 is a capacitance of the first capacitor, and f.sub.1 is a frequency of a reference clock of the constant gm bias circuit.

(19) When I.sub.o is used to bias a transistor in sub-threshold, its transconductance can be calculated using Eq. (2) and (3) as
g.sub.m=ln(M)/ηR.sub.1  (4) which has a lower variation as it only depends on R.sub.1.

(20) The conventional MOS-based current source shown in FIG. 1A can also be biased in the sub-threshold region to obtain a PTAT current. This is because the current through a MOS biased in sub-threshold region is,

(21) $\begin{array}{cc}{I}_{\mathrm{DS}}=I_{S0}\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{th}}-V_{\mathrm{off}}}{\eta V_T}\right)\left(1-\exp \left(-\frac{V_{\mathrm{DS}}}{V_T}\right)\right)& \left(5\right)\end{array}$ where I.sub.S0 is the sub-threshold saturation current and V.sub.off is the offset voltage as discussed in [19] and [20]. The current characteristic is exponential, similar to that of a BJT. However, we use BJTs for a more precise operation. Assuming V.sub.DS>3 V.sub.T in a circuit configuration shown in FIG. 1A which is biased in sub-threshold, the offset V.sub.off in equation (5) gives rise to the following current

(22) $\begin{array}{cc}{I}_o=\frac{V_T\ln \left(K\right)}{R}+\mathrm{const}& \left(6\right)\end{array}$

(23) The constant term, const, is independent of temperature, which makes transconductance vary with temperature. A BJT based PTAT current source does not suffer from this issue and provides better stability.

(24) Resistor implementation is susceptible to process and temperature variations. Also, for small current generation in the nAs range, a very large resistor is needed, which can be difficult to implement. These challenges are overcome by replacing the resistor with a switched capacitor implementation. The SCR implementation is achieved by using MIM cap and a reference frequency clock. MIM caps have a small temperature coefficient of 35 ppm/° C. [21] and small process variations. Also, the stable frequency reference which is used for SCR network is a fundamental component in most systems. It has a stability of less than 3-5 ppm/° C. and can operate with a power consumption of 1-2 nW [22]. Since large resistors in the range of Mega-Ω s are required to generate small current for sub-threshold biasing, the area of the switched capacitor design can be much lower than the resistor based design while providing high degree of accuracy. Also, since the same bias circuit is used to bias several other circuits on the chip, the overhead is not large.

(25) The resistance of the SCR is given by

(26) $\begin{array}{cc}R=\frac{1}{f_1{C}_1}& \left(7\right)\end{array}$
where f.sub.1 is the frequency of the reference clock and C.sub.1 is the capacitor.

(27) From Eq. (4) and (7), transconductance is now given by
g.sub.m=ln(M)f.sub.1C.sub.1/η  (8)

(28) Eq. 8 shows that g.sub.m is now a function of capacitor and reference frequency. Decoupling capacitors (C.sub.d) of 8 pF are added at nodes A and B in FIG. 1B to suppress the ripple originating from the SCR and also to ensure that the resistance of the network remains constant with temperature. Since nodes V.sub.X and V.sub.Y are used to bias other circuits, RC filters are used to filter out the ripple. The filter needed for ripple suppression can be implemented using transistors (FIG. 2A) or with active filters to save area. The op-amp in the current source also helps in filtering out ripple at V.sub.X as it is designed to have small bandwidth.

(29) One source of temperature instability in an SCR based circuit can manifest from the charge injection through the gates of SCR circuits. We use small size switches with dummy switches for charge injection cancellation for better stability with temperature and voltage.

(30) Differential Amplifier

(31) An exemplary single stage differential amplifier with resistive loads in accordance with one or more embodiments depicted in FIG. 2B is biased with the described constant g.sub.m biasing scheme. For low power consumption, the amplifier is designed in the sub-threshold region and is biased with 50 nA current. The gain A.sub.V of the amplifier is given by,
A.sub.v=g.sub.mR.sub.D  (9)

(32) where R.sub.D is the load resistor. A gain of 20 dB with this single stage amplifier requires large resistors of ˜18 MΩ at the load to obtain an output common mode level of 500 mV. Here, the large resistors are replaced with switched capacitor resistors to achieve the same gain (FIG. 2B). The differential amplifier was designed with both a poly-resistor and SCR with 600 fF flying capacitor, and 3 pF decoupling capacitors to estimate area. The area of the poly-resistor amplifier was 1.3× higher area than the SCR implementation. Even lower area and lower power solution can be envisioned with SCR. The gain with SCR load is given by
A.sub.v=ln(M)f.sub.1C.sub.1/ηf.sub.3C.sub.3  (10) where f.sub.3 is the frequency of the load SCR of the amplifier.

(33) Small flying capacitor and high frequency of 90 kHz is used to emulate the load resistor. This is to ensure that the ripple frequency from the load SCR falls outside the bandwidth of the amplifier. The small ripple introduced by the SCR can be filtered out using a filter (FIG. 3). Also, the frequency for the load SCR can be generated from the reference clock on the chip. From eq. (10), it is clear that gain is constant and the only process dependent parameter is η. Capacitors show little variation with process, and are in a ratio that is reliable even with variations. FIGS. 4A and 4B show the temperature and voltage variation of the amplifier gain, and FIG. 5A shows variation with process. The amplifier gain (in V/V) has a temperature coefficient of less than 50 ppm/° C., and varies by 1.27% for a 25% increase in supply.

(34) Second Order Filter

(35) An exemplary second order biquad filter in accordance with one or more embodiments shown in FIG. 2D is biased with the constant g.sub.m biasing circuit to obtain stable cut-off frequency. The filter includes four identical operational transconductance amplifiers (OTAs) (FIG. 2C) biased with sub-threshold PTAT current, whose unity gain frequency is given by

(36) $\begin{array}{cc}UGF=\frac{g_m}{C_2}& \left(11\right)\end{array}$

(37) From Eq (8) and (11)
UGF=ln(M)f.sub.1C.sub.1/ηC.sub.2  (12)

(38) Eq. (12) shows that the UGF is now completely dependent on the ratio of C.sub.1 and C.sub.2 which implies that it is only dependent on reference clock frequency and η to achieve a very high stability. Variation of UGF with temperature is shown in FIG. 7A, which is less than 0.7%. The cut-off frequency of the biquad filter shown in FIG. 2D is given by ([23]),

(39) $\begin{array}{cc}{\left({\omega }_o\right)}^2=\frac{g_{m3}{g}_{m4}}{{\left(C_4\right)}^2}& \left(13\right)\end{array}$

(40) Hence, replacing transconductance by Eq. (8), and assuming all transconductances are equal,
Wo=ln(M)f.sub.1C.sub.1/ηC.sub.4  (14)

(41) The cut off frequency is independent of temperature and supply as shown in FIG. 6A and FIG. 6B. The temperature and voltage coefficients of the filter are found to be 69 ppm/° C. and 49 ppm/mV respectively. Table I shown in FIG. 8 compares our work with prior-works. The work in [16] shows better stability than our work but relies on an external voltage source to fine-tune the PTAT current source. The work in [15] also uses sub-threshold biasing to realize high stability but can only achieve lower bandwidth of 12 Hz. Our work achieves higher performance and reduces the power consume when compared to a more related recent prior art [9]. We also report a very wide temperature range of operation of 0-120° C. when compared to [14] and [10].

(42) In summary, the present application discloses a methodology for constant g.sub.m biasing where the circuits are biased in sub-threshold region with a proportional to absolute temperature current to obtain constant transconductance which is highly stable with temperature, supply and process variations. A differential amplifier with constant gain, and a second order biquad filter with constant cut off frequency disclosed demonstrate proof of concept. The differential amplifier achieves 49 ppm/° C. temperature coefficient for the gain, which varies by 1.27% with a 25% increase in supply. Simulations also show that the with a temperature coefficient of 69 ppm/° C.

(43) Having thus described several illustrative embodiments, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to form a part of this disclosure, and are intended to be within the spirit and scope of this disclosure. While some examples presented herein involve specific combinations of functions or structural elements, it should be understood that those functions and elements may be combined in other ways according to the present disclosure to accomplish the same or different objectives. In particular, acts, elements, and features discussed in connection with one embodiment are not intended to be excluded from similar or other roles in other embodiments. Additionally, elements and components described herein may be further divided into additional components or joined together to form fewer components for performing the same functions.

(44) Accordingly, the foregoing description and attached drawings are by way of example only, and are not intended to be limiting.

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