High dynamic range temperature sensor

Abstract

A temperature sensor having a two-state input current, an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current, a charge-to-digital converter, and a capacitor continuously connected between the element and the charge-to-digital converter. The capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current, and the charge-to-digital converter converts the charge difference to a digital value indicative of the temperature of the element. A two-state DC-shifting current having opposite polarity of the two-state input current, a pull-down resistor whose voltage varies with the two-states of the DC-shifting current, and a second capacitor continuously connected between the pull-down resistor and the charge-to-digital converter operate to shift down a DC operating point of the charge-to-voltage converter to increase its dynamic range.

Claims

1. A temperature sensor, comprising: a two-state input current; an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; a charge-to-digital converter; and a capacitor continuously connected between the element and the charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; wherein the charge-to-digital converter converts the charge difference to a digital value indicative of the temperature of the element; and wherein the temperature sensor is absent switches connected to the element.

2. The temperature sensor of claim 1, wherein the element is an element from the list: a bipolar junction transistor (BJT); and a resistor.

3. The temperature sensor of claim 1, wherein the charge-to-digital converter comprises: a charge-to-voltage converter that converts the charge to a voltage; and a voltage-to-digital converter that converts the voltage to the digital value.

4. The temperature sensor of claim 3, wherein the voltage-to-digital converter samples an output of the charge-to-voltage converter and converts the sampled voltage to the digital value.

5. The temperature sensor of claim 3, further comprising: a two-state direct current (DC)-shifting current that has opposite polarity of the two-state input current; a pull-down resistor whose voltage varies with the two-states of the DC-shifting current; and a second capacitor continuously connected between the pull-down resistor and the charge-to-digital converter; wherein the DC-shifting current, pull-down resistor and second capacitor operate to shift down a DC operating point of the charge-to-voltage converter to increase a dynamic range of the charge-to-voltage converter.

6. The temperature sensor of claim 3, wherein the charge-to-voltage converter comprises: an amplifier having an input and an output; and a feedback capacitor connected between the input and output of the amplifier.

7. The temperature sensor of claim 6, further comprising: a switch, in parallel with the feedback capacitor, whose state follows the two states of the input current.

8. The temperature sensor of claim 6, further comprising: a sense node at which the capacitor is connected to the element, wherein the sense node holds a voltage indicative of the temperature of the element; and wherein the voltage-to-digital converter receives a reference voltage that is a scaled version of the sense node voltage.

9. A method for sensing a temperature, comprising: forcing a two-state input current into an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; using a capacitor to maintain a continuous connection between the element and a charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; converting, by the charge-to-digital converter, the charge difference to a digital value indicative of the temperature of the element; and operating the temperature sensor without switches connected to the element.

10. The method of claim 9, wherein the element is an element from the list: a bipolar junction transistor (BJT); and a resistor.

11. The method of claim 9, wherein said converting the charge difference to the digital value comprises: converting, by a charge-to-voltage converter, the charge to a voltage; and converting, by a voltage-to-digital converter, the voltage to the digital value.

12. The method of claim 11, further comprising: sampling, by the voltage-to-digital converter, an output of the charge-to-voltage converter and converting the sampled voltage to the digital value.

13. The method of claim 11, further comprising: forcing a two-state direct current (DC)-shifting current that has opposite polarity of the two-state input current into a pull-down resistor whose voltage varies with the two-states of the DC-shifting current; using a second capacitor to maintain a continuous connection between the pull-down resistor and the charge-to-digital converter; and operating the DC-shifting current, pull-down resistor and second capacitor to shift down a DC operating point of the charge-to-voltage converter to increase a dynamic range of the charge-to-voltage converter.

14. The method of claim 11, wherein the charge-to-voltage converter comprises: an amplifier having an input and an output; and a feedback capacitor connected between the input and output of the amplifier.

15. The method of claim 14, further comprising: closing a switch that is in parallel with the feedback capacitor during one state of the input current; and opening the switch during the other state of the input current.

16. The method of claim 14, further comprising: holding, on a sense node at which the capacitor is connected to the element, a voltage indicative of the temperature of the element; and receiving, by the voltage-to-digital converter, a reference voltage that is a scaled version of the sense node voltage.

17. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a temperature sensor to perform operations comprising: forcing a two-state input current into an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; using a capacitor to maintain a continuous connection between the element and a charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; converting, by the charge-to-digital converter, the charge difference to a digital value indicative of the temperature of the element; and operating the temperature sensor without switches connected to the element.

18. The non-transitory computer-readable medium of claim 17, wherein said converting the charge difference to the digital value comprises: converting, by a charge-to-voltage converter, the charge to a voltage; and converting, by a voltage-to-digital converter, the voltage to the digital value.

19. A temperature sensor, comprising: a two-state input current; an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; a charge-to-digital converter; a capacitor continuously connected between the element and the charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; wherein the charge-to-digital converter converts the charge difference to a digital value indicative of the temperature of the element; and wherein the charge-to-digital converter comprises: a charge-to-voltage converter that converts the charge to a voltage; and a voltage-to-digital converter that converts the voltage to the digital value; a two-state direct current (DC)-shifting current that has opposite polarity of the two-state input current; a pull-down resistor whose voltage varies with the two-states of the DC-shifting current; and a second capacitor continuously connected between the pull-down resistor and the charge-to-digital converter; wherein the DC-shifting current, pull-down resistor and second capacitor operate to shift down a DC operating point of the charge-to-voltage converter to increase a dynamic range of the charge-to-voltage converter.

20. A method for sensing a temperature, comprising: forcing a two-state input current into an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; using a capacitor to maintain a continuous connection between the element and a charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; converting, by the charge-to-digital converter, the charge difference to a digital value indicative of the temperature of the element; wherein said converting the charge difference to the digital value comprises: converting, by a charge-to-voltage converter, the charge to a voltage; and converting, by a voltage-to-digital converter, the voltage to the digital value; forcing a two-state direct current (DC)-shifting current that has opposite polarity of the two-state input current into a pull-down resistor whose voltage varies with the two-states of the DC-shifting current; using a second capacitor to maintain a continuous connection between the pull- down resistor and the charge-to-digital converter; and operating the DC-shifting current, pull-down resistor and second capacitor to shift down a DC operating point of the charge-to-voltage converter to increase a dynamic range of the charge-to-voltage converter.

21. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a temperature sensor to perform operations comprising: forcing a two-state input current into an element whose temperature is sensed based on a change in voltage across the element induced by the two states of the input current; using a capacitor to maintain a continuous connection between the element and a charge-to-digital converter, wherein the capacitor experiences a charge difference due to the change in voltage across the element induced by the two states of the input current; converting, by the charge-to-digital converter, the charge difference to a digital value indicative of the temperature of the element; wherein said converting the charge difference to the digital value comprises: converting, by a charge-to-voltage converter, the charge to a voltage; and converting, by a voltage-to-digital converter, the voltage to the digital value; forcing a two-state direct current (DC)-shifting current that has opposite polarity of the two-state input current into a pull-down resistor whose voltage varies with the two-states of the DC-shifting current; using a second capacitor to maintain a continuous connection between the pull-down resistor and the charge-to-digital converter; and operating the DC-shifting current, pull-down resistor and second capacitor to shift down a DC operating point of the charge-to-voltage converter to increase a dynamic range of the charge-to-voltage converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1 and 2 are circuit diagrams of prior art temperature sensors.

(2) FIG. 3 is a circuit diagram illustrating a temperature sensor in accordance with embodiments of the present disclosure.

(3) FIG. 4 is a timing diagram illustrating operation of the sensor of FIG. 3 in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

(4) Embodiments of a temperature sensor that provides high temperature detection accuracy with low noise and higher signal level, very low process sensitivity, and very low power consumption are described.

(5) FIG. 3 is a circuit diagram illustrating a temperature sensor 500 in accordance with embodiments of the present disclosure. Sensor 500 is a continuous capacitive gain stage-based temperature sensor without sampling switches. In one embodiment, the temperature sensor is a PTAT sensor. In an alternate embodiment, the temperature sensor is a NTAT sensor. The temperature sensor 500 includes a gain stage 4, a reference stage 5, an analog-to-digital converter (ADC) (also referred to in FIG. 3 as voltage-to-digital converter 8), a first high-low state (two-state) current source I.sub.b coupled to a power source, a second high-low state (two-state) current source I.sub.in coupled to the power source, an NPN bipolar junction transistor (BJT) Q, a capacitor C.sub.s, a capacitor C.sub.b, a feedback capacitor C.sub.f, a pull-down resistor R.sub.b, series resistors R.sub.1 and R.sub.2, a switch 1, a switch 2, a switch 3, a pin OUT at the output of gain stage 4, and a pin SENSE coupled to the non-inverting input of reference stage 5.

(6) Transistor Q is diode-connected, i.e., its base and collector are coupled together. The collector of transistor Q is coupled to the output of two-state current source I.sub.in and to pin SENSE. Two-state input current I.sub.in is pumped into the base and collector of transistor Q. The two states of input current I.sub.in are a high state current I.sub.2 and a low state current I.sub.1 (see FIG. 4). Transistor Q converts the two-state input current I.sub.in into a base-emitter voltage V.sub.BE. More specifically, the voltage generated by transistor Q in response to high state current I.sub.2 is referred to as voltage V.sub.BE2, and the voltage generated by transistor Q in response to low state current I.sub.1 is referred to as voltage V.sub.BE1. Transistor Q is an element whose temperature may be sensed based on a change in its base-emitter voltage V.sub.BE induced by the two different states of the input current I.sub.in, e.g., a change from low current state I.sub.1 to high current state I.sub.2. Other embodiments use a different type of element, e.g., a resistor with a temperature-varying resistance whose temperature may be sensed based on a temperature-dependent change in voltage across it induced by the two different states of the input current I.sub.in.

(7) Capacitor C.sub.s is continuously connected between the base/collector of transistor Q and the inverting input of gain stage 4. That is, capacitor C.sub.s is not switched. The non-inverting input to gain stage 4 receives a common mode input voltage V.sub.cm. The inverting input to gain stage 4 is maintained at the same voltage V.sub.cm by virtual ground effect of feedback around the gain stage. The charge Q.sub.Cs on capacitor C.sub.s is given by the relationship Q.sub.C.sub.s=C.sub.s*(V.sub.BE−V.sub.cm), where C.sub.s is the capacitance of capacitor C.sub.s. In this sense, capacitor C.sub.s samples voltage V.sub.BE. Stated alternatively, capacitor C.sub.s converts base-emitter voltage V.sub.BE into an input charge.

(8) Pull-down resistor R.sub.b is coupled between the output of two-state current source I.sub.b and ground. Two-state current I.sub.b is pumped into pull-down resistor R.sub.b. The two states of current I.sub.b are a high state current I.sub.b2 and a low state current I.sub.b1 (see FIG. 4). Resistor R.sub.b generates a voltage V.sub.b. More specifically, the voltage generated by resistor R.sub.b in response to high state current I.sub.b2 is referred to as voltage V.sub.b2, and the voltage generated by resistor R.sub.b in response to low state current I.sub.b1 is referred to as voltage V.sub.b1 (see equations (2) through (6) below). Capacitor C.sub.b is continuously connected between the non-ground terminal of pull-down resistor R.sub.b and the inverting input of gain stage 4. That is, capacitor C.sub.b is not switched. The charge Q.sub.Cb on capacitor C.sub.b is given by the relationship Q.sub.C.sub.b=C.sub.b*(V.sub.b−V.sub.cm), where C.sub.b is the capacitance of capacitor C.sub.b. In this sense, capacitor C.sub.b samples voltage V.sub.b. Stated alternatively, capacitor C.sub.b converts voltage V.sub.b into an input charge. Two-state current source I.sub.b, pull-down resistor R.sub.b, and capacitor C.sub.b operate as a continuous DC shifting branch to shift the DC operating point and maximize signal dynamic range at the output of gain stage 4. Operation of the continuous DC shifting branch is described in more detail below with respect to FIG. 4.

(9) Feedback capacitor C.sub.f is coupled between the inverting input and the output of gain stage 4. Feedback capacitor C.sub.f gains up the input charge generated by conversion of voltage V.sub.BE by capacitor C.sub.s. Feedback capacitor C.sub.f also gains up the input charge generated by conversion of voltage V.sub.b by capacitor C.sub.b. Switch 1 is coupled across feedback capacitor Cf. The charge Q.sub.Cf on capacitor C.sub.f when switch 1 is open is given by the relationship Q.sub.C.sub.f=C.sub.f*V.sub.o, where C.sub.f is the capacitance of capacitor C.sub.f. When switch 1 is closed, the voltage across capacitor C.sub.f is zero and there is no charge on capacitor C.sub.f.

(10) Stage 5 generates a reference voltage V.sub.ref_adc on its output. The ADC receives the reference voltage V.sub.ref_adc when switch 3 is closed enabling the ADC to convert the analog output voltage V.sub.o to a digital value. Resistor R.sub.2 is coupled between the output of stage 5 and a node to which resistor R.sub.1 and the inverting input of stage 5 are coupled. The other terminal of resistor R.sub.1 is coupled to ground. Thus, when switch 3 is closed, V.sub.ref_adc is a scaled version of voltage V.sub.BE for use by the ADC in converting analog input voltage V.sub.in_adc to digital output D.sub.out.

(11) Gain stage 4 generates an analog output voltage V.sub.o that is provided to switch 2. When switch 2 is closed, the output voltage V.sub.o is provided as an input voltage V.sub.in_adc to the input of the ADC for sampling. The ADC converts the analog input voltage V.sub.in_adc to a digital value D.sub.out.

(12) The average value of the bit stream output D.sub.out of the ADC provides temperature information of the transistor Q, as indicated by equation (1)

(13) $\begin{array}{cc}\mu =\mathrm{Mean}\left\{D_{out}\right\}=G*\left(\frac{\Delta V_{BE}}{V_{BE2}}\right),G=\frac{C_S}{C_F},\Delta V_{BE}=V_{BE2}-V_{BE1}& \left(1\right)\end{array}$
where V.sub.BE1 is the value of voltage V.sub.BE when two-state input current I.sub.in is the low state current I.sub.1 and V.sub.BE2 is the value of voltage V.sub.BE when two-state input current I.sub.in is the high state current I.sub.2.

(14) Gain stage 4, feedback capacitor C.sub.f, and switch 1 are an embodiment of a charge-to-voltage converter 7 that converts a change in the charge on capacitor C.sub.s (ΔQ.sub.Cs) between the two states of the input current I.sub.in to a voltage V.sub.o, which is indicative of the temperature of element transistor Q, as described in more detail below. The input charge to gain stage 4 is generated by capacitor C.sub.s and capacitor C.sub.b, as described above. Together, charge-to-voltage converter 7 and the ADC operate as a charge-to-digital converter 6. Because capacitor C.sub.s is not switched but is instead continuously connected between the element whose temperature may vary (e.g., transistor Q) and charge-to-digital converter 6, it provides an alternating current AC-coupled path between them, rather than a DC path that would be present if the capacitor were used as a switched-capacitor resistor, for example. By changing the state of the input current I.sub.in, the value of voltage V.sub.BE changes accordingly, and such an alternating value couples through capacitor C.sub.s. Furthermore, the voltage difference ΔV.sub.BE, or change of voltage V.sub.BE, between the two states may be considered a DC value that is obtained by operation of the switching in the current domain. Advantages of the embodiment over a switched-capacitor solution (e.g., the Pu Paper) include but are not limited to removal of switching thermal noise and avoidance of kick and settling effects on the element (e.g., transistor Q).

(15) FIG. 4 is a timing diagram illustrating operation of the sensor 500 of FIG. 3 in accordance with embodiments of the present disclosure. The timing diagram illustrates operation of switch 1, switch 2, and switch 3 over a clock cycle. The clock signals that control switches 1, 2, and 3 are shown as signals CLK1, CLK2, and CLK3, respectively, with a high value indicating a closed switch and a low value indicating an open switch. The timing diagram also illustrates the states of two-state current sources I.sub.in and I.sub.b and voltage V.sub.ref_adc over the clock cycle. In one embodiment, current I.sub.b has opposite polarity to current I.sub.in.

(16) At the beginning of a first phase of the clock cycle: switch 1 closes which bypasses feedback capacitor C.sub.f and makes gain stage 4 a unity-gain stage; switch 2 remains open since it is not yet time for the ADC to sample the output of gain stage 4; switch 3 remains open since it is not yet time for the ADC to convert the input voltage V.sub.in_adc; current I.sub.in transitions from low state I.sub.1 to high state I.sub.2; and current I.sub.b transitions from high state I.sub.b2 to a low state I.sub.b1. The increase of current I.sub.in from the low state I.sub.1 to the high state I.sub.2 causes the voltage V.sub.BE to increase to voltage value V.sub.BE2, which charges capacitor C.sub.s with a charge value Q.sub.C.sub.s.sub.CLK1, and which causes reference voltage V.sub.ref_adc to rise as shown. In FIG. 4, the level of V.sub.ref_adc while high state current I.sub.2 is pumped into transistor Q is shown as V.sub.BE2*A, where A is the scaling factor applied to voltage V.sub.BE by stage 5 and resistors R1 and R2 to generate V.sub.ref_adc. The reduction of current I.sub.b to the low state I.sub.b1 causes voltage V.sub.b to decrease to a voltage referred to as V.sub.b1, which charges capacitor C.sub.b with a charge value Q.sub.C.sub.b.sub.CLK1.

(17) At the beginning of a second phase of the clock cycle (e.g., approximately twenty percent into the clock cycle), which may be referred to as the ADC sampling phase: switch 1 opens which allows charge stored on capacitors C.sub.s and C.sub.b to transfer to capacitor C.sub.f, switch 2 closes enabling the ADC to sample its input voltage V.sub.in_adc (i.e., the output voltage V.sub.o of gain stage 4), switch 3 remains open, current I.sub.in transitions from high state I.sub.2 to low state I.sub.1, and current I.sub.b transitions from low state I.sub.b1 to high state I.sub.b2. The decrease of current I.sub.in from the high state I.sub.2 to the low state I.sub.1 causes the voltage V.sub.BE to decrease from voltage value V.sub.BE2 to voltage value V.sub.BE1, which charges capacitor C.sub.s with a charge value Q.sub.C.sub.s.sub.CLK2 that is less than charge value Q.sub.C.sub.s.sub.CLK1, and which causes reference voltage V.sub.ref_adc to drop as shown. In FIG. 4, the level of V.sub.ref_adc while low state current I.sub.1 is pumped into transistor Q is shown as V.sub.BE1*A. The increase of current I.sub.b to the high state I.sub.b2 causes voltage V.sub.b to increase to voltage V.sub.b2, which charges capacitor C.sub.b with a charge value Q.sub.C.sub.b.sub.CLK2 which is greater than charge value Q.sub.C.sub.b.sub.CLK1.

(18) At the beginning of a third phase of the clock cycle (e.g., approximately forty percent into the clock cycle), which may be referred to as the ADC conversion phase: switch 1 remains open, switch 2 opens, and shortly after switch 3 closes enabling the ADC to receive reference voltage V.sub.ref_adc for use in converting its analog input voltage V.sub.in_adc to digital output D.sub.out. Near the end of the clock cycle, switch 3 opens.

(19) The change in voltage ΔV.sub.b has the effect of DC shifting down the output of gain stage 4. The DC down shift may facilitate gain up of ΔV.sub.BE. The gain up of ΔV.sub.BE facilitated by the DC down shift may advantageously boost the dynamic range of output voltage V.sub.o of gain stage 4 and thereby increase the accuracy of the temperature output D.sub.out.

(20) Operation of the sensor 500 may be further understood by reference to equations (2) through (6) which will now be described.

(21) $\begin{array}{cc}\mathrm{CLK}1\{\begin{array}{c}{Q}_{C_{s}CLK1}=C_s.Math.\left\{V_{BE2}-\left(V_{CM}+V_{os}\right)\right\}\\ Q_{C_{b}CLK1}=C_b.Math.\left\{V_{b1}-\left(V_{CM}+V_{os}\right)\right\}\\ Q_{C_{f}CLK1}=C_f.Math.\left\{\left(V_{CM}+V_{os}\right)-0\right\}\end{array}& \left(2\right)\\ \mathrm{CLK}2\{\begin{array}{c}{Q}_{C_s\mathrm{CLK}2}=C_s.Math.\left\{V_{BE1}-\left(V_{CM}+V_{os}\right)\right\}\\ Q_{C_b\mathrm{CLK}2}=C_b.Math.\left\{V_{b2}-\left(V_{CM}+V_{os}\right)\right\}\\ Q_{C_{f}CLK2}=C_f.Math.\left\{\left(V_{CM}+V_{os}\right)-V_O\right\}\end{array}& \left(3\right)\\ \Delta Q_{C_f}=\Delta Q_{C_s}+\Delta Q_{C_b}.Math.& \left(4\right)\\ C_f.Math.\left\{\left(\left(V_{CM}+V_{os}\right)-V_O\right)-\left(\left(V_{CM}+V_{os}\right)-0\right)\right\}=C_s.Math.\left\{\left(V_{BE1}-\left(V_{CM}+V_{os}\right)\right)-\left(V_{BE2}-\left(V_{CM}+V_{os}\right)\right)\right\}+C_b.Math.\left\{\left(V_{b2}-\left(V_{CM}+V_{os}\right)\right)-\left(V_{b1}-\left(V_{CM}+V_{os}\right)\right)\right\}& \left(5\right)\\ V_O=\frac{c_s}{c_f}.\left(V_{BE2}-V_{BE1}\right)-\frac{c_b}{c_f}.Math.\left(V_{b2}-V_{b1}\right)=\frac{c_s}{c_f}.Math.\Delta V_{BE}-\frac{c_b}{c_f}.Math.\Delta V_b& \left(6\right)\end{array}$

(22) In equations (2) and (3), CLK1 and CLK2 refer respectively to the first and second phases of the clock cycle of FIG. 4. That is, during CLK1: switch 1 is closed, switch 2 and switch 3 are open, current I.sub.in is high at I.sub.2, and current I.sub.b is low at I.sub.b1; during CLK2: switch 1 and switch 3 are open, switch 2 is closed, current I.sub.in is low at I.sub.1, and current I.sub.b is high at I.sub.b2. Q.sub.C.sub.s.sub.CLK1, Q.sub.C.sub.b.sub.CLK1, and Q.sub.C.sub.f.sub.CLK1 are the respective charges on capacitors C.sub.s, C.sub.b, and C.sub.f during CLK1, and Q.sub.C.sub.s.sub.CLK2, Q.sub.C.sub.b.sub.CLK2, and Q.sub.C.sub.f.sub.CLK2 are the respective charges on capacitors C.sub.s, C.sub.b, and C.sub.f during CLK2. V.sub.OS is an input offset voltage to gain stage 4.

(23) Equation (4) describes the charge relationship of capacitors C.sub.s, C.sub.b and C.sub.f between CLK1 and CLK2. ΔQ.sub.C.sub.f, ΔQ.sub.C.sub.s, and ΔQ.sub.C.sub.b are the respective differences in charge on capacitors C.sub.f, C.sub.s, and C.sub.b from CLK1 to CLK2. Equation (5) further expresses the relationship of equation (4) substituting the values of equations (2) and (3), and equation (6) is the solution of equation (5). As shown in equation (6), the output voltage V.sub.o of gain stage 4 is the change in the voltage ΔV.sub.BE of the element (e.g., transistor Q) multiplied by the gain that is the ratio of C.sub.s to C.sub.f, with a DC down shift accomplished by the continuous DC shifting branch, which is the change in the voltage ΔV.sub.b of the pull-down resistor R.sub.b multiplied by the gain that is the ratio of C.sub.b to C.sub.f.

(24) Advantageously, sensor 500 is absent sampling switches. Sensor 500 operates to pass temperature information (e.g., ΔV.sub.BE) through capacitor C.sub.s with no switching, and the dynamic DC shifting value ΔV.sub.b passes through capacitor C.sub.b with no switching, reducing the switching noise and the number of switches over conventional sensors. Furthermore, during the ADC sampling phase, the output V.sub.o of gain stage 4 gets a DC shift down. The DC shift down allows ΔV.sub.BE to be further gained up by C.sub.s/C.sub.f. The absence of sampling switches and the further signal gain up advantageously boosts the dynamic range of the output voltage V.sub.o. Another advantage of sensor 500 is that it does not require a ZTC reference voltage. Instead, the reference voltage (e.g., V.sub.ref_adc) is generated internally. Sensor 500 also advantageously does not require differential sampling. Sensor 500 only requires a single element and does not require matching of elements. Finally, sensor 500 provides high temperature detection accuracy with low noise and higher signal level, very low process sensitivity, and very low power consumption.

(25) It should be understood—especially by those having ordinary skill in the art with the benefit of this disclosure—that the various operations described herein, particularly in connection with the figures, may be implemented by other circuitry or other hardware components. The order in which each operation of a given method is performed may be changed, unless otherwise indicated, and various elements of the systems illustrated herein may be added, reordered, combined, omitted, modified, etc. It is intended that this disclosure embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense.

(26) Similarly, although this disclosure refers to specific embodiments, certain modifications and changes can be made to those embodiments without departing from the scope and coverage of this disclosure. Moreover, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element.

(27) Further embodiments likewise, with the benefit of this disclosure, will be apparent to those having ordinary skill in the art, and such embodiments should be deemed as being encompassed herein. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art and are construed as being without limitation to such specifically recited examples and conditions.

(28) This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.