TIMING CIRCUIT FOR LOCKING A VOLTAGE CONTROLLED OSCILLATOR TO A HIGH FREQUENCY BY USE OF LOW FREQUENCY QUOTIENTS AND RESISTOR TO SWITCHED CAPACITOR MATCHING

Abstract

Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.

Claims

1. A circuit, locking a voltage controlled oscillator at a high frequency, comprising: a voltage controlled oscillator (VCO); and an integrator operable to generate and output a control signal to the VCO; wherein the integrator is operable to receive an inverting signal and a reference signal; wherein the control signal locks the VCO to a high frequency signal based upon the inverting signal; wherein the inverting signal is received in response to a low frequency signal; and wherein the low frequency signal is a quotient of the high frequency signal.

2. The circuit of claim 1, further comprising: a frequency divider, coupled to the VCO, operable to: receive the high frequency signal from the VCO; divide the high frequency signal by a factor “F”; and output, based on the dividing of the high frequency signal, the low frequency signal.

3. The circuit of claim 2, wherein the frequency divider further comprises: two or more flip-flop stages operable to successively divide the high frequency signal into the low frequency signal.

4. The circuit of claim 3, wherein the low frequency signal has a given period Ta; and wherein during the given period T.sub.FL, ripples are generated by the integrator in the control signal and the VCO generates jitter in a frequency of the high frequency signal.

5. The circuit of claim 4, wherein the jitter distributes the high frequency signal over a wider frequency band; and wherein an amplitude of an individual frequency component of the high frequency signal is reduced.

6. The circuit of claim 2, wherein F equals thirty-two.

7. The circuit of claim 1, wherein a period of the low frequency signal is generated as a given number of periods of the high frequency signal (T.sub.FH); wherein the low frequency signal has a given period T.sub.FL; and wherein the circuit further comprises: a frequency divider operable to output the low frequency signal; and a switched capacitor resistor circuit (SCRC), coupled to the frequency divider and the integrator, operable to: receive the low frequency signal from the frequency divider; and based on a frequency of the low frequency signal, generates the inverting signal.

8. The circuit of claim 1, further comprising: a switched capacitor resistor circuit (SCRC) coupled to the integrator; wherein the SCRC is operable to: receive the low frequency signal; generate, in response to a frequency of the low frequency signal, the inverting signal by: during a first phase of a given period T.sub.FL of the low frequency signal, coupling a switched capacitor to a ground potential; and charging the switched capacitor by a second reference signal; and during a second phase of the given period T.sub.FL of the low frequency signal, coupling the switched capacitor to the integrator; and outputting the inverting signal to the integrator; wherein the inverting signal comprises an inverting voltage signal and an inverting current signal; and wherein the integrator is operable to: force the inverting voltage signal to equal the reference signal; and wherein the inverting current signal results in the integrator generating the control signal.

9. The circuit of claim 8, wherein the integrator further comprises: an op-amp further comprising: an inverting node; a non-inverting node; and an output node; and an integrating capacitor coupled to the non-inverting node; wherein the integrating capacitor has an integrator capacitance; wherein the switched capacitor has a switched capacitance; wherein the VCO is coupled to the output node; wherein the inverting signal further comprises an inverting voltage signal and an inverting current signal; and wherein the inverting voltage signal is provided at the inverting node; wherein, during the second phase, the inverting current signal charges the integrating capacitor; wherein the reference signal is provided at the non-inverting node; wherein the reference signal equals the second reference signal; wherein the reference signal is generated from a supply voltage; and wherein the control signal is generated based upon a product of the supply voltage times the switched capacitance and the product being divided by the integrator capacitance.

10. The circuit of claim 9, wherein the SCRC further comprises: a first switch for selectively coupling a top terminal of the switched capacitor, via a terminal A, to a ground potential, and via a terminal B, to the supply voltage; a second switch for selectively coupling a bottom terminal of the switched capacitor, via a terminal C, to the integrator and via a terminal D, to a reference circuit; and a discharge resistor R coupled at a bottom terminal to ground and at a top terminal to the inverting node and to terminal C of the second switch; wherein the reference circuit further comprises: a first reference resistor coupled between the supply voltage and to the non-inverting node; and a second reference resistor coupled between the non-inverting node and the ground; and wherein during the first phase of the given period T.sub.FL, a discharge current flows from the integrating capacitor to ground via the discharge resistor R.

11. A circuit comprising: a voltage controlled oscillator; a reference circuit; an integrator comprising: an op-amp comprising: an inverting node; a non-inverting node coupled to the reference circuit; and an output node coupled to the VCO; and an integrator capacitor coupled to the non-inverting node and the output node; a switched capacitor resistor circuit (SCRC) comprising: a first switch including a terminal A and a terminal B; a second switch including a terminal C and a terminal D; a switched capacitor coupled the first switch and the second switch; wherein the switched capacitor has a top terminal and a bottom terminal and is selectively coupled: at the top terminal,  to a ground potential, when the first switch selects terminal A; and  to a supply voltage, when the first switch selects terminal B; at the bottom terminal,  to the inverting node when the second switch selects terminal C; and  to the reference circuit when the second switch selects terminal D; a discharge resistor coupled between the ground potential and the inverting node; wherein a given period Ta for a low frequency signal includes a first phase followed by a second phase; wherein during the first phase of the given period T.sub.FL, the first switch selects terminal A; the second switch selects terminal D; charges received during a prior operating cycle from the SCRC and stored in the integrator capacitor are discharged to ground via the discharge resistor; and wherein during the second phase of the given period T.sub.FL, the first switch selects terminal B; next, the second switch select terminal C; an inverting signal generated by the SCRC charges the integrator capacitor; wherein charging and discharging of the integrator capacitor results in the integrator generating an integrated signal; wherein the integrated signal is used to generate a control signal provided to the VCO; and wherein based on the control signal, the VCO is locked to and outputs a high frequency signal.

12. The circuit of claim 11, further comprising: a frequency divider, coupled to the VCO and the SCRC; and wherein the frequency divider generates the low frequency signal based on the high frequency signal received from the VCO.

13. The circuit of claim 12, wherein the frequency divider further comprises: “N” flip-flop stages, operable to successively divide the high frequency signal; and wherein, the integrator is operable to generate ripples in the control signal; and wherein, based on the ripples in the control signal, the VCO is operable to generate jitter in a frequency of the high frequency signal.

14. The circuit of claim 13, wherein N equals five stages; wherein the ripples in the control signal are approximately fifteen millivolts (15 mV) peak-to-peak; and wherein the jitter in the frequency of the high frequency signal is approximately fifteen megahertz (15 MHz).

15. The circuit of claim 12, further comprising: a filter operable to: receive the integrated signal from the integrator; filter the integrated signal to generate the control signal; and output the control signal to the VCO.

16. The circuit of claim 11, wherein the reference circuit further comprises: a first reference resistor; a second reference resistor; a third reference resistor; and a fourth reference resistor; wherein a Wheatstone bridge is formed by: a first divider string comprising a switched capacitor resistor coupled to the discharge resistor; a second divider string comprising the first reference resistor and the second reference resistor; wherein the second divider string generates a reference signal; wherein the reference signal is provided to the non-inverting node; wherein the Wheatstone bridge seeks equilibrium between the first divider string and the second divider string; wherein when terminal C is selected by the second switch, an inverting voltage signal charges the integrator capacitor; and wherein when equilibrium does not exist in the Wheatstone bridge, an inverting current signal is provided to the integrator capacitor in the inverted signal.

17. The circuit of claim 16, wherein during the first phase, a third divider string, comprising the third reference resistor and the fourth reference resistor, supply a second reference signal to the switched capacitor resistor; and wherein the second reference signal pre-charges the switched capacitor.

18. The circuit of claim 12, wherein a period of the low frequency signal is proportional to a resistance of the discharge resistor times a capacitance of the switched capacitor.

19. A method, of controlling a voltage controlled oscillator to a high frequency, comprising: generating a low frequency signal based on a high frequency signal; wherein the high frequency signal is generated by a voltage controlled oscillator; selectively generating inverting signals based on the low frequency signal; and generating, based on the inverting signals, a control signal used to control the voltage controlled oscillator.

20. The method of claim 19, wherein the low frequency signal is generated by a frequency divider; wherein the inverting signal is generated by a switched capacitor to resistor circuit comprising a switched capacitor and a discharge resistor; wherein the inverting signal is controlled by: selectively switching a first switch coupling a top terminal of the switched capacitor between a supply voltage and a ground potential; and selectively switching a second switch coupling a bottom terminal of the switched capacitor between a reference circuit and an inverting node of an integrator; wherein the low frequency signal occurs over a given period T.sub.FL that includes at least two phases; wherein the selective switching of the first switch and the second switch occurs based on a then occurring phase for the given period T.sub.FL; wherein the control signal is further generated based upon a reference signal provided by the reference circuit to the integrator; wherein ripples are generated in the control signal by the integrator; and wherein, based on the ripples, jitter is generated in a frequency of the high frequency signal by the voltage controlled oscillator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The features, aspects, advantages, functions, modules, and components of the devices, systems and processes provided by the various embodiments of the present disclosure are further disclosed herein regarding at least one of the following descriptions and accompanying drawing figures. In the appended figures, similar components or elements of the same type may have the same reference number and may include an additional alphabetic designator, such as 108a-108n, and the like, wherein the alphabetic designator indicates that the components bearing the same reference number, e.g., 108, share common properties and/or characteristics. Further, various views of a component may be distinguished by a first reference label followed by a dash and a second reference label, wherein the second reference label is used for purposes of this description to designate a view of the component. When the first reference label is used in the specification, the description is applicable to any of the similar components and/or views having the same first reference number irrespective of any additional alphabetic designators or second reference labels, if any.

[0026] FIG. 1 is a schematic illustration of a timing circuit for locking a VCO output frequency at a high frequency using low frequency quotients and a switched capacitor to resistor matching circuit and in accordance with at least one embodiment of the present disclosure.

[0027] FIG. 2 is another schematic illustration of a timing circuit for locking a VCO at a high frequency using low frequency quotients and a switched capacitor to resistor circuit and in accordance with at least one embodiment of the present disclosure.

[0028] FIG. 3A is a graphical representation of an integrated signal V.sub.IS generated by an integrator in the timing circuit of FIG. 2 and in accordance with at least one embodiment of the present disclosure.

[0029] FIG. 3B is a graphical representation of a control signal V.sub.C generated by a filter in the timing circuit of FIG. 2 and in accordance with at least one embodiment of the present disclosure.

[0030] FIG. 3C is a graphical representation of the frequency of the high frequency signal FH generated by a VCO in the timing circuit of FIG. 2 and in accordance with at least one embodiment of the present disclosure.

[0031] FIG. 3D is a graphical representation of the high frequency signal FH of FIG. 3C, as represented in a voltage over time domain, and as generated the VCO of the timing circuit of FIG. 2 and in accordance with at least one embodiment of the present disclosure.

[0032] FIG. 3E is a graphical representation of a low frequency signal LH generated by a divider in the timing circuit of FIG. 2 and in accordance with at least one embodiment of the present disclosure.

[0033] FIG. 3F is an enlargement of the graphical representation provided in FIG. 3C.

DETAILED DESCRIPTION

[0034] The various embodiments described herein are directed to timing circuits for generating high frequency timing signals. For at least one embodiment a timing circuit may be configured to lock a VCO to a high frequency. By using a high frequency, such as a frequency above one-hundred megahertz (100 MHz), voltage spikes that might otherwise result in undesired electromagnetic radiation (“EMR”) may be avoided. EMR will commonly fall outside operating ranges for a vehicle or other device within which a CAN is being used. For at least one embodiment, the circuits and methods may be used in a timing circuit to generate, by a VCO, timing signals in the three-hundred megahertz (300 MHz) to four-hundred megahertz (400 MHz) range. For at least one embodiment, timing signals are generated that have a substantially center frequency of three-hundred and thirty-three megahertz (333 MHz). For at least one embodiment, the timing signals generated by the VCO locked to provide a high frequency output signal, may be used by a transceiver to generated a transmitted signal containing one or more Data/“symbols” over a CAN. The high frequency output signal generated by a VCO locked to so provide may be used with other implementations and are not limited to use with CANs.

[0035] As shown in FIG. 1 and for at least one embodiment of the present disclosure, a timing circuit 100 may include a frequency divider circuit 102, a switched capacitor to resistor circuit (SCRC) 104, a reference circuit 106, an integrator 108, an optional filter 110, and a VCO 112.

[0036] The VCO 112 receives a control signal V.sub.C. V.sub.C may be received from the filter 110 (when the filter 110 is separately provided) or from the integrator 108 (when the filter 110 is not separately provided). It is to be appreciated that functions performed by the filter 110 may be provided by the integrator 108 or separately.

[0037] Based on the received control signal V.sub.C, the VCO 112 generates a high frequency signal/timing signal “FH.” FH is generated by the VCO based on the voltages received in the control signal V.sub.C. The high frequency signal FH may be output as a timing signal for use by other devices in a given implementation, such as in a given CAN implementation. The terms high frequency signal FH may be used as a timing signal, and such terms are used interchangeably herein. FH is also provided to the frequency divider circuit 102. The principles of operation of VCOs are well known and are not otherwise described herein. Any known or later arising VCO technology may be used in implementations of the various embodiments described herein.

[0038] In FIGS. 3C and 3F, an illustrative and non-limiting representation of the high frequency signal FH is shown. The FH generally includes a symmetrical, repeating waveform that has a peak center frequency and multiple ripples. The high frequency signal FH is shown as arising over a bandwidth of approximately three-hundred and thirty-five megahertz (335 MHz) to three-hundred and fifty megahertz (350 MHz). Other ranges may be used for other embodiments. In FIG. 3D, an illustrative and non-limiting representation of output voltages generated by the VCO in the FH are shown. The output voltages form a quasi-square wave with a frequency of approximately three-hundred and thirty-three megahertz (333 MHz). For this non-limiting example, the voltage ranges from zero volts (0V) to approximately three-point-three volts (3.3V).

[0039] As further shown in FIG. 1, a frequency divider circuit 102 (which is also referred to herein in short as the “divider”) divides the high frequency signal FH into a lower frequency signal FL. The division of the high frequency signal FH into the low frequency signal FL may occur using any number “N” of stages. The number of stages used by a given divider 102 is implementation specific. For at least one implementation, five (5) stages are used for a FH signal generated in the 300-400 MHz range, such stages result in an FL generated that ranges from approximately ten megahertz (10 MHz) to approximately thirteen megahertz (13 MHz). FL is output by the frequency divider circuit 102 and is used as a control/drive signal for the SCRC 104. The number of stages N may specify a factor F at which the high frequency signal FH is divided into the low frequency signal FL. For at least one embodiment, F=2.sup.N.

[0040] In FIG. 3E, an illustrative and non-limiting representation of the low frequency signal FL is shown. As shown, FL is a square wave signal that toggles between zero volts (0V) and approximately three-point-three volts (3.3V), with a frequency of approximately ten megahertz (10 MHz) and a period of approximately one-hundred nanoseconds (100 ns).

[0041] As further shown in FIG. 1, the SCRC 104 is configured to receive the FL signal and a supply voltage V.sub.DD. Based on the pulses received in the FL signal and the electrical potential provided by V.sub.DD, the SCRC 1014 generates and outputs an inverted signal to the integrator 108. The inverted signal has a voltage component V.sub.INV (which is also referred to as the “inverting voltage signal”) and a current component I.sub.INV (which is also referred to as the “inverting current signal”). V.sub.INV is provided as an inverting signal to the integrator 108. The reference circuit 106 also is provided with electrical energy by the supply voltage V.sub.DD.

[0042] The reference circuit 106 generates a reference signal V.sub.REF (which is also referred to as the “non-inverting signal”) which is provided to the integrator 108. A second reference signal V.sub.REF2 is also generated and, for at least one embodiment, is substantially equal to the reference voltage V.sub.REF. Based on the received inverting and non-inverting signals, the integrator generates and outputs an integrated signal V.sub.IS.

[0043] In FIG. 3A, an illustrative and non-limiting representation of the integrated signal V.sub.IS is shown. As shown, the integrated signal provides a symmetrical, repeating waveform that includes voltages varying over time and over a range of approximately one-point-one volts (1.1V) to one-point-three volts (1.3). Other voltage ranges may be used for other embodiments. If left unfiltered, it is to be appreciated that the voltage spikes present in the integrated signal V.sub.IS may result in corresponding spikes in the voltages and frequencies generated in the high frequency signal FH by the VCO.

[0044] As shown in FIG. 1, the integrated signal V.sub.IS is filtered by filter 110. As shown in FIG. 3B, filtering of the integrated signal VIS may result in a control signal V.sub.C that avoids sharp voltage spikes while containing numerous voltage ripples.

[0045] Referring again to FIG. 1, with the providing of the control signal V.sub.C to the VCO, a regulation loop is provided which facilitates settling of the timing circuit 100 upon a center high frequency FH signal having multiple frequency jittering and where the center of the high frequency signal FH is based upon the RC values used in the SCRC 104. Also, one or more of the components of the timing circuit 100 may be suitably grounded or otherwise connected to a ground/common potential 114 (“GND”).

[0046] For at least one embodiment, the VCO may be locked to a high frequency signal FH by adjusting one or more of the number of low frequency FL quotients used, as specified by the number of stages “N” used, and/or by tuning the SCRC, such as by adjusting the resistance provided by one or more resistors in the SCRC.

[0047] Further, it is to be appreciated that due to the varying voltage levels provided in the control signal V.sub.C, iterative frequency corrections are performed by the VCO. These iterative corrections result in the ripples in the control signal V.sub.C and the jitters in a frequency of the high frequency signal FH. The frequency jittering enables the timing signal to be distributed across a wider bandwidth and thereby reduce effects of any higher order harmonics, or the like. Further, the voltage rippling in the control signal V.sub.C may occur independently of variations in temperature, the supply voltage V.sub.DD, or the like. Any such variations will have minimum influence on the control signal V.sub.C and correspondingly on the high frequency signal FH. For at least one embodiment, rippling in the control signal V.sub.C may result in a timing signal having an energy distribution over a given frequency range, while being centered at a given operating frequency. The amount of rippling in the control voltage V.sub.C may be reduced or increased based upon the characteristics of the integrator 108 used for a given embodiment. Further, the jittering of the high frequency signal FH may result in a lower total power generated by a transmitter in a given frequency band. This, in turn, may result in greater receptivity by a receiving device due to less noise being present in the transmitted signals.

[0048] For at least one embodiment, a timing circuit may be configured to use wave shaping to generate timing signals that rise and fall within specified ranges. Such wave shaping may occur, for example, in view of the number of stages used in a divider 102. For example and not by limitation, a particular implementation of a CAN may have a range of transmitted signals which include rising edges occurring at approximately sixty nanoseconds (60 ns), with falling edges occurring at approximately one-hundred and twenty nanoseconds (120 ns). Other CAN implementations may use similarly symmetrical rising and falling edges, such as rising edges occurring between sixty nanoseconds (60 ns) and eighty nanosecond (80 ns) and falling edges occurring between one-hundred and twenty nanoseconds (120 ns) and one-hundred and sixty nanoseconds (160 ns) for a full period. For a given implementation, the divider 102 may be operable, based on a single period of FH, to accordingly generate a number of low frequency periods (herein, “Z periods”). Twenty (20) to thirty (30) Z periods may be generated over a half-period, and forty (40) to sixty (60) Z periods may be generated over a full period. Other ranges and/or numbers of Z periods may be used for other implementations. It is to be appreciated that as the number of Z periods increases, the amount of any error generated in a given timing signal will decrease. An increase in the number of Z periods used may result in an increase in a larger VCO. An increase in VCO size may have undesired space, heat, power, and other consequences.

[0049] The number of Z periods generated by the divider 102 based on a given high frequency signal FH may further relate to the frequency ranges to be used in a given transmitted signal. For example, if twenty (20) Z periods are to be used and a given period for the transmitted signal is sixty nanoseconds (60 ns), which corresponds to an operating frequency of 16.6 MHz, a transmitted period (herein, an “Xtr period”) may be generated over three nanoseconds (3 ns), and a timing signal generated at approximately three-hundred and thirty-three megahertz (333 MHz) may be used to provide the given number of Xtr periods, here, twenty (20) to be used by a transceiver in shaping the transmitted signal used, for example and not by limitation, on a CAN. It is to be appreciated, however, that twenty (20) Xtr periods over a full period provides only ten (10) Xtr periods to form a given rising edge or a given falling edge of a transmitted signal. Accordingly, implementations may be configured to use higher numbers of Xtr periods, over a given period or portion thereof, such that a transmitted signal will be shaped and have a given form, such as a well-formed rising edge, a well-formed falling edge, and/or both.

[0050] For an embodiment, a timing circuit may be used that generate successive steps, in a timing signal, at speeds that are an order of magnitude greater than a given frequency used for a given transmitted signal. For example, a VCO may be configured to generate timing signals at 333 MHz while a transmitted signal output by a transceiver is at a lower frequency for example, and not by limitation, ten megahertz (10 MHz). The timing circuit may be provided as an on-chip oscillator.

[0051] To generate the timing signal reliably, the various embodiments described herein may be configured to use steps provided in the lower frequency signal FL. FL may be used in generating, by other circuit components, an inverting input signal to an integrator, with a non-inverting input signal to the integrator being provided by a reference circuit, with an integrated signal being generated.

[0052] For at least one embodiment, a timing circuit configured in accordance with an embodiment of the present disclosure may generate a timing signal that has a frequency accuracy of better than five percent (±5%) accurate. For at least one embodiment, the timing circuit used to lock a VCO and generate a higher frequency signal FH may be provided within a core circuit block, such as an IP block.

[0053] During a start-up phase, the timing circuit 100 may use multiple operating cycles before the timing circuit settles upon a given center frequency. Accordingly, to minimize start-up periods and for at least one embodiment, the timing circuit 100 may be provided with the supply voltage V.sub.DD. While powered, the timing circuit 100 may increase a depletion rate of stored electrical energy, such as in devices operating on battery supplied power. Accordingly, it is to be appreciated that the timing circuit 100 may not be an optimal solution when electrical power used to operate the timing circuit 100 uses a supply voltage V.sub.DD provided by a stored or otherwise limited availability power source, such as a battery.

[0054] As shown in FIG. 2 and for at least one embodiment, a timing circuit 200 may include a divider 102 that is further configured to include one (1) to “N” stages 202(1)-202(N), where N is an integer. The N stages successively divide a received high frequency signal FH into a low frequency signal FL. The “N” stages may include use of flip-flops or other components operable to divide the high frequency signal FH into the low frequency signal FL. The low frequency signal FL is provided by the divider 102 to an SCRC 104. For at least one non-limiting embodiment, the low frequency signal FL may range from approximately one-hundred kilohertz (100 kHz) to less than ten megahertz (10 MHz).

[0055] The SCRC 104 may be configured to include at a first SCRS node 203 at which the low frequency signal FL is received from the divider 102. The SCRC 104 may include a first switch S.sub.1 having a terminal A and a terminal B, and a second switch S.sub.2 having a terminal C and a terminal D. The first switch S.sub.1 and second switch S.sub.2 may be configured to have opposing states and are driven by the low frequency signal FL, such that when S1 is at terminal A, S2 is at terminal D and when S1 is at terminal B, S2 is at terminal C. The SCRC 104 may further include a switched capacitor C.sub.S providing a switched capacitance SC, and a discharge resistor R having a first resistance R.sub.S1 and an optional trimming resistance R.sub.S2 and a total discharge resistance R.sub.D. As discussed below, the combination of the first switch S.sub.1, the second switch S.sub.2, and the switched capacitor C.sub.S form a switched capacitor resistor “R.sub.SC” 230.

[0056] The resistor(s) and capacitor used in an SCRC may be stable over temperatures ranging from minus fifty degrees Celsius (−50° C.) to one-hundred and fifty degrees Celsius (150° C.). As used herein, a stable temperature is a temperature that varies less than plus/minus ten percent (±10%) during a normal operating period. It is to be appreciated that the temperature may vary during start-up and shut-down modes of operation. The SCRC 104 and other components of the timing circuit 200 may be configured for use in a three-point-three volt (3.3V) gate transistor environment. The switched capacitor C.sub.S may be configured such that is settles within a given low frequency signal FL period T.sub.FL.

[0057] Further, the use of the low frequency signal FL to drive the SCRC 104 reduces impacts of parasitics occurring in the switches S1 and S2 when such switches are driven above ten megahertz (10 MHz). Also, the low frequency signal FL facilitates generation of ripples in the control signal V.sub.C provided to the VCO, which due to the transfer function of the VCO results in jitter in the high frequency signal FH. For at least one embodiment, and as shown in FIG. 3F, a ripple of fifteen millivolts (15 mV) peak-to-peak results in a jitter of approximately fifteen megahertz (15 MHz) in a frequency of the high frequency signal FH. Other transfer functions in a VCO may be used for other embodiments to provide more or less jitter in frequencies of the high frequency signal based upon ripples in the control signal V.sub.C.

[0058] The first switch S1 switchable connects, via terminal B, a top terminal of the switched capacitor C.sub.S with either a second SCRC node 204, at which a supply voltage V.sub.DD is provided, and via terminal A, connects the top terminal of the switched capacitor C.sub.S with a fifth SCRC node 210 coupled to GND 114. As shown, the switched capacitor C.sub.S may be charged directly from the supply voltage V.sub.DD and without use of a separate reference voltage source. Further, use of the switched capacitor C.sub.S results in a timing circuit 200 which is substantially insensitive to delays arising in the divider 102 when the switched capacitor C.sub.S and the integrator 108 settle correctly. Further, the parasitic capacitances of the switches S1 and S2 may not play a significant role in the accuracy of the regulation loop.

[0059] The second switch S2 switchable connects a bottom terminal of the switched capacitor C.sub.S, via terminal D, with a third SCRC node 206, and via terminal C, with a fourth SCRC node 208. The third SCRC node 206 is coupled to the reference circuit 106. The fourth SCRC node 208 also couples the resistor R to an inverting node 224 for the integrator 108. The inverting voltage signal V.sub.INV occurs at the fourth SCRC node 208. The resistor R is also coupled to GND 114 via the fifth SCRC node 210.

[0060] The timing circuit 200 may include a reference circuit 106 that includes four reference resistors including a first reference resistor R1, a second reference resistor R2, a third reference resistor R3, and a fourth reference resistor R4. Each of the reference resistors have respective top leads and bottom leads. The first and third reference resistors R1/R3 are coupled, at their respective top leads, to the supply voltage V.sub.DD at a first reference circuit node 212. The second and fourth reference resistors R2/R4 are coupled, at their respective bottom leads, to a fourth reference circuit node 218 and thereby to the GND 114. The bottom lead of the third reference resistor R3 and the top lead of the fourth reference resistor R4 are coupled to second reference circuit node 214, which is further coupled to the third SCRC node 206. The bottom lead of the first reference resistor R1 and the top lead of the second reference resistor R2 are coupled to a third reference circuit node 216 which is further coupled to a non-inverting node 222 for the integrator 108.

[0061] The reference signal V.sub.REF occurs at the third reference circuit node 216 and the second reference signal V.sub.REF2 occurs at the second reference circuit node 214. When the second switch S2 couples the switched capacitor C.sub.S to the reference circuit 106, a third divider string, is formed by the third reference resistor R3 and the fourth reference resistor R4. For at least one embodiment, the second reference signal V.sub.REF2 is substantially equivalent to the reference voltage V.sub.REF.

[0062] When connected to the switched capacitor via the second switch S2, the second reference signal V.sub.REF2 pre-charges the switched capacitor C.sub.S to substantially the same voltage present on the inputs to the integrator 108 which is substantially equal to V.sub.REF. Accordingly, V.sub.REF may be mathematically defined per Equation 1.

[00001]$\begin{array}{cc}{V}_{\mathrm{REF}}\cong \frac{V_{\mathrm{DD}}\times R2}{\left(R1+R2\right)}=\frac{V_{\mathrm{DD}}}{2}\left(\mathrm{when}R1=R2\right)& \mathrm{Equation}1\end{array}$

[0063] Further, the resistor R provides a circuit path from an inverting node 224 of the integrator and so from an integrator capacitor C.sub.INT (having an integrator capacitance “IC”) to GND 114 and thereby R removes, over a full period T.sub.FL, a charge (herein, the “removed charge” “Q.sub.R”) out of the integrator capacitor C.sub.INT. It is to be appreciated that the following principles apply:

Q=Current (I.sub.INV)×Period (T.sub.FL);  1)

I.sub.INV=V.sub.REF/SR;  2)

V.sub.REF=V.sub.DD/2;  3)

Q.sub.R=T.sub.FL×(V.sub.REF/SR); and  4)

Q.sub.R=T.sub.FL*(V.sub.DD/2)/SR.  5)

[0064] Accordingly, the charge removed Q.sub.R may be defined per Equation 2.

[00002]$\begin{array}{cc}{Q}_R\cong \frac{T_{\mathrm{FL}}\times V_{\mathrm{DD}}}{2\mathrm{SR}}& \mathrm{Equation}2\end{array}$

[0065] where “T.sub.FL” is the period for a given low frequency signal FL cycle.

[0066] Each T.sub.FL may be split into two switching phases, phase 1 and phase 2. During each period T.sub.FL, the switched capacitor C.sub.S compensates for the removed charge Q.sub.R and V.sub.REF2 provides a pre-charge voltage to the switched capacitor C.sub.S. V.sub.REF2 may be further defined per Equation 3.

[00003]$\begin{array}{cc}{V}_{\mathrm{REF}2}\cong \frac{V_{\mathrm{DD}}\times R1}{\left(R3+R4\right)}=\frac{V_{\mathrm{DD}}}{2}\left(\mathrm{when}R3=R4,\mathrm{and}\mathrm{when}R4\mathrm{is}\mathrm{grounded}\right)& \mathrm{Equation}3\end{array}$

[0067] During a first phase in period T.sub.FL, the switched capacitor C.sub.S is coupled via S1, terminal A to GND 114 and via S2, terminal D to the reference circuit 106. During this first phase, the switched capacitor C.sub.S is charged to a phase 1 voltage (“V.sub.CSPHASE1”). The phase 1 voltage may by defined per Equation 4.

V.sub.CSPHASE1=GND−V.sub.REF2  Equation 4:

[0068] Accordingly, during phase 1, a charge on the switched capacitor CS, (“Q.sub.CS1”) may be defined per Equation 5.

Q.sub.CS1=−SC*V.sub.REF2.  Equation 5:

[0069] During a second phase in period T.sub.FL, C.sub.S is coupled, via S1, terminal B, to V.sub.DD and, via S2, terminal C to the fourth SCRC node 208, at which V.sub.INV is provided to the integrator 108. Since the op-amp 220 forces the inverting input 226 equal to the non-inverting input 227, after settling, V.sub.INV=V.sub.REF. Accordingly, a charge on switched capacitor during phase 2, (“Q.sub.CS2”) may be defined per Equation 6.

Q.sub.CS2=SC*(V.sub.DD−V.sub.REF).  Equation 6:

[0070] Accordingly, the total charge delivered by the switched capacitance C.sub.S (“Q.sub.T”) may be defined per Equation 7.

Q.sub.T=Q.sub.cs2−Q.sub.cs1.  Equation 7:

[0071] Since V.sub.REF2≈V.sub.REF, over a single period T.sub.FL, the total charge Q.sub.T is delivered by the switched capacitor C.sub.S to the inverting node 224 of the integrator 108 and is transferred to the integrator capacitor C.sub.INT. Q.sub.T may be defined by Equation 8.

Q.sub.T=SC*V.sub.DD.  Equation 8:

[0072] To avoid losing part of the I.sub.CS charge provided to the switched capacitor C.sub.S during phase 1, phase 2 may include a sub-phase 2A, during which S2 is switched from terminal C to terminal D, and then a sub-phase 2B, during which S1 is switched from terminal A to terminal B.

[0073] At the end of each period T.sub.FL, a charge on the integrator capacitor Q.sub.INT may be defined per Equation 9.

Q.sub.INT=Q.sub.R−(Q.sub.CS2−Q.sub.CS1)  Equation 9:

[0074] Accordingly, the regulation loop settles when the voltage of the integrated signal (V.sub.IS) stabilizes. Such stabilization occurs at the end of each low frequency period T.sub.FL and may be measured as a DC component when the condition of Equation 10 exists.

Q.sub.R=(Q.sub.CS2−Q.sub.CS1).  Equation 10:

[0075] When the regulation loop settles, the relationship between the period T.sub.FL and the switched capacitance SC and the discharge resistance R.sub.D may be defined by Equations 11 and 12.

SC*V.sub.DD=T.sub.FL*V.sub.DD/2R.sub.D  Equation 11:

T.sub.FL=2*SC*R.sub.D.  Equation 12:

[0076] It is to be appreciated that Equation 12 can be derived based on Equations 2, 8, 10 and 11. Accordingly, when the regulation loop is not yet settled and the low frequency signal FL is too low, T.sub.FL will be too high (and vice versa). After each period T.sub.FL and per Equation 13 below, an increase (or a respective decrease) in the charge Q.sub.INT on the integrator capacitor C.sub.INT which result in an increase (or a respective decrease) in the control signal V.sub.C that further results in an increase (or a respective decrease) in the high frequency signal FH until an equilibrium is reached at the correct T.sub.FL. Such equilibrium will be reached when the filter 110 and the overall gain of the timing circuit 200 are properly chosen, for example, based on experimental results, simulation, or otherwise using known procedures.

Q.sub.INT=(T−(2*SC*R.sub.D))*V.sub.DD/R.sub.D  Equation 13:

[0077] At the end of phase 2, phase 1 is resumed by the timing circuit 200 executing, in sequence, a sub-phase 1A, during which the first switch S1 is switched from terminal B to terminal A, and a sub-phase 1B, during which S2 is switched from terminal C to terminal D. When the switches S1 and S2 states are reversed, phase 1 commences for a next operating cycle and the switch capacitor C.sub.S is again recharged to its initial charge by V.sub.REF2.

[0078] A Wheatstone bridge (the “Bridge”) facilitates regulation of the charge Q.sub.INT in the integrator capacitor C.sub.INT by use of the combination of the switching capacitor resistor R.sub.SC with the discharge resistor R in relation to the reference voltage V.sub.REF. By switching S1 between GND and the supply voltage V.sub.DD, it is to be appreciated that the integrator 108 is insensitive to variations in V.sub.DD. In contrast, were the first switch S1 alternatively designed to be switched between V.sub.REF and the supply voltage V.sub.DD, the integrator 108 may be sensitive to variations in the supply voltage V.sub.DD.

[0079] More specifically, the Bridge includes a first divider string formed by the switched capacitor resistor R.sub.SC and the discharge resistor R, and a second divider string formed with the first reference resistor R1 and the second reference resistor R2.

[0080] When the low frequency signal FL is generated in the one-hundred kilohertz (100 kHz) to twelve megahertz (12 MHz) range (as may occur during a start-up or resumption of the timing circuit 200), the switched capacitor resistor R.sub.SC provides a switched capacitor resistor resistance “R.sub.SCR”. R.sub.SCR is proportional to the low frequency signal FL and to the switched capacitance SC—as mathematically expressed per Equation 14.

[00004]$\begin{array}{cc}{R}_{\mathrm{SCR}}\cong \frac{1}{\mathrm{FL}\times \mathrm{SC}}& \mathrm{Equation}14\end{array}$

[0081] By using, at the first switch S1, the supply voltage V.sub.DD and GND as reference voltages, during start-up, the switched capacitor C.sub.S will have half the expected value. This results in a low ohmic source for both voltage references at the first switch S1. Accordingly, an extra reference buffer may not be needed.

[0082] Further, the Bridge compares the voltages between the first and second divider strings and seeks an equilibrium. Such equilibrium arises when R1 versus R2 has the same voltage potential as R.sub.SCR versus R.sub.D.

[0083] If the Bridge is not in equilibrium and is not connected to the integrator 108, a voltage error (“V.sub.ERROR”) will arise. When the Bridge is connected to the integrator 108, the voltage error V.sub.ERROR is regulated by the integrator 108 towards zero volts (0V). The op-amp 220 and the integrator capacitor C.sub.INT form a feedback loop between the output node 228 and the inverting node 224 which draws the error current out of the Bridge. Such error current is integrated by the integrator capacitor C.sub.INT and results in a change in the integrated signal V.sub.IS. Accordingly, an equivalent current is effectively formed which may be defined by Equation 15.

[00005]$\begin{array}{cc}\frac{V_{\mathrm{ERROR}}}{\left(R.Math..Math.\left(\frac{1}{2\times \mathrm{SC}\times \mathrm{FL}}\right)\right)}=I_{\mathrm{INV}}& \mathrm{Equation}15\end{array}$

[0084] Further, in view of Equation 12, the low frequency signal FL used and the period T.sub.FL, the low frequency signal FL and the high frequency signal FH may be mathematically expressed, in terms of the discharge resistance R.sub.D and the switched capacitance SC, as per Equation 16.

[00006]$\begin{array}{cc}\mathrm{FL}\cong \frac{1}{2\times R_D\times \mathrm{SC}}\cong \frac{\mathrm{FH}}{F}& \mathrm{Equation}16\end{array}$

[0085] The trimming resistor R.sub.S2 may be used to adjust the discharge resistance R.sub.D and thereby adjust/tune the low frequency signal FL with respect to which the Bridge seeks to reach equilibrium. Since a fixed divider ratio may be used, the high frequency signal FH may be controlled in view of the discharge resistance R.sub.D and the switched capacitance SC used for a given implementation.

[0086] Further, the use of the Bridge facilitates comparisons being made, by the integrator 108, on a first order and with such comparisons being insensitive to low frequency variations in the supply voltage V.sub.DD. It is to be appreciated that higher frequency variations in the supply voltage V.sub.DD may result in undesirable sampling and aliasing occurring in various components used in the timing circuit 200. It is to be appreciated that such low frequency variations and high frequency variations which may cause or not cause undesirable responses by the timing circuit 200 may be determined based on simulations, calculations, testing, use, or otherwise.

[0087] As further shown in FIG. 2, the integrator 108 includes an op-amp 220 having an inverting input 226 and a non-inverting input 227. The inverting input 226 is coupled to the inverting node 224 and to a first lead of an integrator capacitor C.sub.INT. A second lead of the integrator capacitor C.sub.INT is coupled to an output lead of the op-amp 220 and an output node 228 of the integrator 108. The non-inverting input 227 of the op-amp 220 is coupled to the non-inverting node 222 of the integrator 108. The integrator 108 generates an integrated signal V.sub.IS (as shown in FIG. 3A and as discussed above).

[0088] It is to be appreciated that when the bridge is not in equilibrium, V.sub.IS will rise and fall with a slope that is defined by the inverting current signal I.sub.INV. Since the currents into the op-amp 220 are ideally zero, the inverting current signal I.sub.INV will flow into the integrator capacitor C.sub.INT. Accordingly, the relationship between the integrated signal V.sub.IS and the inverting current signal I.sub.INV can be expressed mathematically as per Equation 17.

[00007]$\begin{array}{cc}\frac{{\mathrm{dV}}_{\mathrm{IS}}}{\mathrm{dt}}\cong \frac{I_{\mathrm{INV}}}{C_{\mathrm{INT}}}& \mathrm{Equation}17\end{array}$

[0089] Per Equations 15 and 17, the slope of V.sub.IS is proportional to the error voltage V.sub.ERROR between the two divider strings of the Bridge, which corresponds to the inverting signal current I.sub.INV through the integrator capacitor C.sub.INT. Due to the regulation loop design, the timing circuit 200 will eventually settle to a V.sub.IS which brings the Bridge into equilibrium. Further, the integrating capacitance CI of the integrator capacitor C.sub.INT determines, in part, the amount of ripple provided in the control signal V.sub.C (and correspondingly the amount of jitter in the high frequency signal FH), with a higher capacitance providing less ripple. As shown in FIG. 3A, an initial spike on the integrated signal V.sub.IS commonly arises due to non-ideal op-amps being used, such as an op-amp 220 providing other than a zero (0) output impedance and having a finite reaction speed. The spike commonly occurs upon the first switch S1 connecting the switched capacitor C.sub.S from GND 114 to the supply voltage V.sub.DD, which increases, via the integrator capacitor C.sub.INT, the integrated signal V.sub.IS voltage. After a settling time, the op-amp 220 compensates for this transient voltage by reducing the integrated signal V.sub.IS voltage to a low potential and then integrating the charge from the switched capacitor C.sub.S into the integrator capacitor C.sub.INT. Upon the charge being transferred from the switched capacitor C.sub.S to the integrator capacitor C.sub.INT, the output voltage of the integrated signal V.sub.IS will have decreased to a level that may be determined based on the supply voltage V.sub.DD, the switched capacitance SC and the integrating capacitance CI. This relationship can be mathematically expressed as per Equation 18.

[00008]$\begin{array}{cc}{V}_{\mathrm{IS}}\cong \frac{V_{\mathrm{DD}}\times \mathrm{SC}}{\mathrm{IC}}& \mathrm{Equation}18\end{array}$

[0090] During the remainder of the given period T.sub.FL, the influence of the resistor R and the continuous removing of the removed charge Q.sub.R out of integrator capacitor C.sub.INT, where C.sub.INTI is substantially equivalent to the phase one charge Q.sub.CS1, results in V.sub.IS rising again. Further, due to the discharge resistors' R continuous discharging of the integrator capacitor C.sub.INT, during start-up, the control signal V.sub.C will continually rise, even when a low frequency signal FL is not present to drive the switches S1 and S2. Eventually, the control signal V.sub.C will become sufficiently high, the VCO will generating a high frequency signal FH, and regulation of the timing circuit 200 will occur.

[0091] As shown in FIG. 2, the timing circuit 200 may include a filter 110 that receives the integrated signal V.sub.IS and outputs a control signal V.sub.C to the VCO 112. For at least one embodiment, the filter 110 may use a passive low pass filter. The low pass filter may be used to reduce the magnitude of ripples occurring in the integrated signal V.sub.IS. Such ripples may arise on top of a direct current (DC) component of the integrated signal V.sub.IS. This results in the peak voltage ripples being reduced. As shown in FIGS. 3A and 3B, the peak voltage in V.sub.C is less than the peak voltages in V.sub.IS.

[0092] The total bandwidth available for placement of a given high frequency signal FH may be determinative of one or more characteristics of the filter 110 used in any given implementation. More specifically, the filter 110 may be configured such that a roll off between ripples in the integrated signal V.sub.IS versus ripples in the control signal V.sub.C is sufficiently high such that the jitter in the high frequency signal FH is within a permitted bandwidth. It is to be appreciated that the relationship between the control signal V.sub.C and the voltages in the high frequency signal FH (as shown, for example, in FIG. 3D) may be expressed mathematically as per Equation 19.

FH≅V.sub.C×G  Equation 19: [0093] where, “G” is the gain factor of the VCO 112.

[0094] A process for locking a VCO to a high frequency signal FH may include dividing the high frequency signal FH into a lower frequency signal FL and configuring an SCRC 104 such that a Bridge reaches equilibrium when variations in the error voltage V.sub.ERROR provided to an integrator 108 result in a control signal V.sub.C being output by the integrator 108, with or without additional filtering, to a VCO 112 such that a high frequency signal FH is generated and is jittered about a given center frequency and within a given bandwidth.

[0095] It is to be appreciated that the operations described above are illustrative and are not intended herein to occur, for all embodiments of the present disclosure, in the order described, in sequence, by the controller or otherwise. Further, it is to be appreciated that one or more of the operations may be performed in parallel and operations may be not performed, as provided for any given use of an embodiment of the present disclosure.

[0096] Although various embodiments of the claimed invention have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of the claimed invention. The use of the terms “approximately” or “substantially” means that a value of an element has a parameter that is expected to be close to a stated value or position. Further, as is well known in the art, there may be minor variations that prevent the values from being exactly as stated. Accordingly, anticipated variances, such as 10% differences, are reasonable variances that a person having ordinary skill in the art would expect and know are acceptable relative to a stated or ideal goal for one or more embodiments of the present disclosure. It is also to be appreciated that the terms “top” and “bottom”, “left” and “right”, “up” or “down”, “first”, “second”, “next”, “last”, “before”, “after”, and other similar terms are used for description and ease of reference purposes and are not intended to be limiting to any orientation or configuration of any elements or sequences of operations for the various embodiments of the present disclosure. Further, the terms “coupled”, “connected” or otherwise are not intended to limit such interactions and communication of signals between two or more devices, systems, components or otherwise to direct interactions; indirect couplings and connections may also occur. Further, the terms “and” and “or” are not intended to be used in a limiting or expansive nature and cover any possible range of combinations of elements and operations of an embodiment of the present disclosure. Other embodiments are therefore contemplated. It is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative of embodiments and not limiting. Changes in detail or structure may be made without departing from the basic elements of the invention as defined in the following claims.