Abstract
A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped gate shielded electrodes in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.
Claims
1. A Shielded Gate Trench (SGT) MOSFET comprising: an epitaxial layer of a first conductivity type extends over a substrate; a plurality of first type trenches is formed in said epitaxial layer in an active area, each of said first type trenches is filled with a shielded gate structure comprising a first poly-silicon layer in a lower portion to serve as a shielded electrode and a second poly-silicon layer in an upper portion to serve as a gate electrode, wherein said shielded electrode is insulated from said epitaxial layer by a first insulating film and said gate electrode is insulated from said epitaxial layer by a gate insulating film which has a thickness less than said first insulating film, wherein said shielded electrode and said gate electrode are insulated from each other by a second insulating film; an ESD clamp diode comprises said second poly-silicon layer formed on top of said epitaxial layer and is isolated from said epitaxial layer by said first insulating film; said ESD clamp diode is connected with at least one second type trench through a source metal, wherein said second type trench is filled with said first poly-silicon layer as a single electrode; and said first and second poly-silicon layers are doped with said first conductivity type.
2. The SGT MOSFET of claim 1, wherein said ESD clamp diode is consisted of at least one pair of back to back Zener diodes comprising multiple alternatively arranged doped regions of said first conductivity type and doped regions of a second conductivity type opposite to said first conductivity type.
3. The SGT MOSFET of claim 1, wherein said active area further comprises source regions of said first conductivity type and body regions of a second conductivity type, wherein said source regions and said body regions are connected to said source metal through trenched source-body contacts filled with a contact metal plug which is tungsten metal layer padded by a barrier layer of Ti/TIN or Co/TiN or Ta/TiN.
4. The SGT MOSFET of claim 1, wherein said shielded electrode is connected to said single electrode in said second type trench to further be shorted to said source metal through a trenched shielded electrode contact filled with a contact metal plug, wherein said single electrode is formed by said first poly-silicon layer in said second type trench and said contact metal plug is tungsten metal layer padded by a barrier layer of Ti/TIN or Co/TiN or Ta/TiN.
5. The SGT MOSFET of claim 1, wherein said gate electrode is connected to a wider gate electrode to further be shorted to a gate metal through a trenched gate contact filled with a contact metal plug, wherein said wider gate electrode is formed at a same step as said gate electrode in a third type trench having a greater trench width than said first type trenches and said contact metal plug is tungsten metal layer padded by a barrier layer of Ti/TIN or Co/TiN or Ta/TiN.
6. A method of manufacturing a SGT MOSFET having a ESD clamp diode comprising: growing an epitaxial layer of a first conductivity type onto a substrate of the first conductivity type, wherein said epitaxial layer has a lower doping concentration than said substrate; forming a plurality of trenches inside said epitaxial layer, including a plurality of first type trenches in an active area; depositing a doped first poly-silicon layer to fill all the trenches, padded by a first insulating film; performing poly-silicon CMP; applying a SG mask and performing poly-silicon etching and oxide etching, leaving necessary part of the first poly-silicon layer in said first type trenches to serve as shielded electrodes; growing a gate insulating film; depositing an un-doped second poly-silicon layer covering top of the device and filling the first type trenches onto said gate insulating layer; performing ion implantation of a second conductivity type; forming a thermal oxide layer and a nitride layer successively onto said second poly-silicon layer; applying a poly-silicon mask, performing dry nitride etch and ion implantation of said first conductivity type; driving-in the dopant of said first conductivity type after removing said poly-silicon mask; etching said second poly-silicon layer in an active area for following body ion implantation of said second conductivity type, leaving necessary part of said second poly-silicon layer to serve as gate electrodes in said first type trenches; removing said nitride layer and driving-in the dopant in said body region; applying a source mask and performing ion implantation of said first conductivity type dopant to form source region and anode (cathode) regions for ESD clamp diode.
7. The method of claim 6, wherein forming a plurality of trenches include forming at least a second type trench and a third type trench having a greater trench width than said first and second type trenches.
8. The method of claim 6, before etching away some of said second poly-silicon layer, comprises removing part of said thermal oxide layer under said nitride layer.
9. The method of claim 6, after removing said nitride layer, comprises removing rest of said thermal oxide layer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
[0017] FIG. 1A is a cross-sectional view of a SGT MOSFET of prior art.
[0018] FIG. 1B is a cross-sectional view of a SGT MOSFET having an ESD protection diode of prior art.
[0019] FIG. 2 is a cross-sectional view of a SGT MOSFET having an ESD diode of another prior art.
[0020] FIG. 3A is a cross-sectional view of a preferred embodiment according to the present invention.
[0021] FIG. 3B is a cross-sectional view of another preferred embodiment according to the present invention.
[0022] FIG. 3C is a cross-sectional view of another preferred embodiment according to the present invention.
[0023] FIG. 3D is a cross-sectional view of another preferred embodiment according to the present invention.
[0024] FIG. 3E is a cross-sectional view of another preferred embodiment according to the present invention.
[0025] FIG. 3F is a cross-sectional view of another preferred embodiment according to the present invention.
[0026] FIG. 3G is a cross-sectional view of another preferred embodiment according to the present invention.
[0027] FIG. 4 is a cross-sectional view of another preferred embodiment according to the present invention.
[0028] FIGS. 5A-5H are a serial of cross-sectional views illustrating the process for fabricating the SGT MOSFET in FIG. 4.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] In the following Detailed Description, reference is made to the accompanying drawings, which forms a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., is used with reference to the orientation of the Figure(s) is described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purpose of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
[0030] Please refer to FIG. 3A for a preferred embodiment of this invention wherein an N-channel SGT MOSFET 300 with an ESD clamp diode is formed on an N+ substrate 301 with an N epitaxial layer 302 extending whereon. Inside the N epitaxial layer 302 forms: a plurality of first type trenches 303 in an active area (as illustrated); multiple second type trenches 304 underneath the ESD clamp diode (there are two second type trenches in this embodiment); a third type trench 305 used for shielded gate connection and a fourth type trench 306 used for gate connection. Each of the first type trenches 303 is filled with a shielded gate structure comprising: a first poly-silicon layer in a lower portion to serve as a shielded electrode 307 of n doped type; and a second poly-silicon layer in an upper portion to serve as a gate electrode 308 of n doped type; the shielded electrode 307 is insulated from the N epitaxial layer 302 by a first insulating film 309, the gate electrode 308 is insulated from the N epitaxial layer 302 by a gate insulating film 310 which has a thickness less than the first insulating film 309, wherein the shielded electrode 307 and the gate electrode 308 are insulated from each other by a second insulating film 311. The active area further comprises P body regions 312 and n+ source regions 313 extending whereon between two adjacent gate electrodes 308, wherein the n+ source regions 313 and the P body regions 312 are connected to a source metal 314 through trenched source-body contacts with each filled with a contact metal plug 315-1 which penetrates through a contact interlayer 316, the n+ source regions 313 and extends into a p+ body contact area 317 in the P body region 312 which also extends between two adjacent of other trenches except between two adjacent of the second type trenches 304. The shielded electrodes 307 in the active area are connected to an outlet part 318 of n doped type for the shielded electrodes 307 to further be shorted to the source metal 314 through a trenched shielded electrode contact filled with a contact metal plug 315-2, wherein the outlet part 318 for the shielded electrodes 307 is formed by the first poly-silicon layer in the third type trench 305 and is insulated from the N epitaxial layer 302 by the first insulating film 309. the gate electrodes 308 in the active area are connected to a wider gate electrode 319 of n doped type to further be shorted to a gate metal 320 through a trenched gate contact filled with a contact metal plug 315-3, wherein the wider gate electrode 319 is formed at a same step as the gate electrodes 318 in the first type trenches 303. The ESD clamp diode is formed on top surface of the N epitaxial layer 302 and above two second type trenches 304, wherein each of the second type trenches 304 is filled with the first poly-silicon layer as a single electrode 321 of n doped type. The ESD clamp diode is consisted of at least one pair of back to back Zener diodes comprising multiple alternatively arranged doped regions of n+/p/n+/p/n+, and furthermore, the ESD diode is formed by the second poly-silicon layer and is isolated from the N epitaxial layer 302 by the first insulating film 309 while isolated from the single electrode 321 by the second insulting film 311. In the ESD clamp diode, n+ anode regions on two ends are respectively shorted to the source metal 314 and the gate metal 320 by trenched anode contacts each located right above the second type trenches 304, and the trenched anode contacts are filled with contact metal plugs 315-4. All the contact metal plugs (315-1, 315-2, 315-3 and 315-4) can be implemented by using tungsten metal layer padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN.
[0031] FIG. 3B shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 400 as illustrated has a similar device structure to FIG. 3A, except that, in FIG. 3B, there are at least three second type trenches 404 underneath the ESD clamp diode in the N epitaxial layer 402.
[0032] FIG. 3C shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 500 as illustrated has a similar device structure to FIG. 3B, except that, in FIG. 3C, a plurality of P* regions 522 with less doped concentration and shallower junction depth than the P body regions 512 are formed between every two adjacent of the second type trenches 504 underneath the ESD clamp diodes to avoid early breakdown issue.
[0033] FIG. 3D shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 600 as illustrated has a similar device structure to FIG. 3A, except that, in FIG. 3D, the second type trenches 604 are filled with the shielded gate structure which is the same as in the fourth type trench 606 instead of the single electrode structure in FIG. 3A. Onto a lower electrode 621 in the second type trenches 604, an upper electrode 619 of n doped type is also serving as n+ anodes on two ends of the ESD clamp diode. Accordingly, the trenched anode contacts 623 are extending into the upper electrodes 619.
[0034] FIG. 3E shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 700 as illustrated has a similar device structure of FIG. 3D, except that, in FIG. 3E, a P* region 722 with less doped concentration and shallower junction depth than the P body regions 712 are formed between the two adjacent second type trenches 704 underneath the ESD clamp diode to avoid early breakdown voltage.
[0035] FIG. 3F shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 800 as illustrated has a similar device structure to FIG. 3D, except that, in FIG. 3F, there are at least three second type trenches 804 underneath the ESD clamp diode in the N epitaxial layer 802.
[0036] FIG. 3G shows another preferred embodiment of the present invention, wherein an N-channel SGT MOSFET 900 as illustrated has a similar device structure to FIG. 3F, except that, in FIG. 3G, a plurality of P* regions 922 with less doped concentration and shallower junction depth than the P body regions 912 are formed between every two adjacent of the second type trenches 904 underneath the ESD clamp diode to avoid early breakdown voltage.
[0037] FIG. 4 shows another preferred N-channel SGT MOSFET 950 of the present invention, as illustrated, the preferred embodiment comprises a plurality of first type trenches 951 in an active area, each of the first type trenches 951 comprises a shielded electrode 952 made of a first poly-silicon layer in the lower portion and a gate electrode 953 made of a second poly-silicon layer made of a second poly-silicon layer in the upper portion, wherein the shielded electrode 952 is insulated from an N epitaxial layer 954 by a first insulating film 955, the gate electrode 953 is insulated from the N epitaxial layer 954 by a gate insulating film 956, the shielded electrode 952 and the gate electrode are insulated from each other by a second insulating film 957. Each the shielded electrode 952 is connected to a single electrode 958 in a second type trench 959 to be further shorted to a source metal 960 through a trenched shielded contact 961. Each the gate electrode 953 is connected to a wider gate electrode 962 in a third type trench 963 to be further shorted to a gate metal 964 through a trenched gate contact 965. An ESD clamp diode made of the second poly-silicon layer is formed on top of the N epitaxial layer 954 and is isolated from the N epitaxial layer 954 by the first insulating film 955. Meanwhile, there is no trench existing in the N epitaxial layer 951 underneath the ESD clamp diode. In the ESD clamp diode, n+ anode regions on two ends are respectively shorted to: the single electrode 958 in at least one second type trench 959 through the source metal 960; and to the wider gate electrode 962 in the third type trench 963 through the gate metal 964.
[0038] FIGS. 5A-5H are cross-sectional views illustrating the process for fabricating the N-channel SGT MOSFET 950 in FIG. 4. In FIG. 5A, the process begins with an N epitaxial layer 954 grown on a heavily doped N+ substrate 971. After offering a trench mask onto the N epitaxial layer 954, a plurality of trenches are formed by lithographic and etching step, including a plurality of first type trenches 951, at least a second type trench 959 and a third type trench 963. After that, a first insulating film 955 is formed lining top surface of the N epitaxial layer 954 and lining inner surface of all the trenches. Then, a first poly-silicon layer of n doped is deposited over the first insulating film 955 to fill all the trenches.
[0039] In FIG. 5B, after poly-silicon CMP (Chemical and Mechanical Polish), the first poly-silicon layer is remained within all the trenches, forming a single electrode 958 in the second type trench 959. Then, a SG (shielded gate) mask is applied to define areas for shielded gate structure, including the first type trenches in the active area and the third type trench 963 for gate connection. Then, after steps of oxide etching and dry poly-silicon etching, the first insulating film 955 and the exposed first poly-silicon layer are selectively removed from partial top surface of the N epitaxial layer 954, and from upper portion of the first type trenches 951 and the third type trench 963.
[0040] In FIG. 5C, after removing the SG mask, another oxide layer is formed by thermally grown or deposition to cover exposed surface of the device to serve as a gate insulating film 956. Then, an undoped second poly-silicon layer is deposited filling the first and the third type trenches and over the entire surface of the device, followed by successive steps of blank Boron implantation to make the second poly-silicon layer be doped with P type dopant.
[0041] In FIG. 5D, a thermal oxide layer 972 is formed onto the second poly-silicon layer. Then, a nitride layer 973 is deposited onto the thermal oxide layer 972, and is then dry etched after applying a poly-silicon mask. Then, a Phosphorus ion implantation is performed to make the second poly-silicon layer be doped with N type dopant.
[0042] In FIG. 5E, the poly-silicon mask is removed and a step of Phosphorus driving-in is performed to make the N type dopant further diffuse into the second poly-silicon layer. In the driving-in step, the Phosphorus driving-in helps to make the N type dopant further diffuse into the portion of the second poly-silicon layer respectively in the upper portion of the first and the third type trenches where the nitride layer 973 doesn't exist whereon. After that, the thermal oxide layer 972 is removed, following by a step of poly-silicon etch to make the second poly-silicon layer remained: within the upper portion of the first type trenches 951 to serve as gate electrodes 952 of the shielded gate structure; within and protruding out of the third type trench 963 to serve as a wider gate electrode 962 for gate connection; covering top of the N epitaxial layer 954 between the second type trench 959 and the third type trench 963 for formation of ESD clamp diode. Next, another Boron ion implantation is performed to form P body region 974 between two adjacent of all the trenches except underneath the ESD clamp diode. Then, after the thermal oxide layer 972 and the Nitride layer 973 are removed away, a step of P body dopant driving-in is performed.
[0043] In FIG. 5F, after applying a source mask, a source ion implantation with n type dopant is performed to: form source regions 975 on top of the P body region 974 in the active area; form n+ anode regions 976 for the ESD clamp diode; and make the gate electrode 952 and the wider gate electrode 962 be of n type doped.
[0044] In FIG. 5G after removing the source mask, a contact interlayer 977 is deposited along top surface of the device. Then, after applying a contact mask (not shown) onto the contact interlayer 977, a plurality of contact trenches are formed by performing successive dry oxide etching and dry silicon etching. After that, a BF2 ion implantation is performed to form the p+ contact area 978 in the P body region 974 and surrounding at least bottom of the contact trenches 979 and 980.
[0045] In FIG. 5H, a barrier layer of Ti/TiN (or Ta/TiN or Co/TiN, not shown) is deposited along inner surface of all the contact trenches, then a tungsten metal layer is deposited onto the barrier layer and is then etched back to serve as contact metal plugs 981 filled in all contact trenches. Next, a front metal is deposited covering front surface of the device and is then etched back to form source metal 960 and gate metal 964 by definition of a metal mask (not shown).
[0046] Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
