Integrated Resistor Network and Method for Fabricating the Same

Abstract

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n−1, and the third number is 1, the total number of resistors is 2n.

Claims

1. An integrated resistor network comprising: a resistor ladder including a first number (n) of first integrated resistors coupled in series between a top contact and a bottom contact, with one or more contacts coupled between two adjacent first integrated resistors, wherein n is a natural number; a second number of second integrated resistors coupled in parallel between the top contact and the bottom contact; and a third number of third integrated resistors coupled in series between the second integrated resistors and one of the top contact or the bottom contact, wherein a voltage developed across each of the first integrated resistors is V.sub.TOP-BOT/n, and wherein V.sub.TOP-BOT is a voltage applied between the top contact and the bottom contact.

2. The integrated resistor network of claim 1, wherein each of the first, second and third integrated resistors have substantially equal width, length, and a resistance of R.

3. The integrated resistor network of claim 1, wherein the second number of the second integrated resistors is n−1, the third number of the third integrated resistors is 1, and a total number of the first, second and third integrated resistors is 2n.

4. The integrated resistor network of claim 3, wherein an area on a surface of an integrated circuit (IC) chip occupied by the first, second and third integrated resistors is 2n×A, where A is an area of a one of the first, second or third integrated resistors.

5. The integrated resistor network of claim 4, wherein a voltage resolution of the voltage developed across each of the first integrated resistors is substantially equal to that developed across each integrated resistor of an n.sup.2 integrated resistor network comprising a total of n.sup.2 integrated resistors.

6. The integrated resistor network of claim 5, wherein a total capacitance of the integrated resistor network is reduced to a factor of 2n/n.sup.2 relative to that of the n.sup.2 integrated resistor network.

7. A method of resolving voltage using a resistor network comprising: providing a voltage-generating-section of the resistor network coupled between a top contact and a bottom contact, the voltage-generating-section including a resistor ladder having a first number (n) of first integrated resistors, coupled in series between the top contact and the bottom contact, with one or more contacts coupled between adjacent individual integrated resistors; providing a resistance path coupled between the top contact and the bottom contact in parallel with the voltage-generating-section; applying a voltage (V.sub.TOP-BOT) between the top contact and the bottom contact, wherein current flows through the voltage-generating-section and through the resistance path; and wherein voltage V.sub.TOP-BOT/n is developed across each of the first integrated resistors in the voltage-generating-section flowing current.

8. The method of claim 7 wherein providing the resistance path comprises providing a current-path including a second number of second integrated resistors coupled in parallel, and a third number of third integrated resistors coupled in series with the second number of second integrated resistors between the top contact and the bottom contact, and wherein each of the first, second and third integrated resistors have a resistance of R.

9. The method of claim 8 wherein each of the first, second and third integrated resistors have substantially equal width and length, and have a resistance R.

10. The method of claim 8, wherein the second number of second integrated resistors is n−1, the third number of third integrated resistors is 1, and a total number of the first, second and third integrated resistors is 2n.

11. The method of claim 10, wherein an area on a surface of an integrated circuit (IC) chip occupied by the first, second and third integrated resistors is 2n×A, where A is an area of a one of the first, second or third integrated resistors.

12. The method of claim 11, wherein a voltage resolution of the voltage developed across each of the first integrated resistors is substantially equal to that developed across each integrated resistor of an n.sup.2 integrated resistor network comprising a total of n.sup.2 integrated resistors.

13. The method of claim 12, wherein a total capacitance of the integrated resistor network is reduced to a factor of 2n/n.sup.2 relative to that of the n.sup.2 integrated resistor network.

14. A temperature detecting system comprising: a current source coupled in series with a low range voltage-generating resistor network comprising: a voltage-generating-section including a resistor ladder having a first number (n) of first integrated resistors coupled in series between a top contact and a bottom contact, with one or more contacts coupled between adjacent individual integrated resistors; and a current-path coupled in parallel with the voltage-generating-section, the current-path including a second number of second integrated resistors coupled in parallel, and a third number of third integrated resistors coupled in series with the second number of second integrated resistors between the top contact and the bottom contact; wherein each of the first, second and third integrated resistors has a resistance of R, and a voltage developed across each of the first integrated resistors in the voltage-generating-section is V.sub.TOP-BOT/n, where V.sub.TOP-BOT is a voltage applied between the top contact and the bottom contact.

15. The system of claim 14, further comprising a high range voltage-generating resistor network coupled in series between the current source and the low range voltage-generating resistor network, wherein the low range voltage-generating resistor network can detect temperature with a greater resolution than the high range voltage-generating resistor network.

16. The system of claim 14, wherein each of the first, second and third integrated resistors have substantially equal width and length.

17. The system of claim 16, wherein the second number of second integrated resistors is n−1, the third number of third integrated resistors is 1, and a total number of the first, second and third integrated resistors is 2n.

18. The system of claim 17, wherein an area on a surface of an integrated circuit (IC) chip occupied by the integrated resistors is 2n×A, where A is an area of a one of the integrated resistors.

19. The system of claim 18, wherein a voltage resolution of the voltage developed across each of the integrated resistors the resistor ladder is substantially equal to that developed across each integrated resistor of an n.sup.2 integrated resistor network comprising a total of n.sup.2 integrated resistors.

20. The system of claim 19, wherein a total capacitance of the integrated resistor network is reduced to a factor of 2n/n.sup.2 relative to that of the n.sup.2 integrated resistor network.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts. Further, the accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present invention, and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.

[0014] FIG. 1 (conventional) is a schematic representation of an integrated resistor having a resistance R;

[0015] FIG. 2 (conventional) is a schematic representation of a resistor ladder suitable for use in a voltage divider and including multiple integrated resistors and/or contacts to increase voltage resolution;

[0016] FIG. 3 (conventional) is a schematic representation of a resistor network including multiple integrated resistors in an n×n (n.sup.2) arrangement to increase voltage resolution;

[0017] FIG. 4A is a cross-sectional view of a thin-film or epitaxial integrated resistor formed on a surface of a substrate and a contact thereto;

[0018] FIG. 4B is a cross-sectional view of another integrated resistor formed by diffusion into a surface of the substrate and a contact thereto;

[0019] FIG. 4C is a planar top view of the integrated resistor of either FIG. 4A or 4B and contacts thereto;

[0020] FIG. 5 is a schematic representation of a resistor network including multiple integrated resistors in a 2n arrangement to increase voltage resolution while reducing overhead area from that shown in FIG. 3;

[0021] FIG. 6 (conventional) is block diagram illustrating a surface area on a substrate of a n.sup.2 resistor network;

[0022] FIG. 7 is block diagram illustrating a surface area on a substrate of a 2n resistor network having the same voltage resolution as the n.sup.2 resistor network of FIG. 6;

[0023] FIG. 8 is a flow chart of a method for increasing voltage resolution using the 2n resistor network of FIG. 5;

[0024] FIG. 9 is a block diagram of a temperature detector system including a 2n resistor network;

[0025] FIG. 10 is a schematic representation of a first alternative resistor network having a total of 1.25n+3.5 resistors, and further reducing overhead area from the 2n resistor network of FIG. 5; and

[0026] FIG. 11 is a schematic representation of another alternative resistor network having a total of 1.25n+5 resistors, and further reducing overhead area from the 2n resistor network of FIG. 5.

DETAILED DESCRIPTION

[0027] An integrated resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. The integrated resistor network and methods of operating the same are particularly useful in or with applications or systems implemented as an integrated circuit (IC) on a single IC chip, such as reference voltage generators, voltage regulation loops, resistance-based temperature detector systems, and any resistor-ladder-based voltage-division used as a part of an analog block.

[0028] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.

[0029] Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term to couple as used herein may include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components.

[0030] Integrated resistors are typically made using a bulk or sheet resistivity of a semiconductor material formed on or in a surface of the substrate, and is commonly fabricated by depositing and patterning a thin film or an epitaxial layer of a conducting or semiconducting material, or by diffusing a dopant into the surface of the substrate. FIG. 4A is a cross-sectional view of an integrated resistor 402 formed from a thin-film or epitaxial layer 404 deposited on a surface 406 of a substrate 408 and a contact 410. FIG. 4B is a cross-sectional view of another embodiment of the integrated resistor formed by a diffusion region 412 into the surface 406 of the substrate 408 with the contact 410. FIG. 4C is a planar top view of the integrated resistor 402 of either FIG. 4A or 4B. The patterned layer 404 or diffusion region 412 can have a substantially linear or rectangular shape between the contacts 410, or can have a zig-zag shape resulting in larger effective length for higher values of resistance as shown in FIG. 4C.

[0031] FIG. 5 is a schematic representation of an integrated resistor network including multiple integrated resistors in a 2n arrangement on a surface of a substrate (not shown). Referring to FIG. 5 the resistor network 500 includes a first resistance path including a resistor ladder 502 having a first number (n) of first integrated resistors 504 coupled in series between a top contact 506 and a bottom contact 508, and a second resistance path including a second number of second integrated resistors 510 coupled in parallel between the top contact and the bottom contact and a third number of third integrated resistors 512 coupled in series between the second integrated resistors and one of the top contact or the bottom contact. Generally, as in the embodiment shown, the resistor network 500 further includes one or more contacts 514, coupled between adjacent individual of first integrated resistors 504 in the resistor ladder 502 to provide incremental voltages less than a voltage applied between the top contact and the bottom contact (V.sub.TOP-BOT).

[0032] Each of the first, second and third integrated resistors 504, 510, 512, have similar or substantially equal widths and lengths, and are fabricated using processes and materials having substantially the same sheet resistance to provide resistors having substantially equal resistance of R, so that a voltage developed across each of the first integrated resistors 504 in the resistor ladder 502 is V.sub.TOP-BOT/n. Additionally, for the 2n resistor network 500, such as shown in FIG. 5, in which the first number of first integrated resistors 504 is n, the second number of second integrated resistors 510 is n−1, and the third number of third integrated resistors 512 is 1, for a total number of the first, second and third integrated resistors of 2n, while the equivalent resistance (R.sub.EQ-TOP-BOT) across the 2n resistor network from the top contact 506 to the bottom contact 508 is substantially equal to that of a resistor network 302 including multiple integrated resistors 304 each with equal resistances and arranged in an n×n (n.sup.2) arrangement, such as shown in FIG. 3. This is because the resistance of all resistors in the n.sup.2 resistor network 302 are equal, as are the number of rows 308 and columns 306 in the n.sup.2 resistor network, the resistance for each row is R/n and the equivalent resistance (R.sub.EQ-TOP-BOT) across the n.sup.2 resistor network from the top contact 310a to the bottom contact 310n is n×R/n or R, where R is the resistance for each resistor 304, and n is the number of individual resistors in each row 308 and column 306.

[0033] For a 2n resistor network 500 such as shown in FIG. 5, the R.sub.EQ-TOP-BOT is equal to:

[00001]$\mathrm{nR}.Math.\left(R+\frac{R}{n-1}\right)=\frac{nR\left(R+R/\left(n-1\right)\right)}{nR+\left(R+R/\left(n-1\right)\right)}=\mathrm{nR}\frac{\left[\frac{\left(nR-R+R\right)}{\left(n-1\right)}\right]}{\frac{\left(R{n}^2-Rn+Rn-R+R\right)}{\left(n-1\right)}}=\frac{R^2{n}^2}{R{n}^2}=R$

where R is the resistance of each of the first, second and third integrated resistors 504, 510, 512, and n is the first number of the first integrated resistors in the resistor ladder 502.

[0034] It will be understood from the above that voltage developed across each of the first integrated resistors in the resistor ladder 502 is V.sub.TOP-BOT/n, is equivalent to the voltage developed across each row 308 of the n.sup.2 resistor network 302. Thus, the 2n resistor network 500 provides the substantially same or equivalent voltage-resolution as the conventional n.sup.2 resistor network 302 of FIG. 3 with a substantial reduction in the number of individual resistors required in the 2n resistor network 500 for any value of n≥3. For example, where n is 10, the n.sup.2 resistor network 302 requires 100 separate, resistors 304, while the 2n resistor network 500 provides the same voltage-resolution with just 20 individual resistors, a reduction of 80%. Moreover, because the number of resistors in the n.sup.2 resistor network 302 increases quadratically, the reduction in the number of resistors for a 2n resistor network 500 with the same voltage-resolution also increases quadratically. Thus, where n is 100 the n.sup.2 resistor network 302 requires 10,000 separate, resistors 304, while the 2n resistor network 500 provides the same voltage-resolution with just 200 individual resistors, a reduction of 98%.

[0035] Additionally, because each of the first, second and third integrated resistors 504, 510, 512, have substantially equal widths and lengths and each occupy substantially the same area on a surface of a substrate on which they are fabricated, the 2n resistor network 500 provides a substantial reduction in the surface area or footprint on the substrate for the 2n resistor network as compared to the conventional n.sup.2 resistor network 302 of FIG. 3 having substantially similarly size resistors providing the same voltage-resolution. This reduction in surface area will now be described with reference to exemplary embodiments shown in FIGS. 6 and 7.

[0036] FIG. 6 is a block diagram illustrating an exemplary embodiment of a surface area of a conventional n.sup.2 resistor network 600 formed on a substrate 602, and including a number of integrated resistors 604 arranged in an n×n (n.sup.2) arrangement of n columns 606 of n resistors in series, and n rows 608 of resistors in parallel to provide a total resistance of R for the resistor network from a top contact 610 to a bottom contact 612. Where, as in the embodiment shown, n is equal to ten the total number of individual, integrated resistors 604 is one hundred, and the surface of substrate 602 occupied by the integrated resistors is n.sup.2×A or 100×A, where A is an area occupied by a single integrated resistor.

[0037] FIG. 7 is block diagram illustrating a surface area on a substrate of a 2n resistor network 700 including integrated resistors with the same resistance (R) and physical dimensions, i.e., each with the same length and width and occupying the same area (A), as the integrated resistors 604 of the n.sup.2 resistor network of FIG. 6. As with the embodiment of the 2n resistor network 500 shown and described with respect to FIG. 5, the resistor network 700 includes a first number (n) of first integrated resistors 702 coupled in series between a top contact 704 and a bottom contact 706, a second number (n−1) of second integrated resistors 708 coupled in parallel between the top contact and the bottom contact, and a third integrated resistors 710 coupled in series between the second integrated resistors and the top contact. As noted previously, where n equal ten the 2n resistor network 700 requires only twenty individual resistors 702 to provide the same voltage resolution as the n.sup.2 resistor network of FIG. 6. Thus, the surface area of a substrate 712 occupied by the integrated resistors 702, 708, 710, is 2 nA or 20A, a reduction in surface area of eighty percent.

[0038] Moreover, because the number and thus the area occupied by integrated resistors 604 in the n.sup.2 resistor network 600 increases quadratically, the reduction in the surface area occupied by the integrated resistors 702, 708, 710, for the 2n resistor network 700 with the same voltage-resolution also decreases quadratically. Thus, where n is 100 the integrated resistors of the n.sup.2 resistor network 600 occupy an area of 10,000×A, the 2n resistor network 700 provides the same voltage-resolution while occupying an area of just 200×A, a reduction of 98%.

[0039] Alternatively, in another embodiment where an area on a substrate allocated for a resistor network is held constant, that is the same area required for an n.sup.2 resistor network is used for a 2n resistor network, the number of resistors in the 2n resistor network can be increased to provide increased voltage-resolution. For example, for an n.sup.2 resistor network where n is equal to 10 and occupying an area of 100×A, a 2n resistor network can be fabricated where n is equal to 50 and also occupying an area of 100×A, while increasing voltage resolution by a factor of five.

[0040] A method for operating a 2n resistor network to increase and/or maintain voltage resolution while reducing and/or maintaining the area or footprint of the resistor network on a surface of a substrate will now be described with reference to the flow chart of FIG. 8. Referring to FIG. 8, the method begins with the providing a voltage-generating-section of the resistor network coupled between a top contact and a bottom contact (step 802). Generally, as described above and shown with reference to FIG. 5, the voltage-generating-section includes a resistor ladder 502 with a first number of first integrated resistors connected in series between the top and bottom contacts 506, 508, with one or more additional contacts 514 coupled between adjacent series connected resistors. An additional resistance path is coupled between the top and bottom contacts in parallel with the voltage-generating-section (step 804). The current-path generally includes a second number of second integrated resistors 510 coupled in parallel, and a third number of third integrated resistors 512 coupled in series with the second number of second integrated resistors between the top and bottom contacts 506, 508. Next, a voltage (V.sub.TOP-BOT) is applied between or across the top and bottom contacts (step 806), and an electrical current is caused to flow concurrently through the current-path and the voltage-generating-section (step 808). Finally, a voltage is developed across each of the first integrated resistors in the voltage-generating-section (resistor ladder 502) (step 810). As described above with reference to FIG. 5, the voltage developed across each of the first integrated resistors is V.sub.TOP-BOT/n, where V.sub.TOP-BOT is a voltage applied between the top contact and the bottom contacts and n is the number of first integrated resistors in the voltage-generating-section coupled between the top and bottom contacts.

[0041] The integrated resistor network and methods of operating the same are particularly useful in or with applications or systems implemented as an integrated circuit on a single IC chip, such as reference voltage generators, voltage regulation loops, resistance-based temperature detector systems, and any resistor-ladder-based voltage-division used as a part of an analog block. A resistance-based temperature detector system including such a 2n resistor network will now be described with reference to the block diagram of FIG. 9.

[0042] Referring to FIG. 9, the temperature detector system 900 includes a number of series connected resistors arranged in an architecture that resembles a voltage divider, but differs in that the resistances are not evenly distributed and instead of forcing a voltage a current is caused to flow through the series connected resistors. The current which is introduced into the series connected resistors from a current source 902 is a function of the temperature, and varies approximately linearly with changes in temperature. The temperature is measured by comparing a voltage at different nodes between the series connected resistors to a constant reference voltage (Vref). In the embodiment shown the series connected resistors include a first number of series connected resistors (Rt0−Rtn) in a high range voltage-generating resistor network 904 that is connected through a first multiplexer 906 to a first comparator 908, and a second number of series connected resistors in a low range voltage-generating resistor network 910, which includes a 2N resistor network 912, connected through a second multiplexer 914 to a second comparator 916. By high range it is meant that the high range voltage-generating resistor network 904 is capable of detecting and measuring temperature within larger or courser increments than the smaller or finer increments of the low range voltage-generating resistor network 910.

[0043] Generally:

I=A×T,

where I is current, T is a temperature of the chip, and A is a derivative of the current and is positive (PTAT, so I is I.sub.PTAT).

[0044] At a full temperature operation range a voltage (V.sub.TOP) measured at a top node of the high range voltage-generating resistor network 904, will change from V.sub.TOP_LOW_TEMP=I.sub.PTAT_LOW_TEMP×R.sub.TOP-BOT to V.sub.TOP_HIGH_TEMP=I.sub.PTAT_HIGH_TEMP×R.sub.TOP-BOT. Thus, the temperature can be detected and measured according to changes in V.sub.TOP value since V.sub.TOP voltage is V.sub.TOP (temp)=I.sub.PTAT (temp)×R.sub.TOP-BOT. Thus, by comparing a voltage between resistors (Rt0−Rtn) in the high range voltage-generating resistor network 904 and between resistors (R1−Rn) in the low range voltage-generating resistor network 910 to a constant reference voltage (Vref) the temperature can be detected.

[0045] The high range voltage-generating resistor network 904 and low range voltage-generating resistor network 910 are designed so when a certain temperature is crossed, the voltage generated from a specific node crosses Vref and is higher than Vref, the first or second comparator 908, 916 connected to Vref and to the high range voltage-generating resistor network or low range voltage-generating resistor network through the associated multiplexer 906 or 914 indicates that one or more voltages that comes from the specific node has crossed Vref. The temperature is then determined by noting the lowest node in the high range voltage-generating resistor network 904 and low range voltage-generating resistor network 910 at which the voltage compared is still higher than Vref. Generally, the high range voltage-generating resistor network 904 and low range voltage-generating resistor network 910 have a different number of series connected resistors, and therefore a different total resistance, but each use substantially equally sized resistors having a substantially equal resistance of R. That is a resistance of each of the resistors (Rtn through Rt0) shown in FIG. 9 are not necessarily equal but are generated from a similar basic resistance R. Thus, although each of the resistors is illustrated as having a resistance of R, the overall series resistance of the combined high range voltage-generating resistor network and low range voltage-generating resistor network has a resistance of Rn+1, where the high range voltage-generating resistor network has a resistance of R×m, where m can be any number real or integer and n is used for indexing purposes, and the low range voltage-generating resistor network has a resistance of R. In the embodiment shown in FIG. 9 the high range voltage-generating resistor network 904 has a temperature detection resolution of 25° C., which means that the voltage at a lower node of Rtn (V.sub.RTn) will cross Vref at 25° C. higher temperature than the voltage (V.sub.RTn-1) at which a higher node of Rtn−1 crossed the Vref. The low range voltage-generating resistor network 906, which includes the 2N resistor network, and has a total resistance of RT.sub.n+1 and with a division ration of n=8 allows generating 8 and multiplexed voltages for a 5° C. resolution. As noted above, a temperature detector using a conventional n.sup.2 resistor network would require an area for 64 R-sized resistors for a low range voltage-generating resistor network, while the low range voltage-generating resistor network 910 including the 2n resistor network can achieve an equivalent 5° C. resolution while occupying an area of just 16 R-sized resistors.

[0046] Alternative arrangements or configurations of resistor networks for reducing overhead area from that of a conventional n.sup.2 network to a degree even greater than that achieved by the 2n resistor network of FIG. 5 will now be described with reference to FIGS. 10 and 11.

[0047] Briefly, through the addition of a third resistance path in parallel with the first and second resistance paths in the 2n resistor network of FIG. 5 the alternative resistor networks described below can gain a further area improvement over the 2n resistor network where n is an even number higher than or equal to 6. If the difference of n−2 results in an even natural number divisible by 4, a first alternative resistor network described below with reference to FIG. 10 will result in a total number of resistors of (1.25 n+3.5), as compared to a conventional n.sup.2 network of equal resistance resolution, and an area of (1.25 n+3.5) times the area of a single resistor. If the difference of n−2 does not result in an even natural number divisible by 4, a second alternative resistor network described below with reference to FIG. 11 will result in a total number of resistors of (1.25n+5), as compared to a conventional n.sup.2 network, and an area of (1.25 n+5) times the area of a single resistor.

[0048] A first alternative resistor network, where n is even natural number, greater than or equal to six (≥6), and where n−2 is divisible by 4, will now be described with reference to FIG. 10. All resistors R shown in FIG. 10 have substantially equivalent resistances and dimensions. This first alternative resistor network 1000 includes a first resistance path 1002 with a resistor ladder 1004 including a first group of n resistors. A second resistance path 1006 coupled in parallel with the first resistance path and including a second resistor 1008 coupled in series with a third resistor 1010; and in series with a fourth group of two or more resistors 1012 coupled in parallel. The number of parallel coupled resistors in the fourth group of resistors 1012 is equal to a quotient of (n−2)/4, which in the embodiment shown is two. As noted above, the first alternative resistor network 1000 further includes a third resistance path 1014 coupled in parallel with the first and second resistance paths 1002, 1006. The third resistance path 1014 includes a fifth resistor 1016 coupled in series with a sixth resistor 1018.

[0049] It is noted that in the first alternative resistor network 1000 shown in FIG. 10, the first group of resistors in the resistor ladder 1004 includes n or 10 resistors. The second and third groups of resistors 1008, 1010, each include 1 resistor and as compared to a conventional n.sup.2 resistor network (such as shown in FIG. 3) having an equivalent resolution, i.e., a 10.sup.2 resistor network, each group replaces (n/2−1)×(n/2−1) resistors of the n.sup.2 resistor network, or 16 resistors in the embodiment shown. Similarly, the fourth group of resistors 1012 includes 2 resistors, which replace (n−2)/4, or 8 resistors of the n.sup.2 resistor network, and the fifth and sixth groups of resistors 1016, 1018, each include 1 resistor and replace (n/2)×(n/2), or 25 resistors of the n.sup.2 resistor network. The total number of resistors in the first alternative resistor network 1000 can be calculated by summing the number of resistors in the first resistance path 1002 or n, the number of resistors in the second resistance path 1006 equal to 2+(n−2)/4, and the number of resistors in the third resistance path 1014. Thus, the total number of equally sized resistors in the first alternative resistor network 1000 is n+2+2+(n−2)/4=1¼n+1½+4=1.25 n+3.5, and the first alternative resistor network 1000 can be referred to as a (1.25n+3.5) resistor network. Where n=10 as shown in FIG. 10, the total number of equally sized resistors in the first alternative or (1.25n+3.5) resistor network 1000 is 16 and the area required for the network is 16RA, where RA is the area required for a single resistor. This represents a reduction in area of 84% over a conventional n.sup.2 resistor network where n=10, and a 25% reduction in number of resistors and area over a 2n resistor network, which would require 20 resistors and have an area of 20RA. Where n=6 a (1.25n+3.5) resistor network similar to that shown in FIG. 10 would require 11 resistors, a 66% reduction in number of resistors and area over a conventional n.sup.2 resistor network, and over an 8% reduction over a 2n resistor network. Where n=50 a (1.25n+3.5) resistor network similar to that shown in FIG. 10 would require 66 resistors, a 97% reduction in number of resistors and area over a conventional n.sup.2 resistor network, and over an 34% reduction over a 2n resistor network.

[0050] A second alternative resistor network where n is even natural number, greater than or equal to eight (≥8), and where n−2 is not divisible by 4, will now be described with reference to FIG. 11. In the embodiment shown in FIG. 11 n=12, and all resistors R have substantially equivalent resistances and dimensions. This second alternative resistor network 1100, and includes a first resistance path 1102 with a resistor ladder 1104 including a first group of n resistors, a second resistance path 1106 coupled in parallel with the first resistance path, and a third resistance path 1108 coupled in parallel with the first and second resistance paths. As with the first alternative resistor network 1000 shown in FIG. 10 the second resistance path 1106 includes a second resistor 1110 coupled in series with a third resistor 1112; and in series with a fourth group of two or more resistors 1114 coupled in parallel. The third resistance path 1108 includes a fifth resistor 1116 coupled in series with a sixth resistor 1118. The second resistance path 1106 differs from that shown in FIG. 10 in that it further includes a seventh group 1120 of two series coupled resistors in parallel with the fourth group.

[0051] The total number of resistors in the second alternative resistor network 1100 can be calculated by summing the number of resistors in the first resistance path 1102 or n, the number of resistors in the second resistance path 1106 equal to 2+(n−4)/4+2, and the number of resistors in the third resistance path 1108. Thus, where n=12 as shown in FIG. 12 the total number of resistors in the second alternative resistor network 1100, is n+2+2+(n−4)/4+2=1¼n−1+6=1¼n+5, and the second alternative resistor network 1100 can be referred to as a (1.25n+5) resistor network. Where n=12 as shown in FIG. 11, the total number of equally sized resistors in the first alternative or (1.25n+5) resistor network 1100 is 20 and the area required for the network is 20RA, where RA is the area required for a single resistor. This represents a reduction in area of 86% over a conventional n.sup.2 resistor network where n=12, and a 17% reduction in number of resistors and area over a 2n resistor network, which would require 24 resistors and have an area of 24RA. Where n=8 a (1.25n+5) resistor network similar to that shown in FIG. 11 would require 15 resistors, versus 64 for a conventional n.sup.2 resistor network, and 16 for a 2n resistor network. Where n=52 a (1.25n+5) resistor network similar to that shown in FIG. 11 would require 70 resistors, versus 2704 for a conventional n.sup.2 resistor network, and 104 for a 2n resistor network. In embodiments, alternative resistor networks 1000 and 1100 may be incorporated in the low range voltage-generating resistor network 910 as best shown in FIG. 5.

[0052] Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0053] The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0054] It is to be understood that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.

[0055] The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.