NANOWIRE ARRAY, OPTOELECTRONIC DEVICE AND PREPARATION METHOD THEREOF

Abstract

Provided is a nanowire array, in which a plurality of nanowires are densely packed and in contact with each other via side walls to form a three-dimensional, compact layer structure, wherein the plurality of nanowires are formed from InGaN-based material. Also provided is an optoelectronic device comprising the nanowire array which is epitaxially grown on a surface of a substrate (12). Further provided are methods for preparing the nanowire array and the optoelectronic device.

Claims

1. A nanowire array comprising a plurality of nanowires which are densely packed and in contact with each other via sidewalls thereof, such that a three-dimensional, compact layer structure is formed; wherein the plurality of nanowires are formed from InGaN-based material.

2. The nanowire array according to claim 1, wherein each of the plurality of nanowires in the nanowire array has a diameter of 100 nm or less.

3. The nanowire array according to claim 1, wherein each of the plurality of nanowires in the nanowire array has a length corresponding to a thickness of the three-dimensional, compact layer structure, and has a length of 100 nm to 2 μm.

4. The nanowire array according to claim 1, wherein the plurality of nanowires in the nanowire array are in contact with each other via sidewalls thereof, so as to form lateral electrical conduction.

5. An optoelectronic device comprising the nanowire array according to claim 1 epitaxially grown on a surface of a substrate.

6. The optoelectronic device according to claim 5, wherein the nanowire array is grown on a Si (111) or Si (100) surface of the silicon wafer or silicon-based layer structure.

7. A method for preparing the nanowire array according to claim 1 comprising adjusting an In-to-Ga flux ratio in a range from zero to infinite, when the In-to-Ga flux ratio is 0.4 or less, producing an InGaN layer having an In content of 30% or less, at a growth temperature ranging from 500 to 900° C.; wherein, an active N flux is two or more times a metal In and Ga flux; when the In-to-Ga flux ratio is above 0.4, producing an InGaN layer having an In content above 30%, at a growth temperature ranging from 300 to 500° C.; wherein, an active N flux is two or more times a metal In and Ga flux.

8. (canceled)

9. The method according to claim 7, comprising adjusting a metal In and Ga flux to a value corresponding to a growth rate ranging from 0.2 to 1 μm/h.

10. A method for preparing the optoelectronic device according to claim 5, comprising the following steps of: 1) providing a substrate; and 2) epitaxially growing a three-dimensional, compact layer structure composed of a nanowire array on the substrate, wherein the nanowire array comprises a plurality of nanowires which are densely packed and in contact with each other via sidewalls to form the three-dimensional, compact layer structure.

11. (canceled)

12. The method according to claim 10, wherein the plurality of the nanowires is epitaxially grown along a crystallographic c-axis of a wurtzite structure.

13. (canceled)

14. The method according to claim 10, wherein the substrate is selected from a sapphire, gallium nitride, silicon, silicon carbide or gallium arsenide substrate.

15. The method according to claim 7, wherein, when the In-to-Ga flux ratio is 0.4 or less, the InGaN layer is produced at a growth temperature ranging from 550 to 750° C.

16. The method according to claim 7, wherein, when the In-to-Ga flux ratio is 0.4 or less, the active N flux is 5 to 6 times the metal In and Ga flux.

17. The method according to claim 7, wherein, when the In-to-Ga flux ratio is above 0.4, the InGaN layer is produced at a growth temperature ranging from 420 to 480° C.

18. The method according to claim 7, wherein, when the In-to-Ga flux ratio is above 0.4, the active N flux is 3 to 4 times the metal In and Ga flux.

19. The method according to claim 9, comprising adjusting a metal In and Ga flux to a value corresponding to a growth rate ranging from 0.5 to 0.6 μm/h.

20. The nanowire array according to claim 2, wherein each of the plurality of nanowires in the nanowire array has a diameter of 20 to 40 nm.

21. The optoelectronic device according to claim 5, wherein the substrate is selected from a sapphire, gallium nitride, silicon, silicon carbide or gallium arsenide substrate.

22. The optoelectronic device according to claim 5, wherein the substrate is a silicon substrate.

23. The optoelectronic device according to claim 5, wherein the substrate is a silicon wafer or silicon-based layer structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Hereinafter, the present disclosure is further described with reference to the drawings and specific embodiments. The exemplary embodiments of the present disclosure are illustrated in the accompanying drawings, wherein similar reference numerals indicate the same or similar elements. In the drawings:

[0039] FIG. 1 shows a top view of an InGaN-based optoelectronic device according to an embodiment of the present disclosure. FIG. 1A schematically shows a top view of an InGaN-based optoelectronic device, in which the InGaN-based optoelectronic device is composed of InGaN nanowires with a diameter (11). For clarity of representation, the sizes of different parts are not shown to in scale. FIG. 1B shows a Scanning Electron Microscope (SEM) top view of an InGaN three-dimensional, compact structure.

[0040] FIG. 2 shows a cross-sectional view of an InGaN-based optoelectronic device according to an embodiment of the present disclosure. FIG. 2A schematically shows a cross-sectional view of an InGaN-based three-dimensional, compact structure grown on a substrate (12). It should be understood that the sizes of different parts are not shown in scale. FIG. 2B shows an SEM cross-sectional view of an InGaN three-dimensional, compact structure epitaxially grown on a Si (111) substrate with surface nitridation.

[0041] FIG. 3 shows X-ray diffraction spectra of an InGaN-based optoelectronic device according to an embodiment of the present disclosure. CuKα radiation is used to perform omega/2θ scans in the vicinity of the symmetric Si (111) and InGaN (0002) crystal plane reflection.

DETAILED DESCRIPTION

[0042] The present disclosure is described in detail hereinafter through the specific embodiments. However, it should be understood that the present disclosure is not limited to the following specific embodiments. The scope of protection of the present disclosure is defined by the appending claims. Within the scope of protection of the present disclosure, the following embodiments can be arbitrarily changed and combined. The directional terms mentioned in the embodiments, such as “up”, “down”, “front”, “back”, “left”, “right”, and the like, are only referred to the directions of the drawings, and are not used to limit the scope of protection of the present disclosure.

EXAMPLES

[0043] In this example, a three-dimensional dense layered structure composed of one-dimensional InGaN nanowires was prepared by the following steps:

[0044] 1) providing a Si (111) substrate with surface nitridation,

[0045] 2) epitaxially growing one-dimensional InGaN nanowires by means of a plasma-assisted molecular beam epitaxy device (Vecco Gen II) on the Si (111) substrate, wherein the specific settings are as follows:

[0046] the In/Ga total metal flux was adjusted to obtain a growth rate of about 0.5 μm/h;

[0047] the In/Ga flux ratio was adjusted to be 5 and the growth temperature was set to be 450° C., the active N flux was adjusted to be 3 times the In/Ga metal flux.

[0048] An InGaN three-dimensional, compact structure was obtained by the above method, as shown in FIGS. 1 and 2. It can be seen that the InGaN three-dimensional, compact structure is composed of densely packed one-dimensional nanowires with 71% In content, and has a thickness of about 600 nm.

[0049] FIG. 1A schematically shows a top view of an exemplary InGaN three-dimensional, compact structure, and shows a part of densely packed one-dimensional nanowires with a diameter 11.

[0050] FIG. 1B shows a scanning electron microscope top view of the above InGaN three-dimensional compact structure material.

[0051] For measuring the lateral electrical conductivity of the InGaN three-dimensional, compact structure, two metal ohmic Al contacts, 1 mm apart, are deposited on the surface of the structure in a metal evaporation equipment. Standard current-voltage measurements are performed with a Keithley source meter. Results show that the lateral electrical conductivity of the InGaN three-dimensional is 50 Ω.sup.−1cm.sup.−1. This is comparable, within the same order of magnitude, with the electrical conductivity of compact, single-crystalline InGaN epitaxial layer structures.

[0052] FIG. 2A schematically shows a cross-sectional view of an InGaN-based three-dimensional, compact structure. In particular, FIG. 2A shows a substrate 12, an InGaN three-dimensional, compact structure of a thickness 13, and one-dimensional InGaN nanowires of a diameter 11.

[0053] FIG. 2B shows an SEM cross-sectional view of an InGaN three-dimensional, compact structure with an In content of 71% epitaxially grown on the Si (111) substrate with surface nitridation. As can be seen, the InGaN three-dimensional, compact structure has nanowires with a thickness of 600 nm.

[0054] In addition, the InGaN three-dimensional, compact structure prepared in this example is tested by X-ray diffraction, and results are shown in FIG. 3. FIG. 3 shows omega/2θ diffraction peaks, with logarithmic scale, of symmetric Si (111) and InGaN (0002), by using Cu Kα1 and Cu Kα2 X-ray radiation sources. The diffraction peak of Si (111) crystallographic planes is centered at 14.2°, and the diffraction peak of an InGaN (0002) crystallographic planes with 71% In content is centered at 16.07°. The X-ray diffraction measurement results show that the Si-based InGaN three-dimensional, compact structure prepared in this example has significant and symmetric crystallographic plane diffraction peaks. The results show that the Si-based InGaN three-dimensional, compact structure prepared in this example has good crystal quality.

[0055] The preferred embodiments of the present disclosure are specifically illustrated by the contents above, but the present disclosure is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the scope of the present disclosure. These equivalent modifications or replacements shall all fall within the scope defined by the claims of the present disclosure.