Field-Effect Transistor

Abstract

Example embodiments relate to field-effect transistors. An example field-effect transistor includes a plurality of field-effect transistor elements, each field-effect transistor element including a gate finger and a gate runner. The gate finger of each field-effect transistor element is electrically connected at a plurality of spaced apart positions to the gate runner of that element. Each gate finger is made of a first material or material composition and has a first electrical resistivity. The field-effect transistor further includes, for each gate finger, a gate resistor through which the electrical connection between the gate finger and the gate runner at a position among the plurality of spaced apart positions is realized. The gate resistor is made of a second material or material composition and has a second electrical resistivity that is higher than the first electrical resistivity.

Claims

1. A field-effect transistor comprising a plurality of field-effect transistor elements, each field-effect transistor element comprising a gate finger and a gate runner, wherein the gate finger of each field-effect transistor element is electrically connected at a plurality of spaced apart positions to the gate runner of that element, wherein each gate finger is made of a first material or material composition and has a first electrical resistivity, and wherein the field-effect transistor further comprises, for each gate finger, a gate resistor through which the electrical connection between the gate finger and the gate runner at a position among the plurality of spaced apart positions is realized, said gate resistor being made of a second material or material composition and having a second electrical resistivity that is higher than the first electrical resistivity.

2. The field-effect transistor according to claim 1, wherein the second electrical resistivity is at least 10 times greater than the first electrical resistivity, preferably at least 50 times.

3. The field-effect transistor according to claim 1, wherein the field-effect transistor comprises, for each gate finger, a plurality of gate resistors, each gate resistor corresponding to a respective position among the plurality of said spaced apart positions, wherein the field-effect transistor preferably comprises, for each gate finger, a respective gate resistor for each of the spaced apart positions.

4. The field-effect transistor according to claim 3, wherein, for each gate finger, the plurality of gate resistors are identical, all the gate resistors of the field-effect transistor preferably being identical.

5. The field-effect transistor according to claim 1, wherein the first material or material composition is identical to the second material or material composition, wherein the difference in electrical resistivity is obtained by using a different processing of this material or material composition for the gate fingers and gate resistors.

6. The field-effect transistor according to claim 5, wherein the gate resistors and gate fingers are both made from polysilicon, wherein the polysilicon of the gate fingers has been silicidized, and wherein the gate resistors have not been silicidized.

7. The field-effect transistor according to claim 6, wherein the polysilicon of the gate fingers has been subjected to a dopant diffusion step for decreasing the electrical resistivity of the gate fingers, and wherein the gate resistor has not or hardly been subjected to subjected to such a dopant diffusion step.

8. The field-effect transistor according to claim 1, wherein the gate runner extends in parallel to the gate finger, and wherein the gate runner is made of a metal or metal composition having a third electrical resistivity that is substantially lower than the first electrical resistivity.

9. The field-effect transistor according to claim 8, wherein the first electrical resistivity is at least 50 times greater than the third electrical resistivity, preferably at least 150 times.

10. The field-effect transistor according to claim 1, wherein each gate resistor comprises a first end at which the gate resistor is connected to the gate finger, and a second end opposite to the first end, and wherein the field-effect transistor comprises, for each gate resistor, one or more vias for connecting the gate resistor at or near the second end to the gate runner.

11. The field-effect transistor according to claim 1, wherein the plurality of gate fingers extend in parallel, and wherein during operation, gate currents in each gate finger flow in substantially the same direction.

12. The field-effect transistor according to claim 1, wherein the field-effect transistor comprises a Si-based laterally diffused metal-oxide semiconductor (LDMOS) transistor or a GaN-based high electron mobility transistor (HEMT).

13. The field-effect transistor according to claim 1, further comprising, for each field-effect transistor element, a doped source region and a doped drain region that each extend in parallel to the gate finger of that element on a first and second side of the gate finger, respectively, wherein the plurality of spaced apart positions are arranged on the first side of gate finger.

14. The field-effect transistor according to claim 13, wherein each gate finger extends along a respective first direction, and wherein each gate finger comprises: an elongated main section that extends along the first direction; and for each of the spaced apart positions, a gate island that is connected to the main section and that extends perpendicular to the first direction, wherein each gate resistor is connected in between a respective gate island and the gate finger, and/or wherein each gate resistor at least partially forms the corresponding respective gate island.

15. The field-effect transistor according to claim 14, wherein the doped source region is interrupted near said plurality of spaced apart positions for decreasing a gate-source capacitance of the field-effect transistor.

16. The field-effect transistor according to claim 14, further comprising a plurality of drain fingers, each drain finger being associated with a respective gate finger and being electrically connected to the corresponding doped drain region.

17. The field-effect transistor according to claim 16, further comprising: a gate bondbar that extends in the second direction, and that is electrically connected to the gate fingers; and a drain bondbar that extends in the second direction, and that is electrically connected to the drain fingers, wherein the drain bar is opposite to the gate bar.

18. The field-effect transistor according to claim 17, further comprising an RC-filter in between the gate bondbar and the plurality of gate fingers, said RC-filter comprising a parallel connection of a resistor and a capacitor.

19. A semiconductor die comprising the field-effect transistor as defined in claim 18.

20. An amplifier package, comprising: a substrate; the semiconductor die of claim 19 arranged on the substrate; an input lead and an output lead each arranged spaced apart from the substrate and the semiconductor die; a first plurality of bondwires extending along the first direction from the input lead to the gate bondbar; and a second plurality of bondwires extending along the first direction from the output lead to the drain bondbar.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Next, example embodiments will be described in more detail by referring to the appended drawings.

[0037] FIG. 1A schematically illustrates a known field-effect transistor.

[0038] FIG. 1B schematically illustrates an equivalent circuit of the known field-effect transistor illustrated in FIG. 1A.

[0039] FIG. 2A illustrates a view corresponding to the field-effect transistor of FIG. 1A.

[0040] FIG. 2B illustrates a view corresponding to the field-effect transistor of FIG. 1A.

[0041] FIG. 2C illustrates a view corresponding to the field-effect transistor of FIG. 1A.

[0042] FIG. 3A schematically illustrates a field-effect transistor and amplifier package, according to example embodiments.

[0043] FIG. 3B schematically illustrates a field-effect transistor and amplifier package, according to example embodiments.

[0044] FIG. 3C schematically illustrates a field-effect transistor and amplifier package, according to example embodiments.

[0045] FIG. 4A illustrates a cross-sectional view corresponding to the field-effect transistor of FIG. 3A, according to example embodiments.

[0046] FIG. 4B illustrates a cross-sectional view corresponding to the field-effect transistor of FIG. 3A, according to example embodiments.

[0047] FIG. 5A illustrates a processing stage for realizing a polysilicon gate resistor used in the field-effect transistor of FIG. 3A, according to example embodiments.

[0048] FIG. 5B illustrates a processing stage for realizing a polysilicon gate resistor used in the field-effect transistor of FIG. 3A, according to example embodiments.

[0049] FIG. 5C illustrates a processing stage for realizing a polysilicon gate resistor used in the field-effect transistor of FIG. 3A, according to example embodiments.

[0050] FIG. 5D illustrates a processing stage for realizing a polysilicon gate resistor used in the field-effect transistor of FIG. 3A, according to example embodiments.

[0051] FIG. 5E illustrates a processing stage for realizing a polysilicon gate resistor used in the field-effect transistor of FIG. 3A, according to example embodiments.

DETAILED DESCRIPTION

[0052] FIG. 3A illustrates a semiconductor die 101 comprising a field-effect transistor in accordance with the present disclosure. The field-effect transistor comprises a gate bondbar 102 to which bondwires 103 are bonded for receiving an input signal. Gate bondbar 102 is connected to an RC-filter 104 that is schematically illustrated as a box in between gate bondbar 102 and gate bar 105.

[0053] From gate bar 105 a plurality of gate runners 107 extend. Each gate runner 107 corresponds to a respective field-effect transistor element 108. Such element further comprises a drain runner 109, and a source shield 113. The field-effect transistor is embodied as a laterally diffused metal-oxide-semiconductor (“LDMOS”) transistor of which the details are well known.

[0054] Drain runners 109 are connected to a drain bondbar 111. From this latter bondbar bondwires 112 extend for outputting an output signal.

[0055] RC-filter 104 differs from RC-filter 4 of FIG. 1B in that gate resistor R1 is distributed over the n field-effect transistor elements 108. The Applicant has found that this arrangement of the gate resistor considerably improves the stability of the overall field-effect transistor to such an extent that a gate layout can be used as shown in FIG. 3A. This arrangement presents a more efficient use of die area and introduces less parasitic effects when compared to the gate layout shown in FIG. 1A. Consequently, the power efficiency of the resulting field-effect transistor can be greatly improved.

[0056] FIG. 3C illustrates how semiconductor die 101 can be used inside an amplifier package 200. Here, package 200 comprises a heat-conducting substrate 201 on which semiconductor die 101 is mounted. Package 200 further comprises an input lead 202 and an output lead 203 that both extend from the outside to the inside of package 200. Bondwires 204 are used for connecting these leads to gate bondbar 102 and drain bondbar 111, respectively.

[0057] The top layout of the field-effect transistor of FIG. 3A largely corresponds to that of FIG. 2C. The cross-sectional views corresponding to lines A and B of FIG. 2C are illustrated in FIGS. 4A and 4B, respectively, where the same reference signs have been used to refer to identical or similar components.

[0058] A crucial difference between the field-effect transistor of FIG. 4B and that of FIG. 2B is the presence of gate resistor 818 that extends from gate island 817. Gate resistor 818 can be made of the same material as gate island 817, e.g. polysilicon. However, as the function of gate resistor 818 is to improve stability, the resistance of gate resistor 818 should be much higher than that of gate island 817. This difference in resistance can be achieved using a different processing of the polysilicon as will be explained later with reference to FIGS. 5A-5E.

[0059] It should be noted that a clear distinction between gate island 817 and gate resistor 818 is not always possible. The purpose of gate island 817 is to enable a connection between the gate finger, which has a short gate length, and the upper metal layers 811, 813, 815. This function can also be at least partially achieved using gate resistor 818. However, as the processing of gate resistor 818 should not affect gate finger 807, some margin should preferably be observed.

[0060] In an example, RC filter 4 in FIG. 1B may comprise the values of R1=0.7 Ohm, R2=12 Ohm, and C1=300 pF. This would roughly translate into an RF-filter 104 in which similar values for R2 and C1 are used, but, due to the distribution of R1, a value of 3200 Ohm should be used for each gate resistor 818 in each field-effect transistor element 108.

[0061] FIGS. 5A-5E illustrate an example of processing polysilicon to achieve the simultaneous formation of a gate contact, a gate island, and a gate resistor in accordance with the present disclosure.

[0062] As a first step, shown in FIG. 5A, a SiO2 gate oxide 806 is deposited on substrate 801. Thereafter, as shown in FIG. 5B, a layer of polysilicon 830 is provided on top of gate oxide 806. This layer is masked using a masking layer 831 such as photoresist or an oxide or nitride to provide selective openings 832 through which a dopant can be diffused into the polysilicon according to arrow A1. Hereinafter, the doped region of polysilicon layer 830 will be referred to as region 830A.

[0063] Next, as shown in FIG. 5C, another masking layer 833 will be provided for patterning polysilicon layer 830, 830A. More in particular, the non-masked regions of this layer will be removed as shown in FIG. 5D. Next, another masking layer 834 will be used for defining the areas of the polysilicon that should be silicidized. The process typically comprises depositing a metal layer on top of the polysilicon as illustrated by arrow A2 and subsequently performing an annealing step to cause the polysilicon and the metal to react. This will result in two regions as shown in FIG. 5E, i.e. a region 830A1 which has been subjected to dopant diffusion and silicidization, and a region 830A1 which has only been subjected to silicidization. Here, in FIG. 5E, region 830 could be used as gate resistor 818, region 830A2 as gate island 817, and region 830A1 as gate finger 807.

[0064] In the above, the present invention has been explained using embodiments thereof. However, the skilled person will appreciate that the present invention is not limited to these embodiments but that various modifications are possible without deviating from the scope of the invention, which is defined by the appended claims.