Damascene template for nanoelement printing fabricated without chemomechanical planarization

Abstract

Methods of fabricating a damascene template for electrophoretic assembly and transfer of patterned nanoelements are provided which do not require chemical mechanical polishing to achieve a uniform surface area. The methods include conductive layer fabrication using a combination of precision lithography techniques using etching or building up the conductive layer to form raised conductive features separated by an insulating layer of equal height.

Claims

1. A method of fabricating a damascene template for the electrophoretic assembly and transfer of patterned nanoelements, the method comprising the steps of: (a) providing a substantially planar substrate; (b) depositing an adhesion layer onto the substrate; (c) depositing a conductive metal layer onto the adhesion layer; (d) depositing a layer of lithography resist onto the conductive metal layer; (e) performing lithography to create a two-dimensional pattern of voids in the resist layer, whereby a plurality of surfaces of the conductive metal layer are exposed in the voids; (f) depositing a chromium mask layer onto the resist layer, whereby the voids are filled with said chromium to form chromium nanostructures covering the conductive metal layer according to said two-dimensional pattern; (g) removing the resist layer and the chromium mask layer thereupon, leaving the chromium nanostructures on the conductive metal layer; (h) etching the conductive metal layer which is not covered by the chromium nanostructures, leaving raised conductive metal features in the conductive metal layer corresponding to said two-dimensional pattern; (i) depositing an insulating layer onto the chromium nanostructures and exposed conductive metal surfaces in regions between the raised conductive metal features resulting from step (h), wherein the thickness of the insulating layer in the regions between the raised conductive metal features is essentially the same as the height of the raised conductive metal features; and (j) etching to remove the chromium nanostructures and portions of the insulating layer covering the chromium nanostructures, forming said damascene template, wherein the damascene template has an essentially planar surface comprising said raised conductive metal features separated by said insulating layer, and wherein surfaces of the raised conductive metal features and the insulating layer are essentially coplanar.

2. The method of claim 1, wherein the etching in step (h) is performed by ion milling.

3. The method of claim 1, wherein the thickness of the insulating layer in the regions between the raised conductive metal features is within about 5%, preferably within about 2%, of the height of the raised conductive metal features.

4. The method of claim 1, wherein the resulting damascene template is essentially free of dishing and erosion defects.

5. The method of claim 1, wherein the method does not comprise the use of chemomechanical polishing.

6. The method of claim 1, wherein the insulating layer comprises silicon dioxide, and further comprising, after step (j): (k) silanizing exposed surfaces of the insulating layer with a hydrophobic silane compound.

7. The method of claim 1, wherein the etching of step (j) comprises the use of sonication.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of one embodiment of a damascene template fabrication process according to the present technology. In this process, a combination of lithography and etching using ion milling is used to produce raised conductive metal features.

(2) FIG. 2 is a schematic diagram of another embodiment of a damascene template fabrication process according to the present technology. In this process, raised conductive metal features are produced by a combination of lithography and conductive metal layer deposition.

(3) FIGS. 3A and 3B show two different strategies for creating templates for nanoelement and transfer. In the strategy depicted in FIG. 3A, the metal conductive elements protrude above an insulating layer, which gives rise to a non-uniform electric field and leaves the conductive features susceptible to breaking off during use. In the strategy depicted in FIG. 3B, and used in the present technology, the raised metal features are connected through a metal film underneath the insulating layer, which gives rise to a uniform electric field, and the integration of the raised conductive features with the insulating layer stabilizes the conductive features against break-off.

(4) FIGS. 4A and 4B are schematic diagrams that illustrate how using a damascene template having a flat surface gives rise to more complete and more uniform nanoelement transfer. FIG. 4A shows damascene templates having conductive features that are recessed (left), co-planar with the interspersed insulating layer (middle), or protruding above the insulating layer (right). FIG. 4B shows the typical results of nanoelement transfer damascene templates shown in FIG. 4A.

(5) FIGS. 5A and 5B are schematic depictions of non-uniform surface geometry typically observed near a wafer edge during (5A) and following (5B) a chemical mechanical polishing (CMP) process. See H. Jeong et al., Int. J. Precis. Eng. Man., 2013, V14, pp 11-15.

(6) FIG. 5A shows the pressure distribution across a wafer surface during CMP. FIG. 5B shows a zone of edge exclusion caused by different polishing rates in different parts of a wafer during CMP.

(7) FIG. 6 is a schematic depiction of the results of dishing and erosion defects resulting from CMP.

(8) FIGS. 7A and 7B are schematic representations depicting the effect of thickness of the chromium mask layer in a fabrication process for a damascene template. In FIG. 7A, a thick Cr mask layer leaves residue of the silicon dioxide insulating layer when the mask and excess insulating layer are lifted off with the aid of sonication. The result of an experiment is shown at the right as an atomic force microscopy (AFM) image and scan of the image. FIG. 7B shows an optimal result (flat template surface) obtained with an appropriately thick Cr mask layer.

(9) FIG. 8 schematically depicts an embodiment of a nanoelement assembly and transfer process used to prepare a biosensor for detecting lactate. The damascene template is used to assemble a strip of single-walled carbon nanotubes (SWNT), which is transferred onto a flexible polymer substrate, followed by fabrication of electrodes contacting the SWNT strip and functionalization of the SWNT using lactate oxidase-coupled nanoparticles and a linker.

(10) FIG. 9 is a schematic diagram of an embodiment of a fabrication process for a nanocircuit containing a patterned arrangement of nanowires assembled from metal nanoparticles on a flexible polymer substrate according to the present technology.

DETAILED DESCRIPTION

(11) Methods for fabrication of damascene templates for the electrophoretic assembly and transfer of patterned nanoelements are provided that overcome limitations of current fabrication methods which utilize chemical mechanical polishing (CMP). Instead of using CMP to produce a highly planar template, whose surface contains a co-planar mixture of conductive features filled in by an insulating material, the present technology uses high precision lithography to produce raised conductive features and an interspersed insulating layer of equal height, resulting in a planar surface. The technology utilizes two alternative methods to fabricate damascene templates. One method uses etching of the conductive layer by ion milling to create a two-dimensional pattern of raised conductive features (FIG. 1). The other method uses lithography to build up a conductive layer in two stages, the second of which creates the two-dimensional pattern of raised conductive features (FIG. 2). Both methods utilize chromium masks to create the pattern of raised conductive features followed by chromium etching.

(12) The damascene fabrication methods of the present technology are designed to fulfill two objectives: (1) to achieve equal electric potential on all the conductive features regardless of size, shape, density or position on the template, and (2) maximal flatness over the entire damascene template surface. Both characteristics are important for achieving efficiency and evenness of nanoelement transfer in an offset printing process. Equal potential on all of the nano, micro, and/or macro scale conductive features is obtained by connecting the features with a conductive film underneath an insulating layer. A flat template surface is achieved using highly controlled and precise chip fabrication processes (i.e., matching the height or thickness of the raised conductive features and the interspersed insulating layer).

(13) Uniform assembly of nanomaterials is generally carried out using a uniform electric field. However, when the conductive features on a template for electrophoretic assembly and transfer are of different scale, the potential significantly drops at the smaller-scale features even if all the features are connected to each other. Also, there is a risk of peeling off of the conductive features due to poor adhesion to the substrate. Connecting the conductive features by a metal film underneath an insulating layer, as described below, allows uniform potential regardless of feature size (compare FIGS. 3A, 3B). At the same time, it strengthens the conductive features such that they are not peeled off from the template during transfer.

(14) The damascene template of the present technology is designed to have flat topography over the whole surface of the template, including both surfaces of the conductive patterns and those of regions between the conducting patterns, i.e., the insulating regions. A flat topography is useful for achieving both uniform assembly of nanomaterials and high efficiency of transfer of nanomaterials. The present technology uses precisely controlled etching of metal layers and deposition of insulating layer to achieve flat topography.

(15) FIGS. 4A and 4B illustrate why a template surface with flat surface is advantageous in an assembly and transfer process. FIG. 4A shows damascene templates assembled with either flat (middle) or non-flat (left and right) surfaces. Note that before assembly, in the template on the left the insulating regions project outwards, whereas in the template on the right the conductive features project outwards. FIG. 4A also shows the various templates with assembled nanoelements. FIG. 4B depicts the results of transfer using each of the three templates. The template with flat topography (middle) is expected to result in a perfect transfer and ready to be used in the next transfer. The template on the left is expected to result in imperfect transfer and not expected to be ready to be used in the next transfer without extensive cleaning to remove adherent nanoelements. The template on the right is expected to lead to imperfect transfer due to nanoelements that adhere to the sides of the raised conductive features during assembly.

(16) Available methods of transferring nanomaterials through printing using a template sacrificial layer and intermediate sacrificial films cannot be reused and require additional fabrication steps leading to higher production costs..sup.14-16 Transfer printing using damascene template can be used for fabricating microscale and nanoscale structures, including combinations of microscale and nanoscale structures on a single chip, without the need for an intermediate film..sup.17-18 A damascene template allows electrophoretic assembly of nanomaterials only on the conductive patterns, not on the insulating layer. However, this demarcation is not total. In order to further ensure selective assembly of nanomaterials only on the conductive features, the technology described herein includes reducing the surface energy of the insulating region to prevent the assembly of nanomaterials in these regions. Surface energy of the insulating regions can be reduced using self-assembled monolayers (SAM) without affecting the surface energy of the conductive features. A silane compound with a long chain can be selectively reacted with a SiO.sub.2 (insulating) surface in order to change the surface energy from hydrophilic to hydrophobic without affecting the surface energy of the conductive features. For example, octadecyltrichlorosilane (OTS) or similar compounds (e.g., varying the alkyl chain length) may be used to form the SAM for making the SiO.sub.2 surface hydrophobic. SAM, selectively formed only on the insulating area, enhances directed assembly on conductive features, transfer of nanomaterials with high efficiency, and further allows the damascene template to be reused.

(17) Fabrication of a damascene template according to the present technology results in a template with a flat and uniform surface without the use of CMP. Although CMP is currently used to obtain uniform surface features, it is not suitable when the template is of the scale of a typical wafer or larger. CMP makes a smooth surface possible, but with CMP it is not possible to obtain a uniform flat surface over the entire wafer from edge to edge due to intrinsic limitations of the basic polishing mechanism..sup.22 With use of CMP, the polishing rates between the wafer center and the area near the wafer edge are significantly different, resulting in non-uniform geometry. See FIGS. 5A and 5B. The non-uniform geometry decreases the efficiency of both assembly and transfer. Thus, reliance on CMP limits the template size to only a portion of the size of a wafer, while high productivity requires that the template be much larger even than an entire wafer. Another drawback of the CMP process is that it can lead to “dishing” and “erosion” defects which lead to a nonuniform geometry near the conductive features. See FIG. 6. These defects are caused by different polishing rates achieved with different materials (e.g., insulating vs. conducting). The difference can be more significant when the template has a multi-scale pattern (i.e., more than one of macro, micro, and nano scale features) and a non-uniform pattern density.

(18) The fabrication of damascene templates according to the present technology is described in greater detail in the following. In one embodiment of the fabrication method, shown in FIG. 1, a conductive metallic layer 103 (e.g., Au, Ni, or W) is first deposited on a substrate 101, e.g., a silicon wafer. Evaporation or sputtering may be used for depositing the metallic layer. Depending on the specific metal used, an adhesive layer 102, made of Cr, Ti, or Ni, is deposited between the metallic layer 103 and the substrate 101. A resist layer 104 (e.g. PMMA), suitable for lithography, is deposited over the metallic layer. Next, a two-dimensional pattern of voids 105 is produced in the resist layer using lithography such that the surface of the conductive metal layer is exposed in the voids. Electron beam lithography may be used to produce this two-dimensional pattern of voids. Subsequently, a thin mask of chromium nanostructures 106 of a desired pattern is formed on the metallic layer 103. To obtain the chromium nanostructures, a layer of chromium is deposited over the resist layer 104. In the voids 105, the chromium layer comes into contact with the conductive metal layer. The chromium layer is then selectively removed from regions having the resist layer (i.e., from regions excluding the voids 105). Next, the conductive metal regions exposed as a result of the chromium layer removal are partially etched using a dry-etching process, such as ion milling. The etching leaves behind raised conductive metal features 110 in the conductive metal layer. These raised metal features correspond to the above-described two-dimensional pattern of voids produced by lithography. Their surfaces are covered by the chromium nanostructures 106. In the next step, an insulating layer 112, e.g., a SiO.sub.2 film, is deposited over the entire template, causing both the chromium nanostructures and the exposed conductive metal surfaces in regions between the raised conductive metal features to be covered with the insulating layer. The deposition may be performed using Plasma enhanced chemical vaporized deposition (PECVD). It should be noted that the insulating layer deposition is carried out in a highly controlled fashion such that the thickness of the insulating layer in the regions between the raised conductive metal features, indicated by the reference numeral 113, is essentially the same as the height of the raised conductive metal features 114. Finally, the chromium nanostructures 106 are removed using a liquid etchant, accompanied optionally with sonication, resulting in formation of the damascene template.

(19) Another embodiment of the fabrication method is shown in FIG. 2. In this embodiment as well, initially a conductive metallic layer 103 is deposited on a substrate 101. An adhesive layer 102 is optionally deposited between the metallic layer 103 and the substrate 101. Next, a resist layer 104 suitable for lithography is deposited over the metallic layer. As in the embodiment above, lithography is performed to produce a two-dimensional pattern of voids 105. In these voids, the conductive metal layer is exposed. Subsequently, a second conductive metal layer 207 is deposited onto the resist layer so as to cover both the voids and residual resist layer. A chromium layer is next deposited on the second conductive metal layer, whereby chromium nanostructures 208 are formed over the second conductive metal layer 207, both in the voids 105 and in the regions between the voids. Reference numeral 205 depicts the conductive metal layer forming the walls of the voids, the base of the voids being by chromium. In the next step, the resist layer is removed, which leaves behind raised conductive metal features 211, topped with chromium nanostructures 209, only in the voids. These raised metal features correspond to the two-dimensional pattern of voids produced by lithography. Next, as in the embodiment described above, an insulating layer 212 is deposited over the entire template to cover both the chromium nanostructures 209 and the exposed conductive metal surfaces in regions between the raised conductive metal features. Again, deposition is carried out in a highly controlled fashion such that the thickness of the insulating layer in the regions between the raised conductive metal features, reference numeral 113, is essentially the same as the height of the raised conductive metal features 214. In the final step, the chromium nanostructures 209 are removed using a liquid etchant, accompanied optionally with sonication, thereby resulting in the damascene template.

(20) The damascene template produced by each of the above-described fabrication methods has an essentially planar surface, includes raised conductive metal features 114/214 separated by said insulating layer 113/213. Further, the raised features generally protrude at a 90° angle above the plane of the rest of the metallic conductive layer, and the surfaces of the raised conductive metal features and the insulating layer in the damascene template are essentially coplanar.

(21) In the methods above, a flawless lift off, i.e., perfect removal of the chromium nanostructures, requires that thickness of the chromium layer deposited on the metallic be optimum. If the chromium layer is thick, the insulating material cannot be removed completely during lift off, resulting in some of the material remaining as residues on the edges of conductive features. This is apparent from FIG. 7A, showing lift off with sonication. Some of the insulating material, SiO.sub.2, is seen remaining attached to the raised conductive metal features. On the other hand, if the chromium layer is optimized to be thin, the insulating material can be removed completely, resulting in a smooth surface or a flat topography on the template surface (FIG. 7B, left). In various embodiments, the thickness of the chromium layer can be, for example, from 2 nm to 25 nm, or from 1 nm to 15 nm, or from 1 nm to 10 nm, or from 5 nm to 30 nm, or from 20 nm to 50 nm, or from 30 nm to 100 nm. Surface topography was measured for both thick and thin chromium layer using atomic force microscopy (AFM) and compared (FIGS. 7A and 7B, right).

(22) As previously described, a self-assembled monolayer (SAM) selectively formed on the insulating area enhances both directed assembly of the nanomaterials on the conductive features and efficiency of transfer of the nanomaterials (115/215 in FIGS. 1 and 2). Efficient transfer allows the damascene template to be reused. An embodiment of the technology uses OTS to selectively form a hydrophobic surface on the SiO.sub.2 regions of the template. To form an OTS SAM on the SiO.sub.2 surface, a template made according to the described methods was pre-cleaned for 3 min with a freshly prepared piranha solution (sulfuric acid:hydrogen peroxide=2:1). The template was rinsed under the running deionized water (DIW) for 5 min and dried with a stream of nitrogen. OTS-SAM was formed by immersing the damascene template into a toluene solution containing 1.4 vol. % OTS for 2 min. Next, the template was rinsed with toluene to remove physically adsorbed OTS on the gold surface, followed by drying with a stream of nitrogen. OTS-SAM is non-covalently attached to the gold surface. To completely remove OTS-SAM from the conductive features (Au), the template was again immersed in piranha solution for a short period, rinsed, and dried with nitrogen.

(23) Transfer printing onto recipient substrates can enable the production of various types of new devices including thin-film transistors, gas sensors, and biosensors..sup.19-21 A flexible enzymatic biosensor and a printed nanoscale metal circuit on flexible substrate are shown below as examples of applications of the present technology.

(24) The damascene template produced according to the present technology can be used to fabricate a sensor using nanomaterials such as CNT, MoS.sub.2, and organic nanoparticles. Accordingly, an enzymatic lactate sensor is developed using a single walled carbon nanotube (SWNT) strip or channel functionalized by the enzyme lactate oxidase (LOD). See FIG. 8. The enzyme reacts only with lactate, thereby allowing the SWNT channel to specifically detect a lactate signal. SWNTs are assembled on the damascene template and then transferred to a polymer recipient substrate, such as a polyester (e.g., PET) film. Subsequently metal electrodes are deposited on the assembled SWNT channel, and the channel functionalized with the enzyme.

(25) The damascene template described herein provides an efficient way of fabricating nanoscale metal circuits on a flexible substrate using the assembly and transfer process of metal nanoparticles. This process is schematically shown in FIG. 9.

REFERENCES

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(27) As used herein, “consisting essentially of” allows the inclusion of materials or steps that do not materially affect the basic and novel characteristics of the claim. Any recitation herein of the term “comprising”, particularly in a description of components of a composition or in a description of elements of a device, can be exchanged with “consisting essentially of” or “consisting of”.

(28) While the present technology has been described in conjunction with certain preferred embodiments, one of ordinary skill, after reading the foregoing specification, will be able to effect various changes, substitutions of equivalents, and other alterations to the compositions and methods set forth herein.