SYSTEM AND METHOD FOR DETERMINING THE THERMAL RESISTANCE OF A POWER SEMICONDUCTOR DEVICE

Abstract

A system for determining thermal resistance of a power semiconductor includes a constant current source to apply a constant drain current to a drain terminal of the power semiconductor device, an adjustable gate voltage source to apply a gate voltage signal to a gate terminal of the power semiconductor device, a drain-source voltage sensor coupled between the drain terminal and the source terminal to measure a value of the current drain-source voltage across the power semiconductor device and to output a corresponding drain-source voltage signal, a gate controller to determine a difference between the drain-source voltage signal and a constant reference voltage and to control the output of the adjustable gate voltage source dependent on the determined difference, and a system controller to determine a thermal resistance of the power semiconductor device on the basis of the applied drain current and the measured drain-source voltage.

Claims

1. A system for determining thermal resistance of a power semiconductor device, the system comprising: a constant current source configured to apply a constant drain current to a drain terminal of the power semiconductor device; an adjustable gate voltage source configured to apply a gate voltage signal to a gate terminal of the power semiconductor device; a drain-source voltage sensor coupled between the drain terminal and the source terminal, the drain-source voltage sensor being configured to measure a value of the current drain-source voltage across the power semiconductor device and to output a corresponding drain-source voltage signal; a gate controller configured to determine a difference between the drain-source voltage signal and a constant reference voltage and to control the output of the adjustable gate voltage source dependent on the determined difference; and a system controller configured to determine a thermal resistance of the power semiconductor device on a basis of the applied drain current and the measured drain-source voltage.

2. The system of claim 1, further comprising a gate-source voltage sensor coupled between the gate terminal and the source terminal, the gate-source voltage sensor configured to measure a value of the gate-source voltage across the power semiconductor device.

3. The system of claim 2, wherein the system controller is configured to measure deviations of the gate-source voltage measured by the gate-source voltage sensor over time and to determine the thermal resistance of the power semiconductor device if the measured deviations of the gate-source voltage remain within a tolerance band for a predetermined amount of time.

4. The system of claim 1, wherein the gate controller includes a voltage source controller configured to output a gate voltage control signal to the adjustable gate voltage source.

5. The system of claim 4, wherein the gate controller further includes an adder configured to receive the drain-source voltage signal and the constant reference voltage from the system controller and to output the determined difference to the voltage source controller.

6. The system of claim 5, wherein the voltage source controller includes an integration operational amplifier and the adder includes a differential operational amplifier.

7. The system of claim 1, wherein the system controller is configured to measure deviations of the drain-source voltage signal over time and to determine the thermal resistance of the power semiconductor device if the measured deviations of the drain-source voltage signal remain within a tolerance band for a predetermined amount of time.

8. A method for determining thermal resistance of a power semiconductor device, the method comprising: applying a constant drain current to a drain terminal of the power semiconductor device; applying a gate voltage signal to a gate terminal of the power semiconductor device; measuring a current drain-source voltage across the power semiconductor device and determining a difference between the current drain-source voltage and a constant reference voltage; controlling the gate voltage signal dependent on the determined difference to minimize the determined difference; and determining a thermal resistance of the power semiconductor device on a basis of the applied drain current and the measured drain-source voltage.

9. The method of claim 8, further comprising measuring deviations of the gate-source voltage across the power semiconductor device over time.

10. The method of claim 9, wherein determining the thermal resistance of the power semiconductor device is only performed if the measured deviations of the gate-source voltage remain within a tolerance band for a predetermined amount of time.

11. The method of claim 8, further comprising measuring deviations of the drain-source voltage across the power semiconductor device over time.

12. The method of claim 11, wherein determining the thermal resistance of the power semiconductor device is only performed if the measured deviations of the drain-source voltage remain within a tolerance band for a predetermined amount of time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments of this disclosure will now be described, by way of nonlimiting example, with reference to the accompanying drawings. The disclosure herein will be explained in greater detail with reference to example embodiments depicted in the drawings as appended.

[0028] The accompanying drawings are included to provide a further understanding of the disclosure herein and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the disclosure herein and together with the description serve to explain the principles of the disclosure herein. Other embodiments of the disclosure herein and many of the intended advantages of the disclosure herein will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0029] FIG. 1 illustrates an example circuit design of a system for determining the thermal resistance of a power semiconductor and for estimating junction temperatures of a housed power semiconductor module according to some embodiments of the disclosure herein.

[0030] FIG. 2 illustrates example timing graphs of various characteristic parameters of a power semiconductor module that occur during a method for estimating junction temperatures of the same according to some embodiments of the disclosure herein.

[0031] FIG. 3 depicts blocks of a flow diagram of a method for determining the thermal resistance of a power semiconductor according to some embodiments of the disclosure herein.

[0032] FIG. 4 depicts blocks of a flow diagram of a method for estimating junction temperatures of a power semiconductor module according to some embodiments of the disclosure herein.

DETAILED DESCRIPTION

[0033] The following description of certain embodiments presents various descriptions of specific embodiments. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the disclosure herein. Generally, this application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0034] FIG. 1 illustrates an example circuit design of a system 10 including a three-terminal power semiconductor device 1. The system 10 may in some configurations be used for determining the thermal resistance R.sub.Th of the power semiconductor device 1. The system 10 may in some other configurations also be used for estimating junction temperatures T.sub.J of the power semiconductor device 1 when it is included in a power semiconductor module.

[0035] The system 10 depicted in FIG. 1 may be used in methods for determining the thermal resistance of the power semiconductor device 1 and/or for methods estimating junction temperatures T.sub.J of the power semiconductor device 1 when it is included in a power semiconductor module, such as for example the methods M1 and/or M2 as exemplarily illustrated and explained in conjunction with FIGS. 3 and 4. During the execution of the method M2 of FIG. 4, the power semiconductor device 1 will undergo several stages of operations, the characteristic electrical and thermal parameters of which are exemplarily illustrated and explained in conjunction with FIG. 2.

[0036] The power semiconductor device 1, for example a metal-oxide semiconductor field-effect transistor (MOSFET), includes a drain terminal D, a gate terminal G and a source terminal S. A constant current source 2 is coupled between the drain terminal D and the source terminal S. The constant current source 2 is controlled to apply a drain current I.sub.D of constant adjustable value to the drain terminal D.

[0037] An adjustable gate voltage source 5 is coupled to the gate terminal G. A gate voltage signal U.sub.G can be applied to the gate terminal G, causing a gate-source voltage U.sub.GS to drop between the gate terminal G and the source terminal S. The gate source voltage U.sub.GS may for example be measured by a gate-source voltage sensor 4 that is coupled between the gate terminal G and the source terminal S.

[0038] A drain-source voltage sensor 3 is coupled between the drain terminal D and the source terminal S. The drain-source voltage sensor 3 can measure a value of the current drain-source voltage across the power semiconductor device 1. The drain-source voltage sensor 3 outputs a corresponding drain-source voltage signal indicating the respective drain-source voltage U.sub.DS.

[0039] The drain-source voltage signal is output to a gate controller 6 that is in general configured to determine a difference Δ.sub.DS between the drain-source voltage signal U.sub.DS and a constant reference voltage U.sub.C for the drain-source voltage. The constant reference voltage U.sub.C is the value that the drain-source voltage is to be stabilized on. The gate controller 6 includes an adder 8, for example a differential operational amplifier, that receives the drain-source voltage signal U.sub.DS and a constant reference voltage U.sub.C as input and outputs the difference Δ.sub.DS between the drain-source voltage signal U.sub.DS and a constant reference voltage U.sub.C.

[0040] The difference Δ.sub.DS is routed to a voltage source controller 7 downstream of the adder 8 in the gate controller 6. The voltage source controller 7 produces a gate voltage control signal C.sub.GS that is output to the adjustable gate voltage source 5 for controlling the applied gate voltage signal U.sub.G. As a rising gate-source voltage U.sub.GS will cause the drain-source voltage U.sub.DS to drop, any increase in the drain-source voltage U.sub.DS due to a rising junction temperature T.sub.J within the power semiconductor device 1 can be compensated for by a controlled decrease due to an increasing gate-source voltage U.sub.GS. Thus, the difference Δ.sub.DS serves as a control value for the control loop implemented between the drain-source voltage sensor 3 and the adjustable gate voltage source 5. If the difference Δ.sub.DS is minimized, the drain-source voltage U.sub.DS may be kept at a sufficiently constant level.

[0041] A system controller 9 is coupled to the gate controller 6, the constant current source 2, the drain-source voltage sensor 3 and optionally to the gate-source voltage sensor 4. The system controller 9 is configured to set the value of the drain current I.sub.D to be applied to the drain terminal D of the power semiconductor device 1. The system controller 9 further receives the value of the drain-source voltage U.sub.DS and is able to calculate the thermal resistance R.sub.Th of the power semiconductor device 1 in dependency from, i.e. on the basis of the applied drain current I.sub.D and the measured drain-source voltage U.sub.DS as follows:

R.sub.Th=ΔT.Math.P.sub.L.sup.−1=ΔT.Math.I.sub.D.sup.−1.Math.U.sub.DS.sup.−1,

where ΔT is the temperature difference between the junction temperature T.sub.J and the ambient temperature T.sub.A due to which the power loss P.sub.L occurs.

[0042] One of the aims of the gate controller 6 is to adjust electrical parameters of the power semiconductor device 1 in a way that a defined amount of power losses at a constant loss rate within the power semiconductor device 1 may be established. The on-state resistance R.sub.DSon and thus the drain-source voltage U.sub.DS are dependent on the junction temperature T.sub.J within the power semiconductor device 1. Therefore, if a constant drain current I.sub.D is applied to the drain terminal D, the occurring heat losses within the power semiconductor device 1 will give rise to a rise of the junction temperature T.sub.J.

[0043] The system controller 9 can wait with the determination until a thermal equilibrium has been established at the junctions within the power semiconductor device 1. To determine whether an equilibrium has been reached, the system controller 9 can measure the deviations of the gate-source voltage measured by the gate-source voltage sensor 4 or, alternatively or additionally, the deviations of the drain-source voltage signal U.sub.DS over time. If the respectively measured deviations do not exceed a stability threshold for a predetermined amount of time the system controller 9 can assume that a sufficient thermal equilibrium has been established and that the calculation of the thermal resistance R.sub.Th is sufficiently accurate.

[0044] FIG. 3 shows a method M1 for determining the thermal resistance of a power semiconductor device 1. In a first step M11, a constant drain current I.sub.D is applied to a drain terminal D of the power semiconductor device 1. Then, a second step M12 involves applying a gate voltage signal U.sub.G to a gate terminal G of the power semiconductor device 1. The gate voltage signal U.sub.G causes a gate-source voltage U.sub.GS to drop over the power semiconductor device between the gate terminal G and the source terminal S. The gate-source voltage U.sub.GS will influence the value of the drain-source voltage U.sub.DS over the power semiconductor device 1.

[0045] This current value of the drain-source voltage across the power semiconductor device 1 is measured in a third step M13. The measured value of the drain-source voltage will differ from a constant reference voltage U.sub.C that may for example be given by a system controller such as the system controller 9 of FIG. 1. This difference Δ.sub.DS between the current drain-source voltage and a constant reference voltage U.sub.C can be determined and will be used as feedback signal to control the gate voltage signal U.sub.G in order to minimize the determined difference Δ.sub.DS in a fourth step M14. Steps M12 to M14 will be repeated until an equilibrium has been established, i.e. until the power loss rate over the power semiconductor device 1 is constant.

[0046] It may be possible to measure deviations of the gate-source voltage and/or the drain-source voltage U.sub.DS across the power semiconductor device 1 over time. When the measured deviations have remained under a stability threshold for a predetermined amount of time, the system controller 9 can determine that thermal equilibrium has been reached and that in a fifth step M15, the thermal resistance R.sub.Th of the power semiconductor device 1 may be determined, for example by calculating:

R.sub.Th=ΔT.Math.P.sub.L.sup.−1=ΔT.Math.I.sub.D.sup.−1.Math.U.sub.DS.sup.−1,

where ΔT is the temperature difference between the junction temperature T.sub.J and the ambient temperature T.sub.A due to which the power loss P.sub.L occurs.

[0047] The system 10 of FIG. 1 may be used to thermally characterize a housed power semiconductor module including one or more power semiconductor devices therein without having to open the housing or the encapsulation in order to gain access for purposes of thermal sensors or infrared cameras. FIG. 2 shows example timing graphs of various characteristic parameters of a power semiconductor module that occur during such procedures for thermally characterizing of a power semiconductor module. The thermal characterization process illustrated herein may be particularly useful for a housed power semiconductor module. The graphs qualitatively illustrate the temporal course of (from top to bottom) the gate-source voltage U.sub.GS, the drain-source voltage U.sub.DS, the drain current I.sub.D, the power loss P.sub.L at the junctions of the power semiconductor device and the junction temperature T.sub.J of the power semiconductor device.

[0048] In a first stage B1, a constant drain current I.sub.D is applied by the system controller 9 so that power losses P.sub.L of a first amount P.sub.1 occur in the power semiconductor device 1. These power losses will lead to an increasing junction temperature T.sub.J. In order to combat the concomitant rise of the drain-source voltage U.sub.DS the closed-control feedback loop of the gate controller 6 will raise the gate-source voltage U.sub.GS in a controlled manner so that the drain-source voltage U.sub.DS will remain essentially constant.

[0049] This constant level of the drain-source voltage U.sub.DS will carry over to a second stage B2 in which the junction temperature T.sub.J has stabilized to a constant value T.sub.1 and the gate-source voltage U.sub.GS does not need to be varied any more. The system controller 9 can determine if the deviations in the measured values of the drain-source voltage over time remain within a tolerance band, i.e. that the measured values of the drain-source voltage do not significantly change over time. Depending on the expected time for having the junction temperature T.sub.J settle on a stable value, the second stage B2 may last for a timespan predetermined by the system controller 9.

[0050] After the second stage B2, in which the power semiconductor device 1 is operated in Ohmic mode, the system controller 9 will cause the gate voltage source 5 to abruptly apply a higher value of the gate voltage to the power semiconductor device 1 so that the power semiconductor device 1 is switched to its fully conducting state, i.e. is operating in the saturation region. In this third stage B3, the on-state resistance R.sub.DSon can be estimated from the constant drain current I.sub.D and the drain-source voltage U.sub.DS at the (now) constant level UR to which the drain-source voltage U.sub.DS will drop. The determined on-state resistance R.sub.DSon will allow for estimating the junction temperature T.sub.J within the power semiconductor device 1. The junction temperature T.sub.J directly correlates with the on-state resistance R.sub.DSon—such a correlation may for example be separately determined by heating the power semiconductor device 1 externally without loading it and by determining the drain-source resistance when thermal equilibrium under external heating has been reached. Thus, the measurement of the drain-source voltage U.sub.DS and drain current I.sub.D in the third stage B3 can be used for purposes of determination of the on-state resistance R.sub.DSon.

[0051] Of course, the junction temperature T.sub.J will drop slightly during the third stage B3 but if the measurements are done quickly enough this temperature drop will be insignificant in terms of accuracy of temperature estimation. It should be clear that the length of the third stage B3 may be significantly shorter than any of the previous stages B1 and B2 but has not been depicted to scale in order to better explain the process.

[0052] The entire process may now be repeated for different values of the constant drain current I.sub.D and/or the gate-source voltage U.sub.GS in order to obtain a characterization profile of the power semiconductor module. In the example depicted in FIG. 2 the fourth stage B4 will keep the drain current I.sub.D at the same level as before, but the gate-source voltage U.sub.GS is lowered to incite a higher level of the drain-source voltage U.sub.DS and, consequently, a higher level P.sub.2 of power losses P.sub.L. Then, the process will repeat fifth, sixth, and seventh stages B5, B6, and B7, respectively, which work analogously to the first, second, and third stages B1, B2, and B3, respectively, only for higher values of the drain-source voltage U.sub.DS and the junction temperature T.sub.J which will now rise to a stable temperature T.sub.2 higher than the previous temperature T.sub.1.

[0053] It should be clear that the gate-source voltage U.sub.GS, the drain current I.sub.D and the drain-source voltage U.sub.DS may be adjusted to nearly arbitrary values in various combinations in subsequent stages of the characterization process depicted in FIG. 2 so that a thermal profile of a power semiconductor module may be established under various load conditions.

[0054] FIG. 4 illustrates a method M2 for estimating junction temperatures of a power semiconductor module. In a first step M11, a constant drain current is applied I.sub.D to a drain terminal D of a power semiconductor device 1 of the housed power semiconductor module. Then, in a second step M12, a gate voltage signal U.sub.G is applied to a gate terminal G of the power semiconductor device 1. The current drain-source voltage across the power semiconductor device 1 may be measured and a corresponding difference Δ.sub.DS between the current drain-source voltage and a constant reference voltage U.sub.C; can be determined in a third step M13.

[0055] The gate voltage signal U.sub.G may then be controlled in a fourth step M14 dependent on the determined difference Δ.sub.DS in order to minimize the determined difference Δ.sub.DS. The steps M12, M13 and M14 are iterated in a closed-control feedback loop.

[0056] The deviations of the values of the gate-source voltage across the power semiconductor device 1 over time that are measured in a fifth step M21 may eventually remain within a tolerance band so that the power semiconductor device 1 may be abruptly switched in a sixth step M22 to its fully conducting state. In this fully conducting state, i.e. when the power semiconductor device is operating in saturation, the junction temperature T.sub.J within the power semiconductor device 1 may be estimated in a seventh step M23 on the basis of the on-state resistance R.sub.DSon of the power semiconductor device 1.

[0057] In the foregoing detailed description, various features are grouped together in one or more examples with the purpose of streamlining the disclosure. It is to be understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents. Many other examples will be apparent to one skilled in the art upon reviewing the above specification.

[0058] The embodiments were chosen and described in order to best explain the principles of the disclosure herein and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure herein and various embodiments with various modifications as are suited to the particular use contemplated. In the appended claims and throughout the specification, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Furthermore, “a” or “one” does not exclude a plurality in the present case.

[0059] The subject matter disclosed herein can be implemented in association with software in combination with hardware and/or firmware. For example, the subject matter described herein can be implemented in software executed by a processor or processing unit. In one example implementation, the subject matter described herein can be implemented using a computer readable medium having stored thereon computer executable instructions that when executed by a processor of a computer control the computer to perform steps. Example computer readable mediums suitable for implementing the subject matter described herein include non-transitory devices, such as disk memory devices, chip memory devices, programmable logic devices, and application specific integrated circuits. In addition, a computer readable medium that implements the subject matter described herein can be located on a single device or computing platform or can be distributed across multiple devices or computing platforms.

[0060] While at least one example embodiment of the present invention(s) is disclosed herein, it should be understood that modifications, substitutions and alternatives may be apparent to one of ordinary skill in the art and can be made without departing from the scope of this disclosure. This disclosure is intended to cover any adaptations or variations of the example embodiment(s). In addition, in this disclosure, the terms “comprise” or “comprising” do not exclude other elements or steps, the terms “a”, “an” or “one” do not exclude a plural number, and the term “or” means either or both. Furthermore, characteristics or steps which have been described may also be used in combination with other characteristics or steps and in any order unless the disclosure or context suggests otherwise. This disclosure hereby incorporates by reference the complete disclosure of any patent or application from which it claims benefit or priority.