Merged PiN Schottky (MPS) Diode With Multiple Cell Designs And Manufacturing Method Thereof

Abstract

A semiconductor device may include a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on one side of the substrate; a plurality of regions having a second conductivity type formed under a top surface of the epitaxial layer; a first Ohmic metal patterned and deposited on top of the regions with the second conductivity type; a Schottky contact metal deposited on top of the entire epitaxial layer to form a Schottky junction; and a second Ohmic metal deposited on a backside of the substrate, wherein the regions include one or more wide regions, each having different widths that can be optimized to simultaneously obtain high surge current capability and preserve a low forward voltage drop and reverse leakage current.

Claims

1. A semiconductor device comprising: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on one side of the substrate; a plurality of regions having a second conductivity type formed under a top surface of the epitaxial layer; a first Ohmic metal patterned and deposited on top of the regions with the second conductivity type; a Schottky contact metal deposited on top of the entire epitaxial layer to form a Schottky junction; and a second Ohmic metal deposited on a backside of the substrate, wherein the regions include one or more wide regions, each having different widths that can be optimized to simultaneously obtain high surge current capability and preserve a low forward voltage drop and reverse leakage current.

2. The semiconductor device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type; and each of the regions is a P+ region.

3. The semiconductor device of claim 1, wherein the semiconductor device is a merged PiN Schottky (MPS) diode.

4. The semiconductor device of claim 2, wherein a PN junction formed between each of the P+ regions and N-type drift regions is turned on when the surge current occurs.

5. The semiconductor device of claim 2, wherein the shape of each P+ region is circle, square, hexagon, octagon, other polygons, or the combination thereof.

6. A method for manufacturing a merged PiN Schottky (MPS) diode comprising steps of: providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate, wherein a junction is formed between each region with second conductivity type and a drift region with first conductivity type, and a threshold potential to turn on the junction is determined by a width of each region.

7. The method for manufacturing a merged PiN Schottky (MPS) diode of claim 6, wherein the epitaxial layer is made of N-type silicon carbide, and the first conductivity type is P-type.

8. The method for manufacturing a merged PiN Schottky (MPS) diode of claim 6, wherein the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopants into the epitaxial layer, and removing the mask layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a cross-section view of the merged PiN Schottky (MPS) diode in the present invention.

[0018] FIG. 2 is a schematic view of a first layout design of a merged PiN Schottky (MPS) diode with circle cells.

[0019] FIG. 3 is a cross-section view of the merged PiN Schottky (MPS) diode in FIG. 2 along line AA′.

[0020] FIG. 4 is a partial enlarged cross-section view of the merged PiN Schottky (MPS) diode in FIG. 3.

[0021] FIG. 5 is a schematic view of a second layout design of a merged PiN Schottky (MPS) diode.

[0022] FIG. 6 is a schematic view of a first alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 5.

[0023] FIG. 7 is a schematic view of a second alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 5.

[0024] FIG. 8 is a schematic view of a third alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 5.

[0025] FIG. 9 is a cross-section view of the merged PiN Schottky (MPS) diode shown in FIG. 8 along line DD′.

[0026] FIG. 10 is a schematic view of a third layout design of a merged PiN Schottky (MPS) diode.

[0027] FIG. 11. shows a cross-section view of the merged PiN Schottky (MPS) diode shown in FIG. 10 along line EE′.

[0028] FIG. 12. is a schematic view of a first alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 10.

[0029] FIG. 13. is a schematic view of a second alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 10.

[0030] FIG. 14. is a schematic view of a third alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 10.

[0031] FIG. 15. is a schematic view of a fourth alternative of the second layout design of the merged PiN Schottky (MPS) diode shown in FIG. 10.

[0032] FIG. 16 shows a cross-section view of the merged PiN Schottky (MPS) diode shown in FIG. 15 along line FF′.

[0033] FIGS. 17A to 17G illustrate flow diagrams of the method for manufacturing a merged PiN Schottky (MPS) diode in the present invention.

[0034] FIG. 18 is a block diagram illustrating the method for manufacturing a merged PiN Schottky (MPS) diode in the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0035] The detailed description set forth below is intended as a description of the presently exemplary device provided in accordance with aspects of the present invention and is not intended to represent the only forms in which the present invention may be prepared or utilized. It is to be understood, rather, that the same or equivalent functions and components may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention.

[0036] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which this invention belongs. Although any methods, devices and materials similar or equivalent to those described can be used in the practice or testing of the invention, the exemplary methods, devices and materials are now described.

[0037] All publications mentioned are incorporated by reference for the purpose of describing and disclosing, for example, the designs and methodologies that are described in the publications that might be used in connection with the presently described invention. The publications listed or discussed above, below and throughout the text are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the inventors are not entitled to antedate such disclosure by virtue of prior invention.

[0038] As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes reference to the plural unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the terms “comprise or comprising”, “include or including”, “have or having”, “contain or containing” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. As used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

[0039] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0040] In one aspect as shown in FIG. 1, a merged PiN Schottky (MPS) diode 10 may include a silicon carbide substrate 12 having a first conductivity type, an epitaxial layer 13 with the first conductivity type formed on the substrate 12. In one embodiment, the doping concentration in the epitaxial layer 13 is lower than that in the substrate 12. The merged PiN Schottky (MPS) diode 10 may further include a plurality of regions 14 having a second conductivity type different from the first conductivity type, and formed on the surface of the epitaxial layer 13.

[0041] A first Ohmic contact metal 18 is formed on top of each of the regions of the second conductivity type, and a Schottky contact metal 19 is placed on top of the entire epitaxial layer 13 to form a Schottky junction 16. A second Ohmic contact 17 is formed by a cathode electrode 11 on the back side of the substrate 12.

[0042] In one embodiment, the first conductivity is N type, and the second conductivity type is P type. It is noted that in the merged PiN Schottky (MPS) diode structure, a PN junction can be formed by a P+ region 14, and a N-type drift region 15 can be turned on under surge current condition, forming a parallel operation mode between the PN junction and the Schottky junction 16, providing device with better surge current capability.

[0043] It is noted that the layout design of the merged PiN Schottky (MPS) diode 10 can be strip cell structure, circle cell structure or polygon cell structure. The one-dimensional strip structure has the drawback that the P+ region occupies too much active area, resulting in insufficient Schottky area for normal current operation, leading to a large forward voltage drop of the device. However, two-dimensional circles will also leads to a large P+ percentage because circular cells cannot form a close-packed layout. Therefore, compared with regular polygon cell structure, the device will also have larger forward voltage drop due to inadequate Schottky area under normal current operation.

[0044] FIG. 2 shows a layout design of a first embodiment, while FIG. 3 is a cross-sectional schematic view of the device structure of the first embodiment along line AA′. As shown in FIG. 3, the width of the regions 14 having the second conductivity type are not uniform, which are denoted as P.sub.1 and P.sub.2, respectively.

[0045] When the MPS diode is under forward bias, the current flows from the anode of the diode through the Schottky junction 16 into the drift region 15, then through the substrate layer 12 and flows out of the cathode electrode 11. Before the current enters the drift region 15, it first passes through the channel region formed between the second conductivity type regions. Meanwhile, the current will form a potential difference on the PN junction, which is formed between the region 14 with second conductivity type and the drift region 15 with first conductivity type. When this potential difference exceeds the built-in potential of the PN junction, the PN junction will be turned on. Changing the width of the second conductivity type region 14 will affect the threshold that triggers the turn-on of the PN junction. Once the PN junction is turned on, the voltage drop between the anode and cathode 11 of the diode is referred to as the PN junction turn-on voltage. The larger the width of the region of the second conductivity type 14, the lower the PN junction turn-on voltage. This is because, as shown in FIG. 4, the dash lines BB′, CC′ respectively show the current paths near the second conductivity type regions with widths P.sub.1 and P.sub.2, respectively. When the potential difference between BB′ and CC′ reaches the built-in potential of the PN junction, the PN junction will be turned on. Here, the potential difference between BB′ and CC′ is equal to the channel current times the resistance along the line BB′ and CC′, separately.

[0046] It can be clearly seen from FIG. 4 that when the P+ region spacing is constant, the resistance of the channel is mainly affected by the width of the P+ region 14. If the width of the P+ region is larger (P.sub.2 is greater than P.sub.1), the resistance is larger (R.sub.CC′ is larger than R.sub.BB′). Therefore, once the current increases to the threshold 12 that triggers the first PN junction as shown in 15B in FIG. 3 (formed by the P+ region with the width P.sub.2), the potential difference between CC′ will reach the built-in potential of the PN junction, and the PN junction will be first turned on. As the current continues increasing, once beyond the threshold Ii at which the second PN junction is turned on, the potential difference between BB′ also reaches the built-in potential of the PN junction as shown in 15A in FIG. 3, formed by the P+ region of width P.sub.1.

[0047] As such, based on the layout design shown in FIG. 2, in a second embodiment, the spacing of P+ regions keeps constant and the circle cell is added as shown in FIG. 5. Here, the second conductivity type region has a wider width (P.sub.3). Because the PN junction with P.sub.3 width (see FIG. 9, structure 55C) has a smaller threshold current I.sub.3 compared to I.sub.2, it can be turned on even earlier, and enhancing the surge current capability of the device.

[0048] The layout designs of FIGS. 5 to 8 can be formed through different arrangements of the circle cells. As shown in FIGS. 5 to 8, each circle cell in the second embodiment can be surrounded by the n layer(s) of the circle cell in the first embodiment, where n can be 1 to 200.

[0049] Through calculation, it is found that compared with regular polygons, P+ regions in circle cell design takes too much active area during the arrangement so the Schottky area ratio is only 50.49%. Thus, an octagon cell structure is proposed here for efficient layout design. It is important to note that in order to achieve close-packed arrangement, a square cell is used to fill the gap between the octagonal cells which is shown in FIG. 10, and FIG. 11 is a cross-section view of the MPS diode with the octagonal cells and square cells along EE′ shown in FIG. 10. It is noted that for the layout design in FIG. 10, the width of second conductivity regions as P.sub.1 and P.sub.2 can still be kept, and the Schottky ratio of the device is increased to 52.98%.

[0050] On the basis of the device design shown in FIG. 10, another octagonal cell is added for a third embodiment, where the second conductivity region has a wider width of P.sub.3. The PN junction with P.sub.3 width (see FIG. 16 structure 155C) has a smaller current threshold I.sub.3 than I.sub.2 of the P.sub.2 wide PN junction, which can be turned on at a lower voltage, thus enhancing the surge current capability of the device.

[0051] Through different arrangements of the octagonal cells in shown FIGS. 10 and 12, the layout designs shown in FIGS. 13 to 15 can be obtained. Similarly, each octagonal cell in FIG. 12 can be surrounded by n layer(s) of the octagonal cells in FIG. 10, where n can be 1 to 200.

[0052] In another aspect, as shown in FIGS. 17A to 17G, and 18, a method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type 210; forming an epitaxial layer with the first conductivity type 220 on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer 230; forming a plasma spreading layer in each region 240; depositing and patterning an Ohmic contact metal on the regions with the second conductivity type 250; depositing a Schottky contact metal on top of the entire epitaxial layer 260; and forming an Ohmic contact metal on a backside of the substrate 270.

[0053] In one embodiment, the epitaxial layer is made of N-type silicon carbide. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer 230 may include steps of depositing and patterning a mask layer 20 on the epitaxial layer 2301, implanting P-type dopant into the epitaxial layer 2302, and removing the mask layer 2303. It is noted that the dopant can be aluminum or boron.

[0054] In a further embodiment, the step of depositing and patterning an Ohmic contact metal on the regions 240 may include a step of annealing the Ohmic metal to enable the metal to be in direct contact with the epitaxial layer. In still a further embodiment, the step of depositing a Schottky contact metal on top of the entire epitaxial layer 250 may include a step of conducting a low temperature annealing of the Schottky contact metal.

[0055] Having described the invention by the description and illustrations above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Accordingly, the invention is not to be considered as limited by the foregoing description, but includes any equivalent.