ULTRA-FAST MAGNETIC RANDOM ACCESS MEMORY HAVING A COMPOSITE SOT-MTJ STRUCTURE

Abstract

An ultra-fast magnetic random access memory (MRAM) comprises a three terminal composite SOT magnetic tunneling junction (CSOT-MTJ) element including a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such MRAM-SE will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

Claims

1. A composite SOT magnetic tunneling junction (CSOT-MTJ) element comprises a composite SOT (CSOT) stack provided on the top surface of a CMOS substrate and having at least a magnetic flux guiding (MFG) layer and a spin Hall channel (SHC) layer provided on the top surface of said MFG; a magnetic memory (MM) layer provided on the top surface of said CSOT stack and having magnetic anisotropy in a film plane and having a variable magnetization direction; a tunnel barrier (TB) layer provided on the top surface of said MM layer; a magnetic pinning stack (MPS) provided on the top surface of said TB layer having magnetic anisotropy in a film plane and having an invariable magnetization direction; a cap layer provided on the top surface of said MPS as top electrode (TE).

2. The element of claim 1, wherein said MFG layer is made of a soft magnetic material having a very high magnetic permeability and comprising at least one element selected from the group of Ni, Fe, Co, and preferred to be selected from the group of NiFe, CoFe, NiCo and CoNiFe, or the group of NiFe, CoFe, NiCo and CoNiFe doped with 0-30% of B, Si, Mo, Cr, Nb, Ta, Hf and having a thickness between 1.5-10 nm.

3. The element of claim 1, wherein said SHC is made of a material having a large positive spin Hall angle, preferred to comprise (Au, Pt, Ir, Ag, Pd or Cu) doped with 5-15% (Ta, W, Hf or Bi), and having an electric resistivity lower than the electric resistivity of said MFG and having a thickness between 1.5-10 nm.

4. The element of claim 1, wherein said MM is made of a soft magnetic single layer or multilayer having a magnetic anisotropy in a direction in the film surface and having a variable magnetization direction; and comprising a material selected from CoFeB, FeB, Fe/CoFeB with a total thickness between 1.5-5 nm or a multilayer CoFeB(0.5-2 nm)/(W or Mo)(0.2-0.6 nm)/CoFeB (1-3 nm).

5. The element of claim 1, wherein said TB is made of an oxide MgO or MgZnO with a thickness between 0.7-2 nm.

6. The element of claim 1, wherein said MPS is a multilayer stack having magnetic anisotropy in a film plane and having an invariable magnetization direction and comprising a magnetic reference layer CoFeB/Co, FeB/Co, CoFeB/CoFe or FeB/CoFe, a RKKY coupling layer Ru, Rh or Ir, a pinned layer Co or CoFe and an antiferromagnetic material layer selected from PtMn, PtPdMn, NiMn, IrMn, RhMn, RuMn; and a preferred MPS is CoFeB(1-2 nm)/CoFe(1-1.5 nm)/Ru(0.4-0.85 nm)/CoFe(2-5 nm)/PtMn(5-20 nm).

7. The element of claim 1, wherein said cap layer contains a material selected from Ta, Wu or Ru/Ta, Ru/W with a thickness between 30-100 nm.

8. The element of claim 1, wherein said CSOT-MTJ element contains a three-terminal electric circuit after connecting with a first bottom electrode (BE1) provided on a first side of said CSOT stack; a second bottom electrode (BE2) provided on a second side of said CSOT stack; a bit line provided on the top surface of the cap layer (also TE).

9. The element of claim 8, wherein said three terminal memory device is connected to at least one CMOS transistor coupled through one of the bottom electrodes (BE1) or BE2) and further provided circuitry connected to the bit line through top electrode (TE).

10. The element of claim 1, wherein writing of a low resistance (parallel) state in said MM is done by passing through a spin current flowing from BE1 to BE2, and a high resistance (anti-parallel) state in said MM layer is done by passing a spin current flowing from BE2 to BE1 while leaving the TE open.

11. The element of claim 10, wherein writing of both low (parallel) resistance state and high (anti-parallel) resistance state in said MM is done by a spin orbit torque (SOT) and a Lorentz force generated by current-flowing-wire (CFW) in said SHC layer at both MFG/SHC and SHC/MM interfaces, and further enhanced by a close magnetic flux loop at the cross-section between said MFG/SHC/MM tri-layer.

12. The element of claim 1, wherein writing of a low (parallel) resistance state in said MM is done by passing through a spin current flowing from BE1 to BE2, and a current flowing from said TE down through the entire MTJ film stack to BE2 simultaneously, and a high resistance (anti-parallel) state in said MM layer is done by passing a spin current from BE2 to BE1 and spin current flowing from BE2 up through the entire MTJ stack to TE simultaneously.

13. The element of claim 12, wherein writing of low resistance state and high resistance state in said MM is done by three forces: SOT and Lorentz force generated by current-flow-wire (CFW) in said SHC layer at both MFG/SHC and SHC/MM interfaces, and STT generated by a current vertically flow through the MTJ stack, and further enhanced by a close magnetic flux loop at the cross-section between said MFG/SHC/MM tri-layer.

14. The element of claim 1, wherein reading of magnetic state in said MM layer is done by passing through a current flowing from top electrode down through the entire MTJ stack to BE2 while leaving the transistor connecting with BE1 open, wherein control of current flow is done either by a transistor or diode connecting to said top electrode.

15. The element of claim 1, wherein said CSOT-MTJ element will have a fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

16. A method of manufacturing a composite SOT magnetic tunneling junction (CSOT-MTJ) element comprising: deposit a magnetic flux guiding (MFG) layer on the top surface of a CMOS substrate; deposit a spin Hall channel (SHC) layer on the top surface of said MFG; deposit a magnetic memory (MM) layer on the top surface of said SHC and having magnetic anisotropy in a film plane and having a variable magnetization direction; deposit a tunnel barrier (TB) layer on the top surface of said MM layer; deposit a magnetic pinning stack (MPS) on the top surface of said TB layer having magnetic anisotropy in a film plane and having an invariable magnetization direction; deposit a cap layer on the top surface of said MPS as top electrode (TE); wherein, said CSOT-MTJ element is annealed at a temperature between 350-400 C for 30-150 min in the presence of an in-plane magnetic field with a strength between 1-5Tesla aligning (canted) at an angle α ranging between 10 to 90 degree in the X-Y plane, said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

17. The element of claim 16, wherein said CSOT-MTJ element is photo-lithographically patterned into an oval shape with an aspect ratio of 1.5-3 for its long(easy)/short(hard) (a/b) axes, and with its long a (magnetic easy) axis pointing (canted) at an angle α ranging between 10 to 90 degree in the X-Y plane, said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

18. The element of claim 16, wherein said patterned CSOT-MTJ element is first etched down to the top surface of said SHC to form magnetic recording bits, and second patterned and etched through SHC and MFG to form a current flow channel underneath said MM layer.

19. The element of claim 16, wherein patterned CSOT-MTJ element is first etched down to the MgO barrier layer and the etch-exposed surface of said MM layer is subsequently oxidized to convert it into a non-magnetic insulating layer, and a second patterning and etching through SHC and MFG form a current flow channel underneath said MM layer.

20. The element of claim 16, wherein the tri-layer stripe of MFG/SHC/MM after etching form a close magnetic flux loop which significantly reduces magnetic impedance for said MM layer during switching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 Typical CSOT-MTJ film structure for the current invention.

[0013] FIG. 2 Canted magnetic annealing to preset the pinning direction for the MTJ stack at an angle α in X-Y plane.

[0014] FIG. 3 Patterning of said CSOT-MTJ element with an oval shape to preset its long axis aligning at an angle α in X-Y plane.

[0015] FIG. 4(A,B) Cross section view of a patterned CSOT-MTJ element, A: etch-stopped at the top surface of said SHC layer, B: etch-stopped at MgO tunnel barrier layer followed by oxidization of the exposed portion of memory layer.

[0016] FIG. 5(A, B) Illustration of magnetic flux for the memory layer, A: with a MFG layer underneath the SHC, the magnetic flux forms a close loop, B: without a MFG layer, magnetic flux outside the memory layer is diverging.

[0017] FIG. 6(A,B,C) Illustration of magnetic memory writing when a current passing through the SHC, A: a positive current flow writes the memory layer to a low magnetoresistance state, B: an opposite current flow writes the memory layer to a high magnetoresistance state, C: showing the two forces (SOT, CFW) simultaneously acting on the memory layer for a positive current flow.

[0018] FIG. 7(A, B) A:Illustration of magnetic memory writing with one current laterally flowing through the SHC and another current perpendicularly flowing down from the MTJ stack to write a low magnetoresistance state, B: showing three forces simultaneously acting on the memory layer to switch its magnetic state.

[0019] FIG. 8(A,B) Current flow from top electrode (TE) through the MTJ to BE2 during memory reading, A: a transistor is used for control, B: a diode is used.

DETAILED DESCRIPTION OF THE INVENTION

[0020] The disclosed composite SOT magnetic tunneling junction (CSOT-MTJ) element comprises a film stack 100 (see FIG. 1), starting from a magnetic flux guiding (MFG) layer 10 deposited on a CMOS substrate, followed by a spin Hall channel (SHC) 11, a magnetic memory (MM) layer 12 having magnetic anisotropy in a direction in said film surface and having a variable magnetization direction, a tunnel barrier (TB) layer 13, a magnetic pinning stack (MPS) 20 having magnetic anisotropy in a film plane and having an invariable magnetization direction, and a cap (also as a hard mask) layer 17.

[0021] In above mentioned CSOT-MTJ element, said MFG layer 10 is made of a soft magnetic material having a very high magnetic permeability and comprising at least one element selected from the group of Ni, Fe, Co, and preferred to be selected from the group of NiFe, CoFe, NiCo and CoNiFe, or the group of NiFe, CoFe, Co, NiCo and CoNiFe doped with 0-30% of B, Si, Mo, Cr, Nb, Ta, Hf and having a thickness between 1.5-10 nm. The MFG layer 10 and the SHC layer 11 together are patterned into a rectangular shape with two longitudinal ends connected to its bottom electrodes. The magnetization of the MFG layer is normally aligned along either one of its two longitudinal directions of the MFG layer. Purposes of this MFG layer are to enhance the SOT effect for an easier switch as well as help the MM layer 12 form a magnetic flux closure, instead of magnetic dipole field diverging, for better thermal stability and less magnetic stray field acting on neighbor elements.

[0022] Above said spin Hall channel (SHC) 11 is made of a material having a large positive spin Hall angle, preferred to be selected from the group of (Au, Pt, Ir, Ag, Pd or Cu) doped with 5-15% (Ta, W, Hf or Bi), and having an electric resistivity lower than the electric resistivity of said MFG and having a thickness between 1.5-10 nm. For example, the resistivity of a SHC layer made of Au doped with 10% Ta is readily under 85 μOhm.cm which smaller than the resistivity of CoNbHf thin film layer (125 μOhm.cm). Although beta phase Ta and W have a negative large spin Hall angle, the negative spin torque generated will be counter-balanced partially by a Lorentz force generated by the current-flowing wire (CFW) in the SHC layer which will provide a weaker spin torque for memory layer switch. As an electrical current flows along the CSOT stack from one electrode to the other electrode, the majority current flows inside the SHC layer due to its lower resistivity. Due to the SHE, opposite polarized spin accumulations occur at the two surfaces of the SHC layer depending upon the electrically current direction. More specifically, accumulated polarized spins near its bottom interface are parallel to the width direction, while accumulated polarized spins near its top interface are anti-parallel to above width direction. Since the magnetization in the MFG layer is in-plane and aligned its longitudinal direction, the accumulated polarized spins near SHC bottom interface flow or diffuse into the MFG layer and cause the magnetization in the MFG layer rotate away from its original longitudinal direction; while the accumulated polarized spins near SHC top interface is enhanced in the spin density and flow or diffuse into the MM layer and cause the magnetization in the MM layer switch to an opposite direction. Therefore, the critical writing current, as well as writing power, is reduced.

[0023] Above said magnetic memory (MM) layer 12 is made of a soft magnetic single layer or multilayer having a magnetic anisotropy in a direction in the film surface and having a variable magnetization direction; and comprising a material selected from CoFeB, FeB, Fe/CoFeB with a total thickness between 1.5-5 nm or a multilayer CoFeB(0.5-2 nm)/(W or Mo)(0.2-0.6 nm)/CoFeB(1-3nm).The magnetization of MM layer is also magnetically coupled with the magnetization of the MFG layer, yielding an additional in-plane magnetic anisotropy along its width directions.

[0024] Above said tunnel barrier (TB) layer 13 is made of an oxide selected from MgO or MgZnO with a thickness between 1-2 nm. As compared with the MTJ stack used in pSTT-MTAM, in this MTJ stack, a thicker TB can be used to ensure a good device reliability because the write current does not go through the MTJ stack.

[0025] Above said magnetic pinning stack (MPS) 20 is a multilayer stack having magnetic anisotropy in a film plane and having an invariable magnetization direction and comprising a magnetic reference layer CoFeB/Co, FeB/Co, CoFeB/CoFe or FeB/CoFe, a RKKY coupling layer Ru, Rh or Ir, a pinned layer Co or CoFe and an antiferromagnetic material layer selected from PtMn, PtPdMn, NiMn, IrMn, RhMn, RuMn; and a preferred MPS is CoFeB(1-2 nm)/CoFe(1-1.5 nm)/Ru(0.4-0.85 nm)/CoFe(2-5 nm)/PtMn(5-20 nm).

[0026] There is also a cap layer (not shown in the figures) on top of the MPS 20 containing materials selected from Ta, Wu or Ru/Ta, Ru/W with a thickness between 30-100 nm, and the cap layer is also act as a hard mask for etching or milling during device patterning.

[0027] After film deposition, the above said CSOT-MTJ stack is annealed at a high temperature between 350-400 C for 30-120 minutes in the presence of a high magnetic field Han (1-5Tesla) to preset an initial aligning direction for the entire film stack. The field direction can be canted at an angle α (10-90degree) within the X-Y plane (see FIG. 2) which is needed to avoid using an external magnetic field during memory switching.

[0028] The wafer with a CSOT-MTJ film stack is then photo-lithographically patterned and subsequently etched. To avoid using an external magnetic field during memory switching, the shape of the memory cell can also be made elliptical with an aspect ratio of 1.5-3 for its long(easy)/short(hard) (a/b) axes, and with its long a (magnetic easy) axis pointing (canted) at an angle α ranging between 10 to 90 degree in the X-Y plane (see FIG. 3), said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

[0029] There are two etching options: In the first one (see cross section stack 200 in FIG. 4A), etch is stopped at top surface of the SHC layer then immediately deposit a SiN protection layer (not shown in the figure) to cover the exposed MTJ surface and subsequently refill with SiO2 (18). In the second option (see stack cross section 250 in FIG. 4B): etch is stopped at MgO tunnel barrier layer followed by an oxidization process to convert the exposed portion of the memory layer into non-magnetic insulation layer (12-1). The underneath SHC layer is not affected since it contains Au which is inert to oxidation. Our preferred etching process is option two which yields a better current flow condition especially for thin SHC layer. After SiO2 refill, a CMP process is used to flatten the film surface and remove excess SiO2, followed by a Cu damascene process to form a top electrode 19.

[0030] In FIGS. 4A and 4B, the two magnetic layers 14 (reference) and 16 (pinned) have their magnetic moment aligned in antiparallel across the Ru RKKY coupling layer 15, and the MM 12 is in a parallel state with the reference layer 14 resulting a low magnetoresistance state. The MFG layer 10 across the SHC layer 11, due to its magnetic softness and extremely high permeability, is always trying to align with the MM layer 12 to form a close-loop (see FIG. 5A) to help magnetic switching during memory writing. Without such a MFG layer, the magnetic flux outside the MM layer is diverging (see FIG. 5B) which will make it difficult to switch. And most importantly, with such a magnetic close loop, both the spin orbit torque and Lorentz force generated at upper SHC/MM interface and lower SHC/MFG interface will participate in the switching of the MM layer, more than twice magnitude of torque compared with the ones generated at the upper SHC/MM interface only.

[0031] In FIG. 6A illustrate magnetic switching in a CSOT-MTJ stack 300 when a current is flowing through the SHC layer from BE1 (21) to BE2 (22) to write the MM layer 12 a low magnetoresistance (parallel with 14) state, while FIG. 6B is for an opposite case with a current flowing from BE2 to BE1 to write the MM layer 12 a high magnetoresistance (anti-parallel with 14) state. As shown in FIG. 6C, when a current flowing from BE1 to BE2 in the SHC layer (FIG. 6A), there are 2×SOT and two current flow wire (CFW) generated Lorentz forces (2×CFW) acting on the MM layer 12 to switch its magnetic moment to a parallel state with the reference layer 14. With a small magnetic impedance in the closed magnetic loop as shown in FIG. 5A, magnetic polarization of the MM layer can be easily rotated to its final parallel state. Similarly with an opposite current flow in the SHC layer, the magnetic polarization of the MM will be switched to antiparallel state with the reference layer (see FIG. 6B).

[0032] The magnetic switching of MM layer can be further enhanced by simultaneously passing through a current from top electrode (19) to BE2 (see FIG. 7A) 22 utilizing a spin transfer torque (STT) generated by the MTJ stack. Under such a write operation, there are 2SOT+2CFW+STT forces magnetically acting on the MM layer (see FIG. 7B) which make the switching even easier and faster.

[0033] As for read operation, a current will pass through the MTJ stack from top electrode (19) down to BE2 (22). For the control of current flow, either a transistor (FIG. 8A) or diode (FIG. 8B) can be used for such operation. From the point of device miniaturization and cost of manufacturing, using a diode is more economic, thus only on transistor one diode (1T1D) is needed for each MRAM-SE unit.

[0034] While certain embodiments have been described above, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.