Method of generating self-test signals, corresponding circuit and apparatus

Abstract

A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

Claims

1. A method, comprising: applying frequency division to a local oscillator signal of a radio-frequency receiver, producing a frequency-divided signal; and generating a self-test signal of the radio-frequency receiver using a phase-locked loop (PLL) circuit having an output oscillator, an input comparator, and a loop divider, wherein the loop divider is coupled between the output oscillator and the input comparator, with an input of the loop divider coupled to an output of the output oscillator and an output of the loop divider coupled to a first input of the input comparator, the generating of the self-test signal of the radio-frequency receiver including: generating the self-test signal based on the frequency-divided signal; and monitoring generation of the self-test signal using the frequency-divided signal; supplying the frequency-divided signal to a second input of the input comparator of the PLL circuit; and selectively varying a division factor of said loop divider, varying a frequency of said self-test signal.

2. The method of claim 1, comprising delaying the frequency-divided signal supplied to the second input of the input comparator.

3. A circuit, comprising: a first frequency divider, which, in operation, frequency divides a first oscillation signal, generating a first frequency-divided signal; and self-test signal generation circuitry that includes a phase-locked loop (PLL) having an output oscillator, an input comparator, and a loop divider, wherein the loop divider is coupled between the output oscillator and the input comparator, with an output of the output oscillator coupled to an input of the loop divider and an output of the loop divider coupled to a first input of the input comparator, wherein a second input of the input comparator is coupled to an output of the first frequency divider and wherein the self-test signal generation circuitry, in operation, generates a receiver self-test signal, the generating of the receiver self-test signal including: generating the self-test signal based on the first frequency-divided signal; and monitoring generation of the self-test signal using the first frequency-divided signal, wherein a division factor of the loop divider is adjustable and, in operation, varying the division factor of the loop divider varies a frequency of the self-test signal.

4. The circuit of claim 3, comprising a delay circuit coupled between the output of the first frequency divider and the second input of the input comparator of the PLL.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

(2) FIG. 1 is an exemplary block diagram of a radar sensor, e.g., for automotive use;

(3) FIG. 2, including two portions designated 2A and 2B, respectively, is exemplary of possible time behaviors of certain signals in a block diagram as exemplified in FIG. 1;

(4) FIG. 3 is a block diagram exemplary of one or more embodiments;

(5) FIG. 4 is a block diagram exemplary of one or more embodiments; and

(6) FIGS. 5 and 6 are exemplary of various circuit arrangements according to embodiments.

DETAILED DESCRIPTION

(7) In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

(8) Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(9) The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

(10) A BIST circuit architecture may include an I/Q image rejection mixer. This architecture may be notionally able to generate a SSB (Single-Side Band) signal with characteristics adapted for the calibration of radar sensor IC. In such an arrangement image signal rejection is proportional to I/Q phase and amplitude accuracy.

(11) For high-frequency ICs, the conventional generation of I and Q signals is complex and generally not accurate enough for an image rejection architecture.

(12) This technical drawback limits the use of loop-back solutions for, e.g., high-frequency applications such as radar applications. A calibration procedure may improve radar sensor performance. An approach in that respect may involve measuring calibration data, e.g., using well-known RF test signals and modulation schemes and storing them in the sensor at one temperature, for instance during an end-of-line test. During sensor operation, the calibration data may be used by target detection algorithms for compensating, e.g., silicon IC process variations. Achieving good performance of a sensor can be facilitated by IC performance being as much stable as possible versus, e.g., frequency, temperature, and aging. Run-time procedures for updating calibration data may thus be helpful.

(13) FIG. 1 shows a (simplified) exemplary block diagram of a radar sensor (e.g., including a radar sensor IC) 10 by referring to the exemplary case of an, e.g., FMCW radar sensor 10 capable of detecting an object O at a distance (range) d.

(14) Such a sensor may include a RF frequency synthesizer 12 generating a local oscillator signal TX/LO fed to a (transmitter) variable gain amplifier (VGA) 14. The VGA may in turn feed a power amplifier (PA) 16 driving a transmission (TX) antenna 20.

(15) A corresponding incoming (echo) signal received at a receiver (RX) antenna 22 may be fed via a RF coupler circuit 24 to a low noise amplifier (LNA) 26 and on to a mixer circuit 28 fed with the local oscillator signal TX/LO to produce a down-converted intermediate frequency (IF) signal, which in turn is fed to a (receiver) variable gain amplifier (VGA) 30.

(16) A RF Built-In-Self-Test (BIST) block 32 may generate a RF test signal (with known characteristics) which may be fed to the high frequency stage 24 to reproduce (simulate) an echo radar signal.

(17) Such a signal may have, e.g., the following characteristics: Single-Side Band (SSB) signal frequency modulation coherence with local oscillator (TX/LO) signal variable frequency injection at the input of the receiver (e.g., RF coupler stage 24).

(18) Calibration procedures applied to a circuit layout as exemplified in FIG. 1 may be able to fix both systematic and random errors as revealed by a RF test signal. Such RF test signals may thus be useful in radar sensor (e.g., radar sensor IC) auto-diagnostics and calibration procedures, e.g., with respect to hardware fault and performance improvement.

(19) For instance, a RF test signal from the BIST block 32 in FIG. 1 may be used to simulate an echo signal from the radar sensor IC as depicted in FIG. 2: e.g., during radar sensor calibration, IC malfunction leading to unwanted spurious Doppler shifts (and thus spurious range shifts) may be detected, e.g., by analyzing the FFT of the base band IF signal generated (e.g., at 28 in FIG. 1) by injecting at the receiver input (e.g., at RF coupler 24) the (known) RF test signal RF.sub.TEST.

(20) The diagrams in part 2A of FIG. 2 are exemplary of a possible behavior over time (abscissa scale) of the frequency (ordinate scale) of transmitted and received signals TX and RX varying with a (modulation) bandwidth BW over a time Ts with a Doppler shift DS and a range shift RS.

(21) The diagram in part 2B of FIG. 2 is exemplary of a possible time behavior of a corresponding IF signal with a frequency f.sub.IF=|f.sub.RX−f.sub.TX|.

(22) In one or more embodiments, a RF test signal may be generated by resorting to the BIST architectures exemplified in FIG. 3 or FIG. 4.

(23) In both FIGS. 3 and 4, the left-hand dashed area is exemplary of a frequency generator 120 (e.g., for a radar sensor IC).

(24) In one or more embodiments, a simple implementation of such a generator 120 may include a voltage-controlled oscillator (VCO) 122 (see the frequency synthesizer/generator 12 in FIG. 1) and a frequency divider (:N) 124 acting on the output from the oscillator 122 to produce a frequency-divided signal f.sub.DIV.

(25) In one or more embodiments, the oscillation frequency of the output signal of the oscillator 122 (which may correspond to the signal TX/LO of the diagram of FIG. 1) may be controlled using a tuning signal (e.g., a voltage signal V.sub.FINE, e.g., from a modulator 122a).

(26) In one or more embodiments, the frequency of the output signal of the oscillator 122 may controlled by “finely tuning” with the signal V.sub.FINE from the modulator 122a a coarser signal V.sub.COARSE as derived e.g. from a digital-to-analog converter (DAC) 122b.

(27) In one or embodiments, the modulator 122a and the DAC 122b may be external elements to an IC as exemplified herein.

(28) In one or more embodiments a radar sensor (micro) controller circuit MC may control various components/parts of, e.g., a radar sensor IC as exemplified in the figures. In order to avoid making the graphical representation unnecessarily complex, the possible control action of the controller MC is represented in the figures as an arrow pointing into a certain component/part. For instance, the controller MC may detect (measure) the oscillation frequency from the output of the frequency divider 124 during a calibration time and produce a desired modulation scheme—e.g., chirps—as in the radar output signal.

(29) In one or more embodiments, a frequency generator 120 as exemplified herein may include additional/more complex circuits, such as, e.g.: integrated modulator(s); an integrated DAC, e.g., to reduce the VFINE voltage sensitivity; a fully integrated N-fractional or N-integer PLL (see below).

(30) Operation of one or more embodiments may include the above possible implementation details and may, for example, employ on two signals: a local oscillator signal TX/LO which may be transmitted using the power amplifier chain (see, e.g., blocks 14 and 16 in FIG. 1) and distributed for down-conversion to IF (see, e.g., the mixer 28 of FIG. 1); a frequency-divided signal f.sub.DIV as available, e.g., at the output of the divider 124.

(31) In one or more embodiments as exemplified in FIG. 3, the frequency-divided signal f.sub.DIV may be used for monitoring a RF test signal generated by a (further) fine-tuned oscillator.

(32) In one or more embodiments as exemplified in FIG. 4, the frequency-divided signal f.sub.DIV may be used for driving a PLL circuit including an oscillator which generates the RF test signal.

(33) One or more embodiments may thus involve: applying frequency division (e.g., at 124) to a local oscillator signal (e.g., TX/LO) to produce a frequency-divided signal (e.g., f.sub.DIV), providing a signal generator for generating a self-test signal RF.sub.TEST, and generating the self-test signal RF.sub.TEST by operating a signal generator (222 in FIGS. 3-320a in FIG. 4) with operation of said generator monitored (FIG. 3) or controlled (FIG. 4) with the frequency-divided signal.

(34) Stated otherwise, in more embodiments, generating the self-test signal RF.sub.TEST may involve monitoring or controlling operation of a corresponding generator based on the frequency-divided signal.

(35) FIG. 3 shows an exemplary open-loop architecture of a RF test signal generator 32 according to one or more embodiments, wherein the frequency-divided signal f.sub.DIV at the output of the divider 124 is used to monitor a RF test signal generated by oscillator 222.

(36) In one or more embodiments as exemplified in FIG. 3, the IF output signal intended to simulate target detection may be obtained by setting a frequency shift between the RF test signal RF.sub.TEST and the TX/LO signal by using DACs on tuning voltages.

(37) In one or more embodiments as exemplified in FIG. 3, the first DAC 122b may provide a coarse tuning voltage V.sub.COARSE both to the oscillator 122 (fine tuned by means V.sub.FINE from the modulator 122a to provide the local oscillator signal TX/LO) and another oscillator (e.g., VCO) 222, fine tuned via a further DAC 222a.

(38) Both oscillators 122 and 222 being (digitally) controlled by using a common DAC, that is 122b, may facilitate compensating oscillation frequency drifts due to temperature and silicon process variations.

(39) In one or more embodiments, respective frequency dividers 124, 224 (e.g., by a same factor N) may be coupled to the outputs of the oscillators 122, 222 with the frequency-divided outputs f.sub.DIV, f.sub.DIV_AUX from the dividers 124, 224 fed to a frequency counter 226 (clocked by a clock signal f.sub.CLK) which provides a test flag signal over a line 226a to the microcontroller MC.

(40) In one or more embodiments, such a test flag may be generated—during a calibration phase—when both oscillators 122, 222 are oscillating at expected frequencies due to the microcontroller MC controlling the fine tuning voltage V.sub.FINE_AUX of the (auxiliary) oscillator 222 via the DAC 222a while the fine tuning voltage V.sub.FINE of the (main) oscillator 122 may be managed by the microcontroller MC, e.g., via the modulator 122a.

(41) In one or more embodiments, operation of the frequency counter 226 may involve comparing the frequencies of the frequency-divided f.sub.DIV and f.sub.DIV_AUX and determining that the oscillators 122, 222 are oscillating at expected frequencies when, e.g., the ratio of the frequencies of f.sub.DIV and f.sub.DIV_AUX reaches a certain value: in that respect it will be appreciated that f.sub.DIV and f.sub.DIV_AUX may be generated by oscillators 122, 222 oscillating at respective frequencies such as f.sub.osc and f.sub.osc+f.sub.IF and/or that the dividers 124, 224 need not necessarily have identical division factors (e.g., N).

(42) In one or more embodiments, the oscillator 222 may be coupled to a variable gain amplifier (VGA) 228 to provide the RF test signal RF.sub.TEST with a level (possibly monitored with a power detector 228a) adapted to be fed to the stage 24 (see FIG. 1).

(43) One or more embodiments as exemplified in FIG. 3 may thus exhibit one or more of the following features: the RF test signal RF.sub.TEST may be generated using an auxiliary oscillator, e.g., a VCO (222); the frequency shift between the RF test signal RF.sub.TEST and the TX/LO signal may be properly set using, e.g., DACs on the VCO tuning voltages; a coarse tuning voltage of both VCOs 122 and 222 may be digitally controlled using a common DAC (122b) to compensate the oscillation frequency drift due to both silicon process and temperature variations; the fine tuning voltage V.sub.FINE_AUX of the auxiliary oscillator 222 may be digitally controlled by an additional DAC 222a while the fine tuning voltage of oscillator 122 may be managed by the microcontroller MC during the calibration phase, e.g., via the block 122a; the RF test signal RF.sub.TEST may be a continuous wave (CW) signal with its frequency f.sub.RX generated according to the following equation: f.sub.RX=f.sub.TX/LO+f.sub.IF where f.sub.TX/LO and f.sub.IF are the frequencies of the local oscillator signal TX/LO and the intermediate frequency signal IF, respectively; the difference between the oscillation frequencies of the oscillator 122 and the oscillator 222 may set the frequency f.sub.IF of the IF signal; the microcontroller MC may set the desired IF frequency by changing the fine tuning voltages of the oscillators 122, 222 through the associated (integrated) DACs; the accuracy in setting the IF frequency may be a function of the resolution used in controlling the fine tuning voltages V.sub.FINE, V.sub.FINE_AUX of the oscillators 122, 222; these fine tuning voltages may be modified by the microcontroller MC until the desired IF frequency is set with an expected accuracy and the test flag signal issued by the counter 226 on the line 226a becomes true; the generated RF test signal RF.sub.TEST may be a replica of the transmitted signal adapted to be injected to the receiver input (e.g., at 24 in FIG. 1) reproducing the echo radar signal; the RF test signal RF.sub.TEST down-converted with the TX/LO signal may generate an IF output signal, which may reproduce target detection; programmable frequency dividers (e.g., by a same factor N) may be used at 124, 224 to generate the frequency-divided signals f.sub.DIV and f.sub.DIV_AUX; it will be appreciated that these signals may not be identical insofar as they are generated by oscillators 122, 222 oscillating at respective frequencies such as f.sub.osc and f.sub.osc+f.sub.IF; the frequency-divided signals f.sub.DIV and f.sub.DIV_AUX may be used by a frequency counter such as 226 to provide a test flag signal (true/false signal) on a line 226a, e.g., to the microcontroller MC when both oscillators 122, 222 are oscillating at desired frequencies with the expected accuracy; the power level of RF test signal RF.sub.TEST may be set using a variable gain amplifier (VGA), e.g., 228 which may be detected using a power detector circuit, e.g., 228a; both the test flag signal on line 226a and the power detector circuit 228a may facilitate making the circuit compliant with ISO26262 standard; the BIST circuit 32 may be disabled during the normal operation.

(44) FIG. 4 shows an exemplary PLL-based architecture of a RF test signal generator 32 according to one or more embodiments.

(45) In one of more embodiments a RF test signal generator 32, intended to provide a RF test signal to be applied, e.g., to the stage 24 of FIG. 1, may include a PLL (Phase Locked Loop) circuit 320, operating, e.g., by “locking” an auxiliary, e.g., voltage-controlled oscillator (VCO) 320a using as an input the frequency divided signal f.sub.DIV from the divider 124, possibly delayed by a (controllable) delay 322 to produce a delayed version of f.sub.DIV namely f.sub.REF.

(46) According to an otherwise conventional PLL layout, the circuit 320 may include, in addition to the oscillator 320a, an input comparator 320b which receives f.sub.REF and the frequency from the oscillator 320a via a PLL divider 320c. The result of the (frequency) comparison in the input comparator 320b drives the oscillator 320a via a loop filter 320d.

(47) The PLL 320 having reached a lock condition may be detected by a lock detector 326 which may issue over a line 326a a test flag to the microcontroller MC, thus making the IC arrangement exemplified herein compliant with, e.g., the ISO26262 standard.

(48) In one or more embodiments, the oscillator 320a in the PLL 320 may be followed by a variable gain amplifier (VGA) 328 to provide the receiver with a RF test signal having a level (possibly monitored with a power detector 328a) adapted to be fed to the stage 24 (see FIG. 1).

(49) In one or more embodiments, the PLL divider 320c may permit to change the RF test signal frequency, e.g., by programming the PLL frequency divider 320c.

(50) The frequency shift between the RF test signal and the local oscillator signal TX/LO may generate an IF output signal (e.g., at the output of the mixer stage 28 of FIG. 1), which simulates target detection (see, e.g., FIG. 2).

(51) In one or more embodiments, the amplitude, frequency and phase of IF output signal may be exploited (in a manner known per se) for calibration of the radar sensor (e.g., of the radar sensor IC).

(52) In one or more embodiments, the delay possibly applied (e.g., at 322) to the divided signal f.sub.DIV to produce f.sub.REF may permit to obtain a well-defined delay time between the RF test signal and the TX/LO signal.

(53) In one or more embodiments, the PLL circuit 320 may follow the frequency modulation applied to the transmitted signal.

(54) In one or more embodiments, the two oscillators (e.g., VCOs) 122 and 320a may be designed to oscillate at different frequencies to reduce any “pulling” effect (e.g., the VCO 122 may include a core oscillating at half the operating frequency and followed by a frequency doubler while the VCO 320a may be include a core oscillating at the operating frequency, or vice versa).

(55) In one or more embodiments, the RF test signal sent to the stage 24 may be coherent with the TX/LO signal, which may facilitate simulating the transmitted signal, e.g., with the generated RF test signal exhibiting essentially the same characteristics of radar echo signal.

(56) In one or more embodiments, the BIST circuit including the PLL block 320 may be disabled (e.g., by the controller MC) during normal operation of the radar sensor.

(57) One or more embodiments as exemplified in FIG. 4 may thus exhibit one or more of the following features: generation of a RF test signal RF.sub.TEST; during a self-test or calibration procedure the microcontroller MC may act (e.g., on the PLL divider 320c) to provide a desired IF frequency difference between the two oscillators (122, 320a) to generate a frequency chirp (see, e.g., the TX signal in portion 2A of FIG. 2); the frequency generator 120 may provide the TX/LO signal to the transmitter chain and the receiver down-converter (see, e.g., 14, 16 and 28 in FIG. 1) as well as (e.g., via the divider 124) the frequency-divided signal f.sub.DIV to the BIST circuit 32; the frequency-divided signal f.sub.DIV may be processed by a programmable digital delay circuit 322 to generate a well-defined delay time (see, e.g., the range shift effect in portion 2A of FIG. 2) between the RF test signal and the TX/LO signal; the PLL circuit 320 may lock the auxiliary oscillator 320a using a signal f.sub.REF which is a delayed replica of the frequency-divided signal f.sub.DIV; the PLL circuit 320 may follow the frequency modulation applied to the TX/LO signal; the frequency shift between the RF test signal RF.sub.TEST and the TX/LO signal (see, e.g., the Doppler effect in portion 2A of FIG. 2) may be programmed via the PLL frequency divider 320c; the RF test signal RF.sub.TEST may be made coherent with TX/LO signal, which facilitates simulating the transmitted signal; the amplitude, frequency and phase of the IF output signal may be rendered accurate, thus facilitating radar sensor calibration; the oscillators 122 and 320a may be designed to oscillate at different frequencies to reduce the pulling effect.

(58) As in the case of one or more embodiments as exemplified in FIG. 3, one or more embodiments as exemplified in FIG. 4 may exhibit one or more of the following features: the lock detector 326 may to provide a test flag signal (true/false signal) on a line 326a, e.g., to the microcontroller MC when the PLL circuit 320 is in a locked condition; the power level of RF test signal RF.sub.TEST may be set using a variable gain amplifier (VGA), e.g., 328, and the power level may be detected using a power detector circuit, e.g., 328a; both the test flag signal on line 326a and the power detector circuit 328a may facilitate making the circuit compliant with ISO26262 standard; the BIST circuit 32 may be disabled during normal operation.

(59) In one or more embodiments of the BIST circuit 32 as discussed herein the resulting RF test signal RF.sub.TEST may have the same characteristics of echo radar signal shown.

(60) In one or more embodiments, feeding of the RF test signal may facilitate operation of various arrangements as exemplified herein.

(61) Possible arrangements of various blocks as represented in FIG. 1 are exemplified in FIGS. 5 and 6, where MMIC and PCB are schematically indicative of a Microwave/Millimeter-wave Monolithic Integrated Circuit and a Printed Circuit Board to mount the MMIC.

(62) The use of hybrid coupler, balun, microstrip and inductor between the output of the RF test signal generator 32 and the receiver inputs was found to influence the receiver performance.

(63) One or more embodiments may thus exploit leakage between the RF test signal coming from the output of the VGA (228 in FIG. 3, 328 in FIG. 4) and the input(s) of the receiver 26, e.g., by using external, PCB-hosted coupling as shown in FIG. 5 or MMIC-internal coupling as shown in FIG. 6.

(64) It will again be appreciated that reference to a radar sensor throughout this description is merely exemplary of a possible area of application of one or more embodiments. One or more embodiments may in fact find a wide variety of applications, e.g., as exemplified in the introductory portion of this description.

(65) One or more embodiments may thus provide a method of generating a self-test signal (e.g., RF.sub.TEST) for a receiver of radiofrequency signals (e.g., a radar sensor 10) wherein a local oscillator signal (e.g., TX/LO) is generated (e.g., at 122) for mixing (e.g., at 28) with a reception signal (e.g., 22), the method including: applying frequency division (e.g., 124) to said local oscillator signal to produce a frequency-divided signal (e.g., f.sub.DIV), providing a signal generator (e.g., 222 in FIG. 3 or 320a in FIG. 4) for generating said self-test signal, and generating said self-test signal by operating said signal generator with operation of said signal generator monitored (e.g., via the counter 226 of FIG. 3) or controlled (e.g., via the PLL circuit 320 of FIG. 4) via said frequency-divided signal.

(66) One or more embodiments may include: generating said local oscillator signal via a first oscillator (e.g., 122), generating via a second oscillator (e.g., 222 or 320a) a further oscillating signal to provide said self-test signal with operation of said second oscillator monitored or controlled via said frequency-divided signal.

(67) One or more embodiments may include: setting the frequencies of said first oscillator and said second oscillator with a common coarse tuning signal (e.g., V.sub.COARSE), and finely tuning the frequencies of said first oscillator and said second oscillator with respective fine tuning signals (e.g., V.sub.FINE, V.sub.FINE_AUX), at least one of said fine tuning signals (V.sub.FINE, V.sub.FINE_AUX) optionally produced by means of a digital-to-analog converter (222a).

(68) One or more embodiments may include selectively tuning (e.g., via the microcontroller MC) the frequency of said second oscillator (e.g., 222) to produce chirp modulation of said self-test signal.

(69) One or more embodiments may include: applying frequency division (e.g., at 124, 224) to said local oscillator signal and said further oscillating signal to produce respective frequency-divided oscillating signals (e.g., f.sub.DIV, f.sub.DIV_AUX), and monitoring the frequency of said further oscillating signal by comparing (e.g., via the frequency counter 226) said respective frequency-divided oscillating signals.

(70) One or more embodiments may include: providing a PLL circuit (e.g., 320) with an output oscillator (e.g., 320a) for generating said self-test signal, an input comparator (e.g., 320b) and a loop divider (e.g., 320c) between said output oscillator and said input comparator, supplying to said input comparator of the PLL circuit said frequency-divided signal.

(71) One or more embodiments may include supplying to said input comparator of the PLL circuit a time delayed (322, f.sub.REF) version of said frequency-divided signal.

(72) One or more embodiments may include selectively varying (e.g., vie the microcontroller MC) the division factor of said loop divider to vary the frequency of said self-test signal.

(73) One or more embodiments may provide a circuit (e.g., 120, 32), including: a local oscillator for generating a local oscillator signal, at least one mixer for mixing said local oscillator signal with a reception signal, at least one frequency divider for applying to said local oscillator signal frequency division to produce a frequency-divided signal, at least one further oscillator

(74) the circuit configured for operating with the method of one or more embodiments and generating said self-test signal with operation of said signal generator monitored or controlled via said frequency-divided signal.

(75) One or more embodiments may include a Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC) on a Printed Circuit Board (PCB), the circuit including at least one coupler (e.g., 24) for coupling said self-test signal to a receiver input, wherein said at least one coupler: is hosted on said Printed Circuit Board (PCB) externally of said Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC); or is hosted internally of said Microwave/Millimeter-wave Monolithic Integrated Circuit (MMIC).

(76) One or more embodiments may provide a receiver of radiofrequency signals (e.g., a radar sensor, including a radar sensor IC) including a circuit for generating self-test signals according to one or more embodiments.

(77) In one or more embodiments such a receiver may include a radar receiver for automotive vehicles, wherein said reception signal of the receiver is an echo signal from an object at a distance from a vehicle (see, e.g., O and d in FIG. 1).

(78) Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described herein made by way of example, without departing from the extent of protection.

(79) The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

(80) Some embodiments may take the form of or include computer program products. For example, according to one embodiment there is provided a computer readable medium including a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium such as for example a Read Only Memory (ROM) chip, or a disk such as a Digital Versatile Disk (DVD-ROM), Compact Disk (CD-ROM), a hard disk, a memory, a network, or a portable media article to be read by an appropriate drive or via an appropriate connection, including as encoded in one or more barcodes or other related codes stored on one or more such computer-readable mediums and being readable by an appropriate reader device.

(81) Furthermore, in some embodiments, some of the systems and/or modules and/or circuits and/or blocks may be implemented or provided in other manners, such as at least partially in firmware and/or hardware, including, but not limited to, one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuitry, logic gates, standard integrated circuits, state machines, look-up tables, controllers (e.g., by executing appropriate instructions, and including microcontrollers and/or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices that employ RFID technology, and various combinations thereof.

(82) These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.