Galvanic isolated device and corresponding system

Abstract

A device including an optoelectric circuit that is configured to provide galvanic isolation between a first circuit and a second circuit is disclosed. The optoelectric circuit includes at least one non-inverting buffer and a metal semiconductor diode. The at least one non-inverting buffer is positioned between a collector of a phototransistor and an anode of a light emitting diode. The metal semiconductor diode is positioned between the collector of the phototransistor and the at least one non-inverting buffer.

Claims

1. A device, comprising: an optoelectric circuit configured to provide galvanic isolation between a first circuit and a second circuit, wherein the optoelectric circuit includes: at least one non-inverting buffer positioned between a collector of a phototransistor and an anode of a light emitting diode, and a metal semiconductor diode positioned between the collector of the phototransistor and the at least one non-inverting buffer.

2. The device of claim 1, wherein at least three non-inverting buffers are positioned between the collector of the phototransistor and the anode of the light emitting diode.

3. A system, comprising: a first circuit and a second circuit; and an optoelectric circuit configured to provide galvanic isolation between the first circuit and the second cirrcuit according to claim 1.

4. The device according to claim 1, wherein at least one of the first circuit and the second circuit is an Inter-integrated circuit.

5. The device according to claim 1, wherein at least one of the first circuit and the second circuit is coupled to a high-voltage AC power supply.

6. The system according to claim 3, wherein at least one of the first circuit and the second circuit is an Inter-integrated circuit.

7. The system according to claim 3, wherein at least one of the first circuit and the second circuit is coupled to a high-voltage AC power supply.

8. A method, comprising: providing a signal to an optoelectric circuit from a first circuit; transmitting the signal to a second circuit using the optoelectric circuit; wherein the optoelectric circuit includes: at least one non-inverting buffer positioned between a collector of a phototransistor and an anode of a light emitting diode, and a metal semiconductor diode positioned between the collector of the phototransistor and the at least one non-inverting buffer.

9. The method of claim 8, wherein at least three non-inverting buffers are positioned between the collector of the phototransistor and the anode of the light emitting diode.

10. The method of claim 8, wherein at least one of the first circuit and the second circuit is and Inter-integrated circuit.

11. A computer program product for a programmable apparatus, the computer program product comprising a sequence of instructions for implementing a method according to claim 8, when loaded into and executed by the programmable apparatus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the disclosure will now be described, by way of example only, and with reference to the following drawings in which:

(2) FIG. 1 illustrates a prior art galvanic isolation circuit;

(3) FIG. 2 is an illustration of an exemplary bi-directional data communication device according to an embodiment of the disclosure;

(4) FIG. 3 is an illustration of an exemplary bi-directional data communication device according to another embodiment of the disclosure; and

(5) FIG. 4 illustrates a flowchart of an exemplary method in accordance with one embodiment of the disclosure.

(6) It should be understood that the drawings are for purposes of illustrating the concepts of the disclosure and is not necessarily the only possible configuration for illustrating the disclosure.

DETAILED DESCRIPTION

(7) Galvanic isolation may be achieved using optical isolation. For example, an optical isolator may transmit electrical signals between two isolated circuits using light. Optical isolators prevent high voltages from affecting the system receiving such signals.

(8) A common type of optical isolator includes a light emitting diode (LED) and a phototransistor combination. Other exemplary source-sensor combinations may include LED-photodiode, LED-LASCR (Light Activated Silicon Controlled Rectifier) and lamp-photoresistor pairs. Typically, optical isolators transfer digital (on-off) signals, but analog signals may also be used in some instances.

(9) FIG. 2 illustrates an exemplary bi-directional data communication system 10 in accordance with an embodiment of the present disclosure. System 10 includes communication buses 27a, 27b, which may be for example I.sup.2C circuits. Coupled between communication buses 27a, 27b is an optoelectric circuit 15.

(10) Optoelectric circuit 15 includes optical isolators 25a, 25b which are used to transmit signals between the communication buses 27a, 27b. The optical isolators 25a, 25b include a phototransistor 26a, 26b and a light emitting diode 24a, 24b. A non-latching solution is provided by including non-inverting buffers 29a, 29b, 29c between the collector of the phototransistor 26a, 26b and the anode of the light emitting diode 24a, 24b.

(11) The non-inverting buffers 29a, 29b, 29c allow the phototransistor 26a to go to a low logic level, but does not cause the light emitting diode 24b to emit light. Thus, optoelectric circuit 15 is a non-latching type. In one embodiment, non-inverting buffers 29a, 29b are positioned in series, while non-inverting buffer 29c is positioned parallel to non-inverting buffers 29a, 29b.

(12) FIG. 3 illustrates an exemplary bi-directional data communication system 30 in accordance with another aspect of the present disclosure. System 30 includes communication buses 37a, 37b, which may be for example I.sup.2C circuits. Coupled between communication buses 37a, 37b is an optoelectric circuit 33.

(13) Optoelectric circuit 33 includes optical isolators 35a, 35b which are used to transmit signals between the communication buses 37a, 37b. The optical isolators 35a, 35b include a phototransistor 36a, 36b and a light emitting diode 34a, 34b. A non-latching solution is provided by including at least one non-inverting buffer 39a and a metal-semiconductor diode 31a, 31b between the collector of the phototransistor 36a, 36b and the anode of the light emitting diode 34a, 34b.

(14) The addition of the metal semiconductor diode 31a, 31b and at least one non-inverting buffer 29a allows the collector of the phototransistor 36a to go to a low logic level, but does not cause the light emitting diode 34b to emit light. This is because the metal semiconductor diode 31a causes light emitting diode 34b to short circuit. Thus, optoelectric circuit 33 is a non-latching type.

(15) FIG. 4 illustrates a flowchart of an exemplary method 400 in accordance with another aspect of the disclosure. In step 405, a signal is provided to an optelectric circuit from a first circuit. The optoelectric circuit may receive digital (on-off) signals, but analog signals may also be used. The first circuit may include a communication bus, which may be for example, an I.sup.2C circuit.

(16) The signal received from the first circuit is then transmitted to a second circuit via the optoelectric circuit, as depicted in step 410. The optoelectric circuit uses galvanic isolation to transmit the received signal to the second circuit using optical transmitter-sensor pairs, such as for example, light emitting diode (LED)-phototransistor, LED-photodiode, LED-LASCR (Light Activated Silicon Controlled Rectifier) and lamp-photoresistor pairs.

(17) The second circuit may include a communication bus, which may be for example, an JC circuit. Additionally, at least one of the first circuit and the second circuit may be coupled to a high voltage AC power supply.

(18) It should be understood that the elements shown in the figures may be implemented in various forms of hardware, software or combinations thereof. Preferably, these elements are implemented in a combination of hardware and software on one or more appropriately programmed general-purpose devices, which may include a processor, memory and input/output interfaces. Herein the phrase “coupled” is defined to mean directly connected to or indirectly connected with, through one or more intermediate components. Such intermediate components may include both hardware and software based components.

(19) The present description illustrates the principles of the present disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its scope.

(20) All examples and conditional language recited herein are intended for educational purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

(21) Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

(22) Thus, for example, it will be appreciated by those skilled in the art that the diagrams presented herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

(23) The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, read only memory (ROM) for storing software, random access memory (RAM), and nonvolatile storage.

(24) Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

(25) In the claims, hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The disclosure as defined by such claims resides in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.