Device for measuring the current flowing in an inductive load

Abstract

A circuit includes a switching circuit including a first switch and a second switch. A current sensing circuit is coupled to the switching circuit to sense a first current through the first switch and to generate a first sensed current signal based on the sensed first current, and configured to sense a second current through the second switch and to generate a second sensed current signal based on the sensed second current. An output circuit is coupled to the current sensing circuit and is configured to generate a failure signal based on the first sensed current signal and the second sensed current signal.

Claims

1. A circuit, comprising: a switching circuit including a first switch and a second switch, the first switch having a first terminal coupled to a first node and a second terminal coupled to a second node, the second switch having a first terminal coupled to the second node and a second terminal coupled to a third node; a current sensing circuit coupled to the switching circuit, the current sensing circuit including: a first current-sense amplifier configured to sense a first current through the first switch at a first location between the second terminal of the first switch and the second node, and to generate a first sensed current signal based on the sensed first current, and a second current-sense amplifier configured to sense a second current through the second switch at a second location between the first terminal of the second switch and the second node, and to generate a second sensed current signal based on the sensed second current, wherein the second node is disposed between the first location and the second location; and an output circuit coupled to the current sensing circuit and configured to generate a failure signal based on the first sensed current signal and the second sensed current signal.

2. The circuit of claim 1, wherein the output circuit is configured to generate the failure signal based on a difference between the first sensed current signal and second sensed current signal.

3. The circuit of claim 2, wherein the output circuit is configured to generate an error signal based on the difference between first sensed current signal and the second sensed current signal, and is further configured to generate the failure signal based on the error signal.

4. The circuit of claim 3, wherein the output circuit comprises window comparator configured to generate the failure signal in response to the error signal, a first threshold value, and a second threshold value.

5. The circuit of claim 4, wherein the output circuit further comprises a first sample and hold circuit and a second sample and hold circuit configured to sample the first current and the second current, respectively.

6. The circuit of claim 1, wherein the first switch and the second switch comprise a first transistor and a second transistor, respectively.

7. The circuit of claim 6, wherein each of the first transistor and the second transistor is an power N-channel MOSFET transistor.

8. The circuit of claim 1, wherein the switching circuit comprises a half-bridge circuit.

9. The circuit of claim 1, wherein: the first node is configured to receive a first supply voltage a-configured to be coupled to a first terminal of an inductive load, the second node is configured to be coupled to a second terminal of the inductive load, and the third node configured to receive a second supply voltage.

10. The circuit of claim 1, wherein the switching circuit comprises the first and second switches coupled in series with first and second measurement resistors.

11. A load driver circuit, comprising: a switching circuit including first and second nodes configured to be coupled to an inductive load, a first switch having a first terminal coupled to the first node and a second terminal coupled to the second node, and a second switch having a first terminal coupled to the second node and a second terminal coupled to a third node configured to receive a reference supply voltage; a current sensing circuit coupled to the switching circuit, the current sensing circuit including: a first current-sense amplifier configured to sense a first current through the first switch at a first location between the second terminal of the first switch and the second node, and a second current-sense amplifier configured to sense a second current through the second switch at a second location between the first terminal of the second switch and the second node, wherein the second node is disposed between the first location and the second location; and an output circuit coupled to the current sensing circuit and configured to generate a failure signal based on the first and second currents, the failure signal indicating if peak values of the first and second currents differ by a predefined value.

12. The load driver circuit of claim 11, wherein the output circuit is configured to generate the failure signal based on a difference between the sensed first and second currents.

13. The load driver circuit of claim 11, wherein the output circuit is configured to receive a first threshold value and a second threshold value, and is configured to generate the failure signal indicating the peak values differ by the predefined value based on a window defined by the first threshold value and second threshold value.

14. The load driver circuit of claim 13, wherein the output circuit is configured to generate and error signal based on a difference between the sensed first and second currents, and is configured to activate the failure signal in response to the error signal having a value outside the window defined by the first threshold value and second threshold value.

15. The load driver circuit of claim 11, wherein the switching circuit is configured to receive a control signal and the current sensing circuit is configured to receive a clock signal derived from the control signal.

16. A method, comprising: sensing, by a first current-sense amplifier, a first current flowing through a first switch at a first location, the first switch having a first terminal coupled to a first node and a second terminal coupled to a second node, the first node further coupled to a first terminal of an inductive load, the first location being between the second terminal of the first switch and the second node; sensing, by a second current-sense amplifier, a second current flowing through a second switch at a second location, the second switch having a first terminal coupled to the second node and a second terminal coupled to a third node, the second node further coupled to a second terminal of the inductive load, the second location being between the first terminal of the second switch and the second node; generating a current error signal based on a difference between the sensed first current and the sensed second current; and generating a failure signal based upon the current error signal.

17. The method of claim 16, wherein generating the failure signal comprises activating the failure signal in response to the current error signal having a value outside a window defined by a first threshold value and a second threshold value.

18. The method of claim 16, wherein sensing the first current comprises closing the second switch.

19. The method of claim 18, wherein sensing the second current comprises closing the first switch.

20. The load driver circuit of claim 11, wherein the switching circuit comprises the first and second switches coupled in series with first and second measurement resistors.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) One or more embodiments will now be described, purely by way of example, with reference to the annexed drawings, wherein:

(2) FIGS. 1, 1a, 1b, 1c, 1d, and 2, regarding solutions belonging to the prior art, have already been described; and

(3) FIGS. 3-12 are examples of various embodiments of a device for measuring the current that flows in an inductive load.

DETAILED DESCRIPTION

(4) In the ensuing description, one or more specific details are illustrated in order to provide an in-depth understanding of the examples of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known operations, materials or structures are not illustrated or described in detail so that certain aspects of the embodiments will not be obscured.

(5) Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described with reference to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer precisely to one and the same embodiment. Furthermore, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(6) The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(7) In particular, the solution proposed does not interfere, reducing the performance in terms of speed, with the known solutions illustrated in FIGS. 1, 1a, 1b, 1c, 1d and 2.

(8) Parts that are the same as one another in the various devices for measuring current in inductive loads illustrated in the various figures are designated by the same references.

(9) Consequently, the similar blocks already described with reference to the figures regarding the solutions of prior art will not be described again.

(10) With reference to FIG. 3, an embodiment of the solution described herein measures the current of the inductive load Inductive Load separately on the path of the high-side MOSFET HS and on the path of the low-side MOSFET LS.

(11) Various embodiments of the solutions proposed exploit the principle of the inductive current that does not change significantly at the moment when there is switching from the transistor HS to the transistor LS, and vice versa.

(12) The comparison between the two currents is not continuous in time as in the known solution, but is made between the current of the low-side MOSFET LS an instant before this turns off and the current of the high-side MOSFET HS an instant after this has turned on. In this case, in the embodiments described herein, the comparison is made between the two currents at the maximum peak where there is passage from conduction of the transistor LS to conduction of the transistor HS.

(13) In particular, in the embodiment illustrated in FIG. 3, two different current-measuring paths detect the current I.sub.L of the load that flows in the transistor HS and in the transistor LS.

(14) In particular, the device for measuring the current is driven at input by a control signal com. In greater detail, the gate terminal of the high-side MOSFET HS receives the control signal com inverted by the inverter 10, while the gate terminal of the low-side MOSFET LS receives the control signal com in a direct way via the stage 12.

(15) The current I.sub.L in the inductive load is reconstructed by adding, in an adder SUM, the contributions of the two high-side and low-side sections, in particular by adding the outputs of the current-sense amplifiers (CSAs).

(16) The maximum current peak is sampled and held (S&H) separately on the path of the high-side transistor HS and on the path of the high-side transistor LS, respectively, via the two sample-and-hold blocks S&H.sub.1 and S&H.sub.2.

(17) For instance, in various embodiments, the sample-and-hold blocks S&H can be obtained with very simple sequential electronic circuits, such as flip-flops. In particular, the signal present on the input terminal D.sub.IN at the next enable signal supplied at input on the clock terminal CK passes at output as signal D.sub.OUT.

(18) Furthermore, the control signal com inverted by the inverter stage 14, denoted as com, is used as activation signal (or clock signal) for enabling the sample-and-hold blocks S&H.sub.1 and S&H.sub.2.

(19) In particular, the inverted signal com is brought at input as signal S directly on the clock input of the block S&H.sub.2, whereas it is first delayed by a delay block 16 and then sent at input as signal S.sub.del on the clock input of the block S&H.sub.1.

(20) A subtractor node SUB generates the error signal err as the difference of the outputs of the two sample-and-hold blocks S&H.sub.1 and S&H.sub.2.

(21) A window comparator 18 generates a failure signal Fail in the case where the error signal err falls outside a predefined window. Hence, the resulting failure signal Fail indicates the case where the maximum peaks of the currents in the transistors HS and LS differ by a predefined value.

(22) The waveforms appearing in FIG. 3 represent, respectively, the voltage V.sub.Q on the node Q, the current I.sub.L on the inductive load, the currents I.sub.L-HS and I.sub.L-LS in the two respective separate measurement paths (and the output signals of the sample-and-hold blocks S&H.sub.1output and S&H.sub.2output), the delayed clock signal S.sub.del, the clock signal S, and the control signal com. In this case, the waveforms reproduced show that the outputs S&H.sub.1output and S&H.sub.2output of the sample-and-hold blocks S&H.sub.1 and S&H.sub.2 are at a level that corresponds to the maximum peak, where there is the passage from conduction of the transistor LS to conduction of the transistor HS.

(23) In various embodiments, the comparison can also be made between the current that flows in the transistor HS an instant before this turns off and the current that flows in the transistor LS an instant after this has turned on (see, for example, FIG. 6).

(24) With reference to FIG. 6, in this case the comparison is made between the two currents at the minimum peak, where there is passage from conduction of the transistor HS to conduction of the transistor LS.

(25) In this embodiment (FIG. 6), unlike the embodiment of FIG. 3, the control signal com is used as activation signal (or clock signal) for enabling the sample-and-hold blocks S&H.sub.1 and S&H.sub.2. Furthermore, in this case the inverter stage 14 is not necessary.

(26) In particular, the delay block 16 is replaced by a delay block 16′ set on the low-side path, for generating a signal S.sub.del, which is sent at input as clock signal of the block S&H.sub.2.

(27) In this case, the waveforms reproduced show that the outputs S&H.sub.1output and S&H.sub.2output of the sample-and-hold blocks S&H.sub.1 and S&H.sub.2 are at a level that corresponds to the minimum peak, where there is passage from conduction of the transistor HS to conduction of the transistor LS.

(28) In various embodiments, it may be envisaged that the checks are made on both of the peaks, as illustrated in FIGS. 7 and 8.

(29) Illustrated in FIGS. 7 and 8 is a possible variant of the embodiments, which represents a combination of the principles proposed in the embodiments of FIGS. 3 and 6. In particular, in this case both of the maximum and minimum current peaks are sampled and held (S&H) on the two transistors HS and LS separately with the two blocks S&H.sub.1 and S&H.sub.2, respectively. The filtering block combines and averages the values of the minimum and maximum peaks of the two transistors HS, LS in such a way as to: separate the signal from the noise; and accept or reject various types of failure.

(30) In FIG. 7 a finite-state machine is present, which generates the signals s.sub.1 and s.sub.2 that are required for driving the filter. The filter receives at input the two values S&H.sub.1output and S&H.sub.2output at output from the sample-and-hold blocks S&H.sub.1 and S&H.sub.2 and generates the value err at output.

(31) In particular, FIG. 8a shows the detection of the failures.

(32) Detection of the failures due to the leakage resistances RH.sub.LEAK and RL.sub.LEAK is guaranteed irrespective of whether they are inside or outside the load driver device Load Driver. In particular, in FIG. 8a, which exemplifies an embodiment, the two leakage resistances RH.sub.LEAK and RL.sub.LEAK are within the load driver device Load Driver.

(33) Also indicated are the two leakage currents that flow in the two resistors RH.sub.LEAK and RL.sub.LEAK, which can be calculated as:

(34) ${\mathrm{IH}}_{\mathrm{LEAK}}=\frac{V_{\mathrm{POS}}-V_{\mathrm{NEG}}}{{\mathrm{RH}}_{\mathrm{LEAK}}}$${\mathrm{IL}}_{\mathrm{LEAK}}=\frac{V_{\mathrm{POS}}-V_{\mathrm{NEG}}}{{\mathrm{RL}}_{\mathrm{LEAK}}}$

(35) FIG. 8b shows the waveforms in the case of a classic filter with the following characteristic:

(36) $\mathrm{err}=\frac{1}{n}\underset{i=1}{\overset{n}{.Math.}}\left(S\&H_{2,i}-S\&H_{1,i}\right)$

(37) In particular, the filtering block: subtracts corresponding samples S&H.sub.j,i with j=1,2; in this way, it detects the failures of the leakage or dispersion currents IH.sub.LEAK and IL.sub.LEAK; it also detects, with the same principle, errors in the gain chain of the two current-sense amplifiers CSA.sub.1 and CSA.sub.2; and averages the “n” samples; in this way it reduces the noise of the individual samples.

(38) The criterion of acceptance is that the difference of the measurements should be lower than a pre-set maximum error; instead, if the error is higher than a maximum value, it is not accepted. Consequently, in all the figures representing the solutions described herein, a window comparator always appears.

(39) With reference to FIG. 4, the first of the two samplings is made on the transistor LS before it turns off, as in FIG. 3. Instead, the second sampling is made after calculation of the difference between the sample of the transistor HS just turned on and the previously stored sample of the transistor LS.

(40) In particular, a subtractor node SUB1 calculates the value err1 as difference between the value of the current that flows in the transistor HS and the value of the current that was flowing at the previous instant in the transistor LS and was previously stored in the block S&H.sub.2.

(41) The second sampler S&H.sub.1 in this case must store a difference that is normally close to zero and in any case must exceed the pre-set maximum error only slightly. Consequently, in this case, the second sampler S&H.sub.1 receives at input the value err1, samples it, stores it, and makes it available at output at the next clock signal. Consequently, the signal at output from the second sampler S&H.sub.1 represents the error err.

(42) The second sampler S&H.sub.1 presents the advantage of greater simplicity in so far as it requires a lower accuracy, because the difference is calculated before, and a smaller storage capacity, because the difference signal has a lower value.

(43) With reference to FIG. 5, the second sampler S&H.sub.1 is shifted even further downstream with respect to the solution of FIG. 4, in particular after the window comparator. The final result (signal Fail) remains unaltered after this modification. The advantage for the second sampler S&H.sub.2 is even more marked since it becomes a flip-flop in so far as it has to store just one logic information bit (low level “0” or high level “1”).

(44) Consequently, the embodiment illustrated in FIG. 5 follows the same principle as the solution illustrated in FIG. 4, where the second sampler S&H.sub.1 has been shifted after the window comparator.

(45) The advantage of this embodiment is represented by the fact that the second sampler S&H.sub.1 has a minimal complexity since it processes a single-bit digital signal.

(46) With reference to FIG. 6, the comparison of currents may also be made between that of the transistor HS an instant before this turns off and that of the transistor LS an instant after this has turned on. In this case, the comparison is made between the two currents at the minimum peak where there is passage from conduction of the transistor HS to conduction of the transistor LS.

(47) The passages described in FIGS. 4 and 5 also apply to the embodiment of FIG. 6.

(48) In particular, the same principle as that of the embodiment of FIG. 3 applies, where the minimum peak current is sampled and held (S&H) on the two, high-side and low-side, portions separately by the two blocks S&H.sub.1 and S&H.sub.2, respectively.

(49) As already said, the operating principle of this embodiment also applies to the solutions proposed in FIGS. 4 and 5.

(50) FIG. 9 shows a further alternative embodiment.

(51) In the solutions proposed according to FIGS. 3 to 8, the measurement of current can be made via two series resistances, which, however, are activated just one at a time. Consequently, there is a minimal impact on the series resistance of the total impedance seen between the pins of the integrated device. In particular, the path from the node D to the node Q is made up of R.sub.S1 and R.sub.HS. Furthermore, the path from the node Q to the node G is made up of R.sub.S2 and R.sub.LS.

(52) The solution proposed consequently adds just one series resistance on each of the two paths. Consequently, the power transistors do not require any oversizing with respect to the case of current measurement in the absence of redundancy for functional safety.

(53) FIG. 10 shows a further alternative embodiment.

(54) In particular, in this embodiment, the current is sampled on the drain and on the source of the two transistors HS and LS.

(55) This embodiment adopts a known practice alternative to the measurement of current according to FIG. 9, i.e., that of using the power MOS transistor (HS and LS), which, when it is turned on, has an impedance equivalent to that of a resistance (R.sub.HS and R.sub.LS, respectively). With this solution, the measurement of current has a zero impact on the series resistance of the total impedance seen between the pins of the integrated device. Consequently, the path from the node D to the node Q is only constituted by R.sub.HS. Instead, the path from the node Q to the node G is only constituted by R.sub.LS.

(56) With respect to the embodiment proposed in FIG. 9, the current-detection resistances R.sub.S1 and R.sub.S2 are obtained with the resistances R.sub.HS and R.sub.LS, respectively, of the power MOS transistors. In this way, the total impedances on the paths HS and LS are due just to the ON-resistance of the power MOS transistors themselves, and consequently the size of the circuit area is minimized.

(57) In the embodiments proposed according to FIGS. 3 to 9, the measurement of current may be made via the power MOS transistor (HS and LS), as in the case of the known solution, without any drawbacks.

(58) In all the solutions proposed up to FIG. 10, an analog-to-digital converter is introduced on both of the outputs of the CSA, and consequently all the subsequent functions are implemented in digital technology.

(59) FIG. 11 shows by way of example the digital evolution of the embodiment of FIG. 7.

(60) In particular, in FIG. 11 the analog-to-digital converters (ADCs) have been introduced.

(61) All the solutions proposed describe a load with one side connected to the positive supply; however, the same solutions apply also in the case of a load with one side connected to the negative supply, or else with both sides of the load driven.

(62) Some types of inductive load, such as the solenoids of automotive braking systems, show a current that varies fast after switching of the driver.

(63) All the solutions proposed up to FIG. 11 would calculate an error err.sub.0 even in the case of normal operation in the absence of failures. This error would be rather high with respect to what there would be in the case of failure. It is consequently necessary to erase this error prior to sending the result to the input of the window comparator.

(64) In general, this error err.sub.0 depends upon the characteristics of the inductive load and the operating conditions to which it is subjected (supply voltage, average operating currents, temperature, etc.).

(65) The solution proposed in FIG. 12 is a table that estimates the value of err.sub.0 on the basis of the operating conditions mentioned above and a subtractor that subtracts it from the measurement obtained with any of the embodiments proposed up to FIG. 11.

(66) FIG. 12 reproduces a case of inductive load with fast time constant.

(67) In this case, the waveform of the load current is a steep exponential rather than triangular, as in the previous figures. All the embodiments proposed for this case show a high value of err.sub.0 also in the case of normal operation.

(68) In this case, the solution proposed is an additional block that subtracts the above value of err.sub.0 upstream of the window comparator that makes the decision as to whether there is a failure or not. This value is stored within a table that takes into account all the independent variables that affect the value itself, such as: the supply voltage of the driver load; the average current in the load; and the temperature of the load.

(69) Without prejudice to the underlying principles, the details and the embodiments may vary, even appreciably, with respect to what has been described purely by way of example, without thereby departing from the sphere of protection, as this is defined by the annexed claims.

(70) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.