Resistive random access memory device

Abstract

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Claims

1. A method of manufacturing a resistive random access memory device, the method comprising: forming a first electrode; forming, on the first electrode, a solid electrolyte made of metal oxide extending at least partially onto the first electrode; forming, on the solid electrolyte made of metal oxide, an interface layer; forming, on the interface layer, a soluble second electrode, the soluble second electrode being configured to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first electrode and the soluble second electrode when a voltage is applied between the first electrode and the soluble second electrode, wherein said forming, on the solid electrolyte made of metal oxide, of the interface layer comprises the following sub-steps: (i) a first sub-step of depositing, on the solid electrolyte made of metal oxide, a layer comprising a chalcogen element and a soluble conductive element; (ii) after the first sub-step, a second sub-step of depositing, on the layer comprising the chalcogen element and the soluble conductive element, a layer comprising a transition metal from groups 3, 4, 5 or 6 of the periodic table; and (iii) after the second sub-step, a third sub-step of thermal annealing for at least partially diffusing the transition metal into the layer comprising the chalcogen element and the soluble conductive element, and for obtaining the interface layer; and wherein said forming, on the interface layer, of the soluble second electrode comprises depositing, on the interface layer, an ion source layer comprising the soluble conductive element, said depositing, on the interface layer, of the ion source layer being carried out after said third sub-step of thermal annealing.

2. The method according to claim 1, wherein forming the soluble second electrode comprises: depositing, on the ion source layer comprising the soluble conductive element, a diffusion barrier made from a conductive material; depositing, on the diffusion barrier, an electrical contact layer made from a conductive material; the ion source layer, the diffusion barrier and the electrical contact layer forming the soluble second electrode, the diffusion barrier being configured to limit at least partially the diffusion of the conductive material of the electrical contact layer to the ion source layer over a given temperature range.

3. The method according to claim 1, wherein the transition metal is from groups 3, 4, 5 or 6 of the periodic table is titanium (Ti).

4. The method according to claim 1, wherein the chalcogen element is tellurium (Te).

5. The method according to claim 1, wherein the layer comprising the transition metal from groups 3, 4, 5 or 6 of the periodic table is deposited in contact with the layer comprising the chalcogen element and the soluble conductive element.

6. The method according to claim 1, wherein the layer comprising the chalcogen element and the soluble conductive element is a single layer.

7. The method according to claim 1, wherein the layer comprising the chalcogen element and the soluble conductive element and the layer comprising the transition metal from groups 3, 4, 5 or 6 of the periodic table are the only two layers deposited for forming the interface layer before performing the thermal annealing.

8. The method according to claim 1, wherein the layer comprising the chalcogen element and the soluble conductive element is the only layer deposited between the solid electrolyte made of metal oxide and the layer comprising the transition metal from groups 3, 4, 5 or 6 of the periodic table.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The figures are presented for indicative purposes and in no way limit the invention.

(2) FIG. 1 shows a schematic representation of the passage from an “OFF” state to an “ON” state for a CBRAM type memory device.

(3) FIG. 2 schematically illustrates a metal oxide based CBRAM memory cell according to an aspect of the invention.

(4) FIGS. 3a, 3b, 3c and 3d show the steps of a first method of manufacturing a metal oxide based CBRAM memory cell according to a first embodiment of the invention.

(5) FIGS. 4a, 4b, 4c and 4d show the steps of a second method of manufacturing a metal oxide based CBRAM memory cell according to the first embodiment of the invention.

(6) FIGS. 5a, 5b, 5c and 5d show the steps of a first method of manufacturing a metal oxide based CBRAM memory cell according to a second embodiment of the invention.

(7) FIGS. 6a, 6b, 6c and 6d show the steps of a second method of manufacturing a metal oxide based CBRAM memory cell according to the second embodiment of the invention.

DETAILED DESCRIPTION

(8) Unless stated otherwise, a same element appearing in the different figures has a single reference.

(9) In the present description, the expressions “CBRAM memory cell”, “CBRAM type memory device” and “resistive random access memory device” will be employed indiscriminately.

(10) FIG. 1, which shows a schematic representation of the passage from an “OFF” state to an “ON” state for a CBRAM type memory device, has been described previously.

(11) FIG. 2 schematically illustrates a metal oxide based CBRAM memory cell 10 according to a first embodiment of the invention. The CBRAM memory cell 10 according to the first embodiment of the invention comprises: a first electrode E1, also called “inert electrode” or “cathode”, extending along a reference plane; a solid electrolyte ML made of metal oxide, extending onto the first electrode E1, parallel to the reference plane; an interface layer INT1 of a first type extending onto the solid electrolyte ML made of metal oxide, parallel to the reference plane; a second electrode E2, also called “soluble electrode” or “anode”, extending onto the interface layer INT, parallel to the reference plane.

(12) The second electrode E2 includes: a first layer ISL, designated “ion source layer” made from a soluble conductive element and extending onto the interface layer INT1 of the first type; a second layer DB, designated “diffusion barrier”, made from a conductive material and extending onto the ion source layer ISL; a third layer CT, designated “electrical contact layer”, made from a conductive material and extending at least partially onto the diffusion barrier DB.

(13) The first electrode E1 is made of an inert conductive material, that is to say not participating in the formation of a conductive filament within the solid electrolyte ML made of metal oxide. This inert conductive material may typically be: ruthenium Ru, ruthenium dioxide RuO.sub.2, tungsten W, tungsten nitride WN.sub.x, tantalum nitride TaN, titanium nitride TiN, or any alloy or combination of the elements which have just been cited.

(14) In the particular example represented in FIG. 2, the solid electrolyte ML made of metal oxide is made of gadolinium oxide Gd.sub.2O.sub.3. In particular, the solid electrolyte ML made of metal oxide may be made of hybrid gadolinium oxide Gd.sub.2O.sub.3, that is to say comprising at least one first sub-layer made of gadolinium oxide Gd.sub.2O.sub.3 and one second sub-layer made of gadolinium oxide Gd.sub.2O.sub.3. The first sub-layer is a standard sub-layer formed by RF sputtering using an argon Ar, xenon Xe or krypton Kr gas. The second sub-layer is formed by RF sputtering using, in addition to a main gas of argon Ar, xenon Xe or krypton Kr, oxygen as second gas such that the oxygen/main gas ratio is less than or equal to 1/16. The first and second sub-layers are, at least partially, directly in contact with each other, and the first and second sub-layers are typically substantially of the same thickness.

(15) Alternatively, the following configurations, considered individually or according to all technically possible combinations thereof, could be adopted: the solid electrolyte ML made of metal oxide is made of aluminium oxide Al.sub.2O.sub.3, zirconium dioxide ZrO.sub.2, titanium dioxide TiO.sub.2 or tantalum oxide Ta.sub.2O.sub.5; the solid electrolyte ML made of metal oxide comprises at least one bilayer of type Gd.sub.2O.sub.3/Al.sub.2O.sub.3, Gd.sub.2O.sub.3/GeO, Gd.sub.2O.sub.3/La.sub.2O.sub.3, Gd.sub.2O.sub.3/Li.sub.2O, Gd.sub.2O.sub.3/B.sub.2O.sub.3, Gd.sub.2O.sub.3/WO.sub.2, Gd.sub.2O.sub.3/VO.sub.2, Gd.sub.2O.sub.3/V.sub.2O.sub.5, Gd.sub.2O.sub.3/MgO or Gd.sub.2O.sub.3/MgAl.sub.2O.sub.4; the solid electrolyte ML made of metal oxide comprises at least one trilayer of type Gd.sub.2O.sub.3/Al.sub.2O.sub.3/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/GeO/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/La.sub.2O.sub.3/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/Li.sub.2O/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/B.sub.2O.sub.3/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/WO.sub.2/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/VO.sub.2/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/V.sub.2O.sub.5/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/MgO/Gd.sub.2O.sub.3, Gd.sub.2O.sub.3/MgAl.sub.2O.sub.4/Gd.sub.2O.sub.3.

(16) The ion source layer ISL of the second electrode E2 is made of soluble conductive material, that is to say participating in the formation of a conductive filament within the solid electrolyte ML made of metal oxide. The soluble conductive material may be for example: copper Cu; zinc Zn; silver Ag; copper nitride Cu.sub.3N; zinc nitride Zn.sub.3N.sub.2; silver nitride Ag.sub.3N.

(17) The diffusion barrier DB of the second electrode E2 is made of a conductive material, such as for example: titanium nitride TiN; tantalum nitride TaN; ruthenium Ru or ruthenium nitride RuN.

(18) The diffusion barrier DB is typically a thin layer, of thickness less than or equal to 5 nm. The thickness of the diffusion barrier DB is measured along a direction substantially perpendicular to the reference plane.

(19) It will be appreciated that the diffusion barrier DB makes it possible to contribute to an efficient control of the concentration of the transition metal in the interface layer INT.

(20) The electrical contact layer CT of the second electrode E2 is made from a conductive material, such as for example Ti—TiN, that is to say a layer of Ti and a layer of TiN, or Ta—TaN, that is to say a layer of Ta and a layer of TaN.

(21) According to the first embodiment of the invention, the interface layer INT1 of the first type comprises: a transition metal from groups 3, 4, 5 or 6 of the periodic table, referred to hereafter as “transition metal”, and a chalcogen element.

(22) In an embodiment, the transition metal is titanium Ti, or alternatively hafnium Hf or zirconium Zr. In an embodiment, the chalcogen element is tellurium Te, or alternatively sulphur S or selenium Se.

(23) The interface layer INT1 of the first type according to the first embodiment of the invention is also designated by the acronym ICL (Ion Crossing Layer).

(24) According to a second embodiment of the invention, the CBRAM memory cell (reference 20 of FIGS. 5d and 6d) includes an interface layer INT2 of a second type, comprising: a transition metal as described previously, a chalcogen element, and a soluble conductive element.

(25) The interface layer INT2 of the second type is particularly represented in FIGS. 5d and 6d, which are described hereafter.

(26) In the same way as previously:

(27) the transition metal of the interface layer INT2 of the second type is titanium Ti, or alternatively hafnium Hf or zirconium Zr, and the chalcogen element of the interface layer INT2 of the second type is tellurium Te, or alternatively sulphur S or selenium Se.

(28) The soluble conductive element of the interface layer INT2 of the second type is beneficially the same as the soluble conductive element of the ion source layer ISL. Thus, for example, when the ion source layer ISL is made from copper Cu, the soluble conductive element of the interface layer INT2 of the second type is copper Cu. The interface layer INT2 of the second type is also designated by the acronym IBL (Ion Buffer Layer). The choice of the soluble conductive material of the ion source layer ISL thus determines the soluble conductive element present in the interface layer INT2 of the second type.

(29) FIGS. 3a to 3d schematically illustrate the steps of a first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention, in which the CBRAM memory cell 10 comprises the interface layer of the first type INT1.

(30) The method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment firstly comprises the following steps: forming the first electrode E1; forming, on the first electrode E1, the solid electrolyte made of metal oxide ML; depositing, on the solid electrolyte made of metal oxide ML, a C1 layer comprising the chalcogen element; depositing, on the C1 layer comprising the chalcogen element, a C2 layer comprising the transition metal.

(31) FIG. 3a schematically shows the result obtained at the end of the steps which have just been cited. In the particular example of FIG. 3a, the transition metal of the C2 layer is titanium Ti, the solid electrolyte made of metal oxide ML is made of gadolinium oxide and the chalcogen element of the C1 layer is tellurium Te.

(32) The first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment then comprises a thermal annealing step, illustrated in FIG. 3b. This thermal annealing step is carried out typically at a temperature comprised between 100° C. and 450° C., and for a duration comprised between 1 minute and 20 minutes.

(33) The thermal annealing step enables the at least partial diffusion of the transition metal of the C2 layer, deposited previously, into the C1 layer comprising the chalcogen element. At the end of the thermal annealing step, the diffusion of the transition metal into the C1 layer makes it possible to obtain the interface layer of the first type INT1, comprising the transition metal and the chalcogen element. FIG. 3c schematically illustrates the stack thereby obtained at the end of the thermal annealing step.

(34) According to a first alternative, the first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This UV irradiation step is then carried out typically with an average power comprised between 20 mW/cm.sup.2 and 150 mW/cm.sup.2, for a duration comprised between 1 minute and 20 minutes, and for wavelengths comprised between 100 nm and 400 nm.

(35) It will be appreciated that the UV irradiation step makes it possible to break bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.

(36) According to this first alternative, the steps of thermal annealing and UV irradiation may then take place simultaneously or not. Thus, generally speaking: the thermal annealing step could indiscriminately start before, at the same time as or after the start of the UV irradiation step, and the thermal annealing step could indiscriminately end before, at the same time as or after the end of the UV irradiation step.

(37) The first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment finally comprises the following steps: depositing, on the interface layer of the first type INT1, the ion source layer ISL comprising the soluble conductive element; depositing, on the ion source layer ISL, the diffusion barrier DB; depositing, on the diffusion barrier DB, the electrical contact layer CT.

(38) The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.

(39) FIG. 3d schematically illustrates the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention, obtained by the manufacturing method 100; this cell 10 is identical to that illustrated in FIG. 2.

(40) FIGS. 4a to 4d schematically illustrate the steps of a second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention, in which the CBRAM memory cell 10 comprises the interface layer of the first type INT1.

(41) The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment firstly comprises, in the same way as the first method 100, the following steps: forming the first electrode E1; forming, on the first electrode E1, the solid electrolyte made of metal oxide ML.

(42) The second method 200 then comprises a step of depositing, on the solid electrolyte made of metal oxide ML, a C3 layer comprising the transition metal, the chalcogen element and a soluble conductive element. The soluble conductive element of the C3 layer is able to participate in the formation of a conductive filament within the solid electrolyte made of metal oxide ML and may thus for example be: copper Cu; zinc Zn; silver Ag; copper nitride Cu.sub.3N; zinc nitride Zn.sub.3N.sub.2; silver nitride Ag.sub.3N.

(43) FIG. 4a schematically shows the result obtained at the end of the steps that have just been cited. In the particular example of FIG. 4a, the C3 layer comprises titanium Ti, tellurium Te and copper Cu.

(44) The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment then comprises, in the same way as the first method 100, a thermal annealing step, illustrated in FIG. 4b. This thermal annealing step is carried out typically at a temperature comprised between 100° C. and 450° C., and for a duration comprised between 1 minute and 20 minutes.

(45) The thermal annealing step enables the at least partial separation of the species of the C3 layer and to obtain: the interface layer of the first type INT1, extending to the contact of the solid electrolyte made of metal oxide ML and comprising the transition metal and the chalcogen element, and the ion source layer ISL, extending to the contact of the interface layer of the first type INT1 and comprising the soluble conductive element.

(46) FIG. 4c schematically illustrates the stack thereby obtained at the end of the thermal annealing step.

(47) According to a first alternative, the second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This first alternative has been described previously in the case of the first method 100. The UV irradiation step makes it possible to break the bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.

(48) The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment finally comprises the following steps: depositing, on the ion source layer ISL, the diffusion barrier DB; depositing, on the diffusion barrier DB, the electrical contact layer CT.

(49) The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.

(50) FIG. 4d schematically illustrates the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention, obtained by the manufacturing method 200. This cell 10 is identical to that illustrated in FIG. 2.

(51) FIGS. 5a to 5d schematically show the steps of a first method 300 of manufacturing a metal oxide based CBRAM memory cell according to the second embodiment of the invention, in which the CBRAM memory cell 20 comprises the interface layer of the second type INT2. The first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment firstly comprises the following steps: forming the first electrode E1; forming, on the first electrode E1, the solid electrolyte made of metal oxide ML; depositing, on the solid electrolyte made of metal oxide ML, a C4 layer comprising the chalcogen element and a soluble conductive element; depositing, on the C4 layer comprising the chalcogen element and the soluble conductive element, a C2 layer comprising the transition metal.

(52) The choice of the soluble conductive element of the C4 layer is determined by the type of soluble conductive material that it is wished to use later to form the ion source layer ISL. For example, in the case where it is wished to form later an ion source layer ISL made of copper Cu, the soluble conductive element of the C4 layer is copper Cu.

(53) FIG. 5a schematically shows the result obtained at the end of the steps that have just been cited. In the particular example of FIG. 5a, the solid electrolyte made of metal oxide ML is made of gadolinium oxide and the C4 layer comprises tellurium Te and copper Cu.

(54) The first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment then comprises a thermal annealing step, illustrated in FIG. 5b. This thermal annealing step is carried out typically at a temperature comprised between 100° C. and 450° C., and for a duration comprised between 1 minute and 20 minutes.

(55) The thermal annealing step enables the at least partial diffusion of the transition metal of the C2 layer, deposited previously, into the C4 layer comprising the chalcogen element and the soluble conductive element. At the end of the thermal annealing step, the diffusion of the transition metal into the C4 layer makes it possible to obtain the interface layer of the second type INT2, comprising the transition metal, the chalcogen element and the soluble conductive element. FIG. 5c schematically illustrates the stack thereby obtained at the end of the thermal annealing step.

(56) According to a first alternative, the first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This first alternative has been described previously in the case of the first method 100 of manufacturing the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention. The UV irradiation step makes it possible to break bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.

(57) The first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment finally comprises the following steps: depositing, on the interface layer of the second type INT2, the ion source layer ISL, the ion source layer ISL comprising a soluble conductive element; depositing, on the ion source layer ISL, the diffusion barrier DB; depositing, on the diffusion barrier DB, the electrical contact layer CT.

(58) The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.

(59) As evoked above, FIG. 5d schematically illustrates a metal oxide based CBRAM memory cell 20 according to the second embodiment of the invention, obtained by the manufacturing method 300.

(60) FIGS. 6a to 6d schematically show the steps of a second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment of the invention (as represented in FIGS. 5d and 6d), in which the CBRAM memory cell 20 comprises the interface layer of the second type INT2.

(61) The second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment firstly comprises the following steps: forming the first electrode E1; forming, on the first electrode E1, the solid electrolyte made of metal oxide ML; depositing, on the solid electrolyte made of metal oxide ML, the interface layer of the first type INT1 comprising the transition metal and the chalcogen element; depositing, on the interface layer of the first type INT1, a C5 layer of a soluble conductive element.

(62) The soluble conductive element of the C5 layer is typically determined by the type of soluble conductive material that it is wished to use later to form the ion source layer ISL. In the case where it is wished to form later an ion source layer ISL made of copper Cu, the soluble conductive element of the C3 layer is copper Cu. FIG. 6a schematically shows the result obtained at the end of the steps which have just been cited.

(63) The second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment then comprises a thermal annealing step, illustrated in FIG. 6b. This thermal annealing step is carried out typically at a temperature comprised between 100° C. and 450° C., and for a duration comprised between 1 minute and 20 minutes.

(64) According to a first alternative, the second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment may comprise, instead of the thermal annealing step that has just been described, a UV irradiation step. According to a second alternative, the second method 400 may comprise the thermal annealing step and the UV irradiation step. These first and second alternatives have been described previously in the case of the first method 100 of manufacturing the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention.

(65) The thermal annealing step and/or the UV irradiation step enable the at least partial diffusion of the soluble conductive element of the C5 layer, deposited previously, into the interface layer of the first type INT1. At the end of the thermal annealing step and/or the UV irradiation step, the diffusion of the soluble conductive element into the interface layer of the first type INT1 makes it possible to obtain the interface layer of the second type INT2, comprising the transition metal, the chalcogen element and the soluble conductive element. FIG. 6c schematically illustrates the stack thereby obtained at the end of the thermal annealing step and/or the UV irradiation step.

(66) The second method 400 of manufacturing the CBRAM memory cell 20 according to the second embodiment finally comprises the following steps: depositing, on the interface layer of the second type INT2, the ion source layer ISL, the ion source layer ISL comprising the soluble conductive element; depositing, on the ion source layer ISL, the diffusion barrier DB; depositing, on the diffusion barrier DB, the electrical contact layer CT.

(67) The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.

(68) FIG. 6d schematically illustrates the metal oxide based CBRAM memory cell 20 (identical to the cell 20 of FIG. 5d) according to the second embodiment of the invention, obtained by the manufacturing method 400.