Electric circuit for testing a power-on reset circuit

Abstract

An electric circuit for testing a power-on reset circuit. The electric circuit including a comparator, which is configured to detect an undervoltage for an input voltage to be compared to a reference voltage and to output an output signal, a first noise filter for filtering out noise from the output signal received as a first input signal for a first time period and for outputting a first filtered output signal of a second noise filter for filtering out noise from a second input signal for a second time period, and for outputting a second filtered output signal, and a digital part having an OR gate for the logical linkage of a first filtered output signal and a second filtered output signal for the output of a power-on reset signal.

Claims

1. An electric circuit for testing a power-on reset circuit, comprising: a comparator to detect an undervoltage for an input voltage by comparing the input voltage to a reference voltage, and to output an output signal, wherein the power-on reset circuit includes the comparator; a first noise filter to filter out noise from the output signal received as a first input signal for a first time period and to output a first filtered output signal; a second noise filter to filter out noise from a second input signal for a second time period and to output a second filtered output signal; a digital part including an OR gate for a logical linkage of the first filtered output signal and the second filtered output signal for an output of a power-on reset signal; and a circuit to supply a test signal for the comparator or the second noise filter; wherein the digital part periodically performs a built-in self-test (BIST) during a normal operating mode to test whether the power-on reset circuit is functioning properly, so long as the power-on reset is inactive.

2. The electric circuit as recited in claim 1, wherein test signal is provided as the input voltage at the comparator.

3. The electric circuit as recited in claim 1, wherein the first filtered output signal or a test signal is provided as an input signal at the second noise filter.

4. The electric circuit as recited in claim 1, wherein an analog circuit is provided as the first noise filter and/or as the second noise filter.

5. The electric circuit as recited in claim 1, wherein the comparator and the first noise filter are jointly provided in a component of the electric circuit.

6. The electric circuit as recited in claim 1, wherein the second noise filter is configured to take a configurable filter time into account.

7. The electric circuit as recited in claim 6, wherein the second noise filter has an input for receiving a value for the configurable filter time.

8. The electric circuit as recited in claim 7, wherein the digital part is configured to supply the value for the configurable filter time.

9. The electric circuit as recited in claim 1, wherein the circuit is configured to supply the test signal for the comparator.

10. The electric circuit as recited in claim 1, wherein the circuit is configured to supply the test signal for the second noise filter.

11. The electric circuit as recited in claim 1, wherein the digital part is configured to supply test signals.

12. The electric circuit as recited in claim 1, further comprising: a voltage splitter to supply an adapted supply voltage from a supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments of the present invention are described in greater detail based on the figures and the description below.

(2) FIG. 1 shows an exemplary embodiment of a circuit according to the present invention for an error detection and for testing a power-on reset circuit.

(3) FIG. 2 shows signal characteristics of a power-on phase as well as a built-in self-test phase according to the circuit of the present invention.

(4) FIG. 3 shows a further exemplary embodiment of a circuit according to the present invention for an error detection and for testing a power-on reset circuit.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(5) FIG. 1 shows an exemplary embodiment of a circuit according to the present invention or a circuit for an error detection and for testing a power-on reset circuit PoR according to the present invention. Power-on reset circuit PoR is made up of an analog undervoltage comparator COMP.sub.UV, which compares input voltage V.sub.IN with a known band gap reference voltage V.sub.REF. Depending on whether input voltage V.sub.IN lies below or above reference voltage V.sub.REF, the level at output UV.sub.FLAG of comparator COMP.sub.UV is set to low or high. A low level at output UV.sub.FLAG indicates that supply voltage V.sub.DD lies below the minimum level required for a proper function of digital part D and other load circuits. A high level at output UV.sub.FLAG means that supply voltage V.sub.DD lies above the minimum level required for a proper function of the circuits.

(6) The level at output UV.sub.FLAG of comparator COMP.sub.UV is conveyed to a first filter NF.sub.1 having a falling edge, which filters out the noise of the supply voltage for a definable time period T1. This means that first noise filter NF.sub.1 changes its output state UV.sub.NF1 from a high level to a low level only if comparator COMP.sub.UV detects an undervoltage of supply voltage V.sub.DD and keeps output UV.sub.FLAG at the low level for a minimum period of T.sub.1. When output UV.sub.FLAG changes from a low level to a high level, noise filter NF.sub.1 also immediately sets its output UV.sub.NF1 to a high level, without any filter delay. Filter .sub.NF1 is therefore applied only to the falling edge of UV.sub.FLAG.

(7) In addition, the output of filter NF.sub.1 is conveyed to second filter NF.sub.2 having a falling edge as input V.sub.IN,NF2, which filters out the input noise for a time period of T.sub.2. This means that second noise filter NF.sub.2 changes its output state UV.sub.NF2 from a high level to a low level only if its input V.sub.IN,NF2 is kept at a low level for a minimum period of T.sub.2. If V.sub.IN,NF2 changes from a low level to a high level, noise filter NF.sub.2 also immediately sets its output UV.sub.NF2 to a high level. Filter NF.sub.2 is thus applied only to a falling edge of V.sub.IN,NF2. The two outputs UV.sub.NF1 and UV.sub.NF2 of the noise filters are then conveyed to digital part D, which generates the power-on reset signal UV.sub.POR by combining the two outputs using an OR gate. Both noise filters NF.sub.1 and NF.sub.2 are implemented using analog circuits.

(8) FIG. 2 shows signal characteristics for a power-on phase as well as a built-in self-test phase (BIST phase) of an ASIC equipped with the circuit according to the present invention. During the startup of supply voltage V.sub.D, shown on the left in FIG. 2, comparator COMP.sub.UV sets its output UV.sub.FLAG to a low level as long as voltage V.sub.IN applied at the input is smaller than the reference value of reference voltage V.sub.REF. In the meantime, outputs UV.sub.NF1 and UV.sub.NF2 of noise filters NF.sub.1 and NF.sub.2 as well as power-on reset signal UV.sub.POR are set to a low level with the result that digital part D and the load circuits are set to the reset state.

(9) As soon as input voltage V.sub.IN crosses reference voltage v.sub.REF, the signal characteristics for the outputs UV.sub.FLAG, UV.sub.NF1, UV.sub.NF2 and power-on reset signal UV.sub.POR reach a high level. The setting of output UV.sub.POR to a high level enables the reset or the reset signal, and digital part D is able to begin with the startup of the different load circuits and also with setting the ASIC to the normal operating mode.

(10) In the event that input voltage V.sub.IN drops below reference value V.sub.REF for a time period T>(T.sub.1+T.sub.2) during the normal operation of the ASIC, outputs UV.sub.FLAG followed by UV.sub.NF1, UV.sub.NF2 and UV.sub.POR are all set to a low level in order to indicate an undervoltage at V.sub.DD. The setting of UV.sub.POR to a low level puts digital part D and the ASIC into the reset state. On the other hand, if an undervoltage exists in supply voltage V.sub.DD for a time period T<=(T1+T2), then signal UV.sub.POR is not set to a low level because the brief undervoltage is filtered out by the combined filter time of the two noise filters NF.sub.1 and NF.sub.2 and the ASIC continues operating in the normal mode. As long as the power-on reset is inactive, that is to say, signal UV.sub.POR is at a high level, digital logic D is able to periodically perform a simple BIST during the normal operating mode in order to check whether the power-on reset circuit PoR is functioning properly. In addition, it can be verified in this way that no internal defects are present between the input and the output of the power-on reset circuit PoR.

(11) Whether filter time period T.sub.1 may be greater or smaller than filter time period T.sub.2 is determined by the employed semiconductor technology and the design of power-on reset circuit PoR. Additional test signals are provided in order to test the functionality of the power-on reset circuit POR during the BIST phase by digital part D. Signal UV.sub.TEST_COMP induces an undervoltage at input V.sub.IN of comparator COMP.sub.UV in order to set the value for UV.sub.FLAG in the BIST to a low level. In a similar manner, signal UV.sub.TEST_NF2 stimulates a low level input V.sub.IN_NF2 of filter NF.sub.2 in order to set its output UV.sub.NF2 to a low level in the BIST.

(12) FIG. 2 furthermore shows the BIST, which is carried out in two phases and during which the functionality of comparator COMP.sub.UV and of noise filter NF.sub.1 is tested to begin with. Next, the functionality of noise filter NF.sub.2 is tested. On the left, FIG. 2 shows the signal characteristics during the BIST phases BIST1 and BIST2 in a normal operation without an undervoltage and/or defects in the circuit, followed by the BIST phases BIST1.sub.UV and BIST2.sub.UV, illustrated in the center, during an undervoltage, and the BIST phases BIST1.sub.D and BIST2.sub.D shown on the right with a defect in the power-on reset circuit. The BIST phase begins as soon as both outputs UV.sub.NF1 and UV.sub.NF2 of noise filters NF.sub.1 and NF.sub.2 are at a high level.

(13) In the first BIST phases BIST1, BIST1.sub.UV, BIST1.sub.D, the path from input V.sub.IN of comparator COMP.sub.UV to output UV.sub.NF1 of first noise filter NF.sub.1 is tested to check its functionality. This is done by setting signal UV.sub.TEST_COMP to a high level for a time period T.sub.1<T<(T.sub.1+T.sub.2). Under this condition, undervoltage comparator COMP.sub.UV immediately sets it output UV.sub.FLAG to a low level. First noise filter NF.sub.1 detects that its input is set to a low level and therefore filters the low input level for a time period of T.sub.1. After a time T.sub.1, noise filter NF.sub.1 sets its output UV.sub.NF1 to a low level. Digital part D actively monitors signal UV.sub.NF1 for changes in its states. It detects the low output of the level and removes the pulse by setting output signal UV.sub.TEST_COMP to a low level. When removing the pulse, undervoltage comparator COMP.sub.UV sets its output UV.sub.FLAG to a high level. First noise filter NF.sub.1, which receives a high level at its input, also immediately sets its output UV.sub.NF1 to a high level. As a result, the digital logic or digital part D expects a high output at output UV.sub.NF1 in first BIST phase BIST1, followed by a low output and then followed by a high output, as illustrated on the left in FIG. 2.

(14) If output UV.sub.NF1 does not change its state on account of a defect in undervoltage comparator COMP.sub.UV or in first noise filter NF.sub.1, as shown on the right in phase BIST1.sub.D of FIG. 2, then this is detected by digital logic D during the BIST phase, and corrective measures are able to be taken by initiating the deactivation of the ASIC, for instance.

(15) If input V.sub.IN of comparator COMP.sub.UV is stimulated for a time period that is smaller than entire filter period T.sub.1+T.sub.2 of the two noise filters NF.sub.1 and NF.sub.2, then the output of second noise filter NF.sub.2 always retains a high output and does not change its state.

(16) In second BIST phases BIST2, BIST2.sub.UV, BIST2.sub.D, the path from input V.sub.IN-NF2 of second noise filter NF.sub.2 to its output UV.sub.NF2 is tested to check its functionality. This is done by setting signal UV.sub.TEST_NF2 to a high level for a time period T>T.sub.2. Under this condition, second noise filter NF.sub.2 detects that its input level is low and therefore filters the low input level for a time period of T.sub.2. After a time T.sub.2, noise filter NF.sub.2 sets its output UV.sub.NF2 to a low level. Digital logic D actively monitors signal UV.sub.NF2 for changes in its states. It detects the low output level and removes the pulse by setting UV.sub.TEST_NF2 to a low level. When removing the pulse, second noise filter NF.sub.2, which samples a high signal level at its input, also immediately sets its output UV.sub.NF1 to a high level. Digital logic D therefore expects a high level at output UV.sub.NF2 in the second BIST phase, followed by a low level and then followed by a high level, as illustrated in the phase BIST2 on the left in FIG. 2. If output UV.sub.NF2 does not change its state because of an existing defect in second noise filter NF.sub.2, as illustrated in phase BIST2.sub.D on the right in FIG. 2, then this is detected by digital part D during the second BIST phase so that corrective measures are able to be taken such as the deactivation of the ASIC.

(17) While a pulse is present at filter input V.sub.IN_NF2 of filter NF.sub.2, output UV.sub.NF1 of first noise filter NF.sub.1 is unaffected and consequently always retains a high output level without changing its state. Since the power-on reset signal is generated by the two outputs UV.sub.NF1 and UV.sub.NF2 of noise filters NF.sub.1 and NF.sub.2 and at least one of the noise filter outputs always has a high level in both BIST phases BIST1 and BIST2, the ASIC continues to operate in the normal way without transitioning to the reset state. In the two BIST phases, the entire path from the input to the output of the power-on reset circuit PoR is tested to check its functionality and the presence of any defects. An additional advantage of the described procedure is that in the event of a defect in digital part D, which causes the BIST pulse to be applied for a longer period than the one described above, the worst reaction that may occur is the output of a power-on reset signal, which sets the ASIC and the digital part to the reset state. The advantage of the circuit according to the present invention is that it continues to operate in the normal manner even during the BIST phase. This manifests itself in the way in which BIST signals are applied and removed. Since the entire stimulation of the BIST signals UV.sub.TEST_COMP and UV.sub.TEST_NF2 takes place within a period that is smaller than filter time T1+T2 of the power-on reset circuit PoR, power-on reset signal UV.sub.POR does not change its state. The UV.sub.POR signal changes its state from a high to a low state during the BIST phase only if an undervoltage is already present or if it occurs in parallel with the BIST pulse. This means that comparator COMP.sub.UV remains at a low level at its output UV.sub.FLAG even after pulse UV.sub.TEST_COMP has been removed.

(18) If, for instance, as shown in the center under BIST1.sub.UV in FIG. 2, input voltage V.sub.IN drops below reference voltage V.sub.REF during the first BIST phase, UV.sub.FLAG and thus also UV.sub.NF1 keep their states at a low level even after pulse UV.sub.TEST_COMP has been removed. If the undervoltage event exists in such a way that second noise filter input V.sub.IN_NF2 of filter .sub.NF2 is kept at a low value for a period that is greater than T.sub.2, then second noise filter output UV.sub.NF2 and finally also the power-on reset signal UV.sub.POR are likewise set to a low level. Digital part D then assumes the reset state.

(19) In a similar manner, if input voltage V.sub.IN drops below reference voltage V.sub.REF in the second BIST phase, as shown in the center under BIST2.sub.UV in FIG. 2, output UV.sub.NF1 of first noise filter NF.sub.1 is adjusted from a high to a low level after a period of T.sub.1. When pulse UV.sub.TEST_NF2 is removed, second noise filter NF.sub.2 continues to detect a low level at its input and thus retains a low level at its output UV.sub.NF2. Depending on whether the undervoltage event is present before or after the start of the second BIST phase, the power-on reset signal UV.sub.POR is adjusted to low after a minimum time of T.sub.1. It is therefore understood that the BIST for the power-on reset circuit PoR does not interfere with the normal operation because power-on reset circuit PoR is able to trigger a reset as long as the undervoltage event in supply voltage V.sub.DD lasts for at least T>(T1+T2) in the first BIST phase or during a normal operation, and for at least T>T1 in the second BIST phase.

(20) FIG. 3 shows an alternative embodiment of the present invention according to an exemplary embodiment, in which the circuit includes a configurable filter time for second noise filter NF.sub.2 for applications in which filter period T.sub.1+T.sub.2 of the power-on reset signal has to be very small. In such a configurable mode, the noise filter period of second noise filter NF.sub.2 is able to be increased from T.sub.2 to T.sub.3, where T.sub.3>T.sub.2 during the first BIST phase. As a result, power-on reset signal UV.sub.POR is set to a low level during the first BIST phase only if an undervoltage is present for a time greater than T.sub.1+T.sub.3. In addition, power-on reset signal UV.sub.POR is set to a low level during the normal mode only if the undervoltage event exists for a period of T.sub.1+T.sub.2, where (T.sub.1+T.sub.2)<(T.sub.1+T.sub.3). Depending on the circuit configuration, first noise filter NF.sub.1 may be integrated into undervoltage comparator COMP.sub.UV.