Controlled current manipulation for regenerative charging of gate capacitance

Abstract

A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.

Claims

1. A method for regenerative gate charging, the method comprising: holding, by an output control circuit, one or more of a plurality of switches of a bridged inductor driver circuit in an ON state for a first time period in accordance with a first switch timing profile of a first switching cycle, the first switch timing profile being determined prior to the first switching cycle, the bridged inductor driver circuit being coupled to a first terminal of an inductor and a second terminal of the inductor, the second terminal of the inductor being coupled to a gate node of a field effect transistor (FET) to control the FET; holding, by the output control circuit, all of the plurality of switches in an OFF state for a second time period in accordance with the first switch timing profile of the first switching cycle, the second time period beginning after an expiration of the first time period; sampling one or more first voltages of the gate node during the second time period; generating, by a timing control circuit, a second switch timing profile for a second switching cycle using the one or more sampled first voltages; holding, by the output control circuit, the one or more of the plurality of switches of the bridged inductor driver circuit in the ON state for a third time period in accordance with the second switch timing profile of the second switching cycle; and holding, by the output control circuit, all of the plurality of switches in the OFF state for a fourth time period in accordance with the second switch timing profile of the second switching cycle; wherein: the first time period and the second time period are determined by a plurality of adjustable delay circuits, respective first adjustable delay values of the plurality of adjustable delay circuits being in accordance with the first switch timing profile during the first switching cycle; and the third time period and the fourth time period are determined by the plurality of adjustable delay circuits, respective second adjustable delay values of the plurality of adjustable delay circuits being in accordance with the second switch timing profile during the second switching cycle.

2. The method of claim 1, further comprising: retrieving, by a digital configuration circuit before the first switching cycle, a default switch timing profile; and using, by the digital configuration circuit, the default switch timing profile as the first switch timing profile.

3. The method of claim 1, wherein: the first time period and the second time period are determined by a plurality of static delay circuits in addition to the plurality of adjustable delay circuits; and the third time period and the fourth time period are determined by the plurality of static delay circuits in addition to the plurality of adjustable delay circuits.

4. The method of claim 1, wherein: during a charging sequence of the gate node of the FET, the method further comprises: turning off, by the output control circuit, a first switch of the plurality of switches at a first time during the second switching cycle, the first switch having a first high-side node coupled to the second terminal of the inductor, a first output control node coupled to the output control circuit, and a first low-side node coupled to a first voltage node of the bridged inductor driver circuit; turning on, by the output control circuit, a second switch of the plurality of switches at a second time during the second switching cycle, the second switch having a second high-side node coupled to a second voltage node of the bridged inductor driver circuit, a second output control node coupled to the output control circuit, and a second low-side node coupled to the first terminal of the inductor; turning off, by the output control circuit, the second switch at a third time during the second switching cycle; turning on, by the output control circuit, a third switch of the plurality of switches at a fourth time during the second switching cycle, the third switch having a third high-side node coupled to the first terminal of the inductor, a third output control node coupled to the output control circuit, and a third low-side node coupled to the first voltage node; turning off, by the output control circuit, the third switch at a fifth time during the second switching cycle; and turning on, by the output control circuit, a fourth switch of the plurality of switches at a sixth time during the second switching cycle, the fourth switch having a fourth high-side node coupled to the second voltage node, a fourth output control node coupled to the output control circuit, and a fourth low-side node coupled to the second terminal of the inductor.

5. The method of claim 4, wherein: the sixth time occurs after the fifth time, the fifth time occurs after the fourth time, the fourth time occurs after the third time, and the third time occurs after the second time; and the method further comprises: sampling one or more second voltages of the gate node after the fifth time and before the sixth time; and generating, by the timing control circuit, a third switch timing profile of a third switching cycle using the one or more sampled second voltages.

6. The method of claim 5, wherein the first time occurs before the second time.

7. The method of claim 5, wherein the first time occurs after the second time and before the third time.

8. The method of claim 5, wherein: the timing control circuit receives a first FET control signal at a trigger time of the first switching cycle; the first time and the second time occur at about the trigger time; and the method further comprises: offsetting each of the third time, the fourth time, the fifth time and the sixth time in time from the trigger time based on respective adjustable delays, each of the respective adjustable delays having a static delay portion and a tunable delay portion.

9. The method of claim 4, wherein: during a discharging sequence of the gate node, the method further comprises: turning off, by the output control circuit, the fourth switch at a seventh time during the second switching cycle; turning on, by the output control circuit, the third switch at an eighth time during the second switching cycle; turning off, by the output control circuit, the third switch at a ninth time during the second switching cycle; turning on, by the output control circuit, the second switch at a tenth time during the second switching cycle; turning off, by the output control circuit, the second switch at an eleventh time during the second switching cycle; and turning on, by the output control circuit, the first switch on at a twelfth time during the second switching cycle; and the seventh time, the eighth time, the ninth time, the tenth time, the eleventh time, and the twelfth time are in accordance with the second switch timing profile.

10. The method of claim 9, wherein: the twelfth time occurs after the eleventh time, the eleventh time occurs after the tenth time, the tenth time occurs after the ninth time, and the ninth time occurs after the eighth time; and the method further comprises: sampling one or more second voltages of the gate node of the FET after the eleventh time and before the twelfth time; and generating, by the timing control circuit, a third switch timing profile of a third switching cycle using the one or more sampled second voltages.

11. The method of claim 10, wherein the seventh time occurs before the eighth time.

12. The method of claim 10, wherein the seventh time occurs after the eighth time and before the ninth time.

13. The method of claim 10, wherein: the timing control circuit receives a first FET control signal at a trigger time of the first switching cycle; the first time and the second time occur at about the trigger time; and the method further comprises: offsetting each of the third time, the fourth time, the fifth time and the sixth time in time from the trigger time based on respective adjustable delays, each of the respective adjustable delays having a static delay portion and a tunable delay portion.

14. A circuit for regenerative gate charging, the circuit comprising: an inductor having a first terminal and a second terminal, the second terminal being configured to be coupled to a gate node of a field effect transistor (FET); a bridged inductor driver circuit being configured to be coupled to the first terminal of the inductor and the second terminal of the inductor, the bridged inductor driver circuit comprising a plurality of switches; an output control circuit coupled to the bridged inductor driver circuit; a sense circuit configured to be coupled to the gate node; a timing control circuit coupled to the output control circuit and the sense circuit; and a plurality of adjustable delay circuits coupled to the timing control circuit; wherein: the output control circuit holds one or more of the plurality of switches in an ON state for a first time period of a first switching cycle using first output control signals, the first time period being in accordance with a first switch timing profile, and the first switch timing profile being determined prior to the first switching cycle; the output control circuit holds all of the plurality of switches in an OFF state for a second time period of the first switching cycle, the second time period being in accordance with the first switch timing profile and beginning after an expiration of the first time period; the sense circuit samples one or more first voltages of the gate node during the second time period; the timing control circuit uses the one or more sampled first voltages to generate a second switch timing profile for a second switching cycle; the output control circuit holds one or more of the plurality of switches in the ON state for a third time period of the second switching cycle using second output control signals, the third time period being in accordance with the second switch timing profile; the output control circuit holds all of the plurality of switches in the OFF state for a fourth time period of the second switching cycle, the fourth time period being in accordance with the second switch timing profile; the first output control signals are generated during the first switching cycle using the plurality of adjustable delay circuits; the first time period and the second time period are determined by the plurality of adjustable delay circuits; respective first adjustable delay values of the plurality of adjustable delay circuits are in accordance with the first switch timing profile during the first switching cycle; the second output control signals are generated during the second switching cycle using the plurality of adjustable delay circuits; the third time period and the fourth time period are determined by the plurality of adjustable delay circuits; and respective second adjustable delay values of the plurality of adjustable delay circuits are in accordance with the second switch timing profile during the second switching cycle.

15. The circuit of claim 14, wherein: the timing control circuit generates the second output control signals during the second switching cycle in accordance with the second switch timing profile; and the timing control circuit transmits the second output control signals to the output control circuit during the second switching cycle.

16. The circuit of claim 14, further comprising: a digital configuration circuit, the digital configuration circuit comprising: a switch timing profile retrieval circuit; wherein: the switch timing profile retrieval circuit retrieves a default switch timing profile; and the default switch timing profile is used as the first switch timing profile.

17. The circuit of claim 14, further comprising: a plurality of static delay circuits coupled to the timing control circuit; wherein: the first output control signals are generated during the first switching cycle using the plurality of static delay circuits in addition to the plurality of adjustable delay circuits; and the second output control signals are generated during the second switching cycle using the plurality of static delay circuits in addition to the plurality of adjustable delay circuits.

18. The circuit of claim 14, wherein the bridged inductor driver circuit comprises: a first voltage node; a second voltage node; a first switch having a first high-side node coupled to the second terminal of the inductor, a first output control node coupled to the output control circuit, and a first low-side node coupled to the first voltage node; a second switch having a second high-side node coupled to the second voltage node, a second output control node coupled to the output control circuit, and a second low-side node coupled to the first terminal of the inductor; a third switch having a third high-side node coupled to the first terminal of the inductor, a third output control node coupled to the output control circuit, and a third low-side node coupled to the first voltage node; and a fourth switch having a fourth high-side node coupled to the second voltage node, a fourth output control node coupled to the output control circuit, and a fourth low-side node coupled to the second terminal of the inductor.

19. The circuit of claim 14, wherein: the timing control circuit receives a first FET control signal at a trigger time of the first switching cycle; the timing control circuit generates the first output control signals in accordance with the first switch timing profile; and the timing control circuit transmits the first output control signals to the output control circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified schematic of an example synchronous switching power converter circuit, in accordance with some embodiments.

(2) FIG. 2 is a simplified schematic of an example circuit for regenerative charging of gate capacitance, in accordance with some embodiments.

(3) FIG. 3A is a simplified signal timing diagram.

(4) FIG. 3B is a simplified schematic of a portion of an example output control circuit, in accordance with some embodiments.

(5) FIG. 3C is a simplified signal timing diagram.

(6) FIGS. 4A-B are simplified signal timing diagrams.

(7) FIGS. 5A-B are simplified signal timing diagrams.

(8) FIG. 6 is a simplified schematic of a portion of an example signal processing circuit, in accordance with some embodiments.

(9) FIGS. 7A-C are simplified schematics of a portion of an example signal processing circuit, in accordance with some embodiments.

(10) FIGS. 8A-B are simplified schematics of example bridged inductor driver circuits, in accordance with some embodiments.

(11) FIGS. 9A-B are simplified schematics of example control circuits, in accordance with some embodiments.

DETAILED DESCRIPTION

(12) Improved methods and circuits are described herein for controlled current manipulation for regenerative charging of gate capacitance. Large field effect transistors (e.g., power FETs) such as those used in synchronous switching power converter circuits require significant gate charge that is consumed from the supply rail on every switching cycle. If part of the energy used for charging and discharging the gate is recovered during a switching cycle, energy losses are reduced, and efficiency is improved. As described herein, this energy recovery can be achieved by transferring energy to and from the gate using an inductor. In some embodiments, the inductor and associated control circuitry are implemented in an integrated driver along with the FET as the timing of the control signals for operating the inductor can then be very accurately controlled. The improvement of the timing controls enables the advantage of ensuring optimal charging and discharging of gate capacitance for improved power consumption or minimization of power loss. Additionally, the inductor may be integrated on the same die or in the same package as the FET, which further enhances the advantages enabled by the accurate timing controls for the inductor. Other advantages or improvements of the methods and circuits described herein will also become apparent from the present disclosure.

(13) In some embodiments, such methods and circuits involve circuits for charging and discharging a gate of a FET by controlling the current flow through an inductor coupled to the gate of the FET such that power loss is reduced. Such circuits accept input from a switched-mode controller and switch the FET on and off as determined by a desired duty cycle of the switching power converter. Current flow through the inductor and to the gate of the FET is controlled by a switch timing profile that has static and tunable delay portions. The tunable delay portions of the switch timing profile are adjusted to further reduce power loss in subsequent switching cycles by sampling the gate voltage of the FET at a known time in a charge or discharge cycle of the gate of the FET. The sampled gate voltages are compared to desired voltages as a form of feedback regarding the previous gate charge or discharge cycle. Based on that feedback, the adjustable delay portions of the switch timing profile are tuned (e.g., a delay duration is lengthened or shortened) to modify current flow through the inductor during a subsequent gate charge or discharge cycle.

(14) FIG. 1 is a simplified schematic of an example synchronous switching power converter (“converter”) circuit 100 that converts an input voltage V.sub.IN at a V.sub.IN node to an output voltage V.sub.OUT at a V.sub.OUT node, in accordance with some embodiments. In general, the converter circuit 100 includes a control circuit 104 that is coupled to a high-side field effect transistor (FET) 106 through a high-side drive circuit 108. The control circuit 104 is also coupled to a low-side FET 110 through a low-side drive circuit 112. A high-side source node of the high-side FET 106 and a low-side drain node of the low-side FET 110 are electrically coupled to the phase node 114, which is electrically coupled to a capacitor 116 through an inductor 118. A phase signal PH is a static or continuously changing voltage at the phase node 114. The control circuit 104 is electrically coupled to the phase node 114 to receive the phase signal PH. A load, such as a load 120, is typically electrically coupled in parallel with the capacitor 116. In some embodiments, the control circuit 104 is electrically coupled to the V.sub.OUT node (e.g., through a feedback path to receive V.sub.OUT). The control circuit 104 receives V.sub.OUT and the phase signal PH and may receive other signals which are not shown here for simplicity. The control circuit 104 outputs a signal H.sub.ON and a signal L.sub.ON. The high-side drive circuit 108 receives the H.sub.ON signal. The high-side drive circuit 108 buffers, amplifies, level-shifts, or otherwise conditions the signal H.sub.ON to produce a signal H.sub.DRV that is suitable for turning the high-side FET 106 on and off. The signal H.sub.DRV is received at a high-side gate node of the high-side FET 106. Similarly, the low-side drive circuit 112 receives the signal L.sub.ON. The low-side drive circuit 112 buffers, amplifies, level-shifts, or otherwise conditions the signal L.sub.ON to produce a signal L.sub.DRV that is suitable for turning the low-side FET 110 on and off. The signal L.sub.DRV is received at a gate node of the low-side FET 110. In some embodiments, the low-side drive circuit 112 receives external control signals from the control circuit 104.

(15) FIG. 2 is a simplified schematic of an example low-side drive circuit 112 for regenerative charging of gate capacitance of the low-side FET 110. The portion of the low-side drive circuit 112 shown includes a timing control circuit 208 that receives the L.sub.ON signal and triggers a series of events, timed by timer circuits 214.sub.1-N. The timer circuits 214.sub.1-N include static delay circuits and adjustable delay circuits to provide static delays, as well as to provide variable (e.g., tunable) delays which are controlled by a configuration provided by the timing control circuit 208. The low-side drive circuit 112 also includes a control loop that adjusts the variable delays based on feedback from previous gate charge/discharge cycles. The initial state of the low-side drive circuit 112 is set, in some embodiments, by a digital configuration circuit 210, which sources configuration data signals Cfg.sub.1-3 either from a non-volatile source, or an external supervising controller. The timing control circuit 208 outputs a sequence of timed pulses to an output control circuit 204 which contains combinational logic that converts the timed pulses into gate waveforms, and buffers these signals to control current flow through an inductor L.sub.1 that is coupled to the gate of the low-side FET 110 to charge or discharge the gate of the low-side FET 110. After the gate of the low-side FET 110 has finished charging or discharging, but the corresponding hold switch (or current source) is not enabled, a signal processing circuit 206 samples the gate voltage of the low-side FET 110 to generate the feedback to the timer control circuit 208 about the performance of the previous cycle.

(16) As shown, the low-side drive circuit 112 generally includes the inductor L.sub.1 coupled to the gate node of the low-side FET 110. A bridged inductor driver circuit 202 is coupled to the inductor L.sub.1 and to the output control circuit 204. The signal processing circuit 206 is coupled to the gate node of the low-side FET 110. The timing control circuit 208 is coupled to the timer circuits 214.sub.1-N, to the output control circuit 204, to the signal processing circuit 206, and to the digital configuration circuit 210. The digital configuration circuit 210 includes a non-volatile memory (NVM) circuit 212.

(17) In the example embodiment shown, the bridged inductor driver circuit 202 includes switches S.sub.1-4. Other embodiments of the bridged inductor driver circuit 202 are shown and discussed with reference to FIGS. 8A-9B. The timing control circuit 208 receives the signal L.sub.ON from the control circuit 104 and based on that signal turns the low-side FET 110 on or off by charging the gate of the low-side FET 110 up to Vdd or discharging the gate of the low-side FET 110 down to Vss. To turn the low-side FET 110 on or off, the timing control circuit 208, triggered by the signal L.sub.ON, generates output control signals (“Output Ctrl”) and transmits the Output Ctrl signals to the output control circuit 204. The output control circuit 204 uses the Output Ctrl signals to control the bridged inductor driver circuit 202 to cause current to flow to and from the inductor L.sub.1 and the gate node of the low-side FET 110. In the example shown, the flow of current is caused by turning one or more of the switches S.sub.1-4 on or off for a duration of time. In some embodiments, one or more of the switches S.sub.1-4 is a FET. In other embodiments, one or more of the switches S.sub.1-4 is a controlled current source or a diode.

(18) The Output Ctrl signals sent to the output control circuit 204 are generated by the timing control circuit 208 in accordance with a switch timing profile. A switch timing profile is a timing sequence that defines or controls the flow of current to and from the inductor L.sub.1 and the gate node of the low-side FET 110. Example timing sequences are shown and discussed with reference to FIGS. 4A-5B. In some embodiments, switch timing profiles are stored in, and retrieved from, the digital configuration circuit 210 (e.g., using the NVM circuit 212). A default switch timing profile may be used while the converter circuit 100 reaches a steady state of operation on power-up or after reset.

(19) During specific times during a switching cycle, measurements of the voltage and/or current related to the low-side FET 110 are made by the signal processing circuit 206. A switching cycle is a duration of time in which both FETs 106, 110 have transitioned through full on and off states (e.g., the sequence of turning low-side FET 110 off . . . high-side FET 106 on . . . high-side FET 106 off . . . low-side FET 110 on . . . low-side FET 110 off . . . and so on). In the example shown the voltage V.sub.G of the gate node of the low-side FET 110 is measured by the signal processing circuit 206, but in other embodiments, other currents/voltages related to the low-side FET 110 are measured as well. These example embodiments are shown and discussed with reference to FIGS. 7A-C. Based on measurements made during the current switching cycle, the switch timing profile used in a subsequent switching cycle is created or updated (e.g., tuned). When the timing control circuit 208 receives a second FET control signal at a second trigger time of a subsequent switching cycle, the timing control circuit 208 generates output control signals in accordance with the updated or generated switch timing profile (based on measured gate voltages from the previous cycle) and transmits updated output control signals to the output control circuit 204. The created or updated switch timing profile can be stored by the digital configuration circuit 210 (e.g., by transmitting configuration signals Cfg.sub.4 from the timing control circuit 208 to the digital configuration circuit 210) and be recalled by the digital configuration circuit 210 for later use. An example embodiment of a portion of the signal processing circuit 206 is shown and discussed with reference to FIG. 6.

(20) Upon, or before, receiving the FET control signal L.sub.ON during a switching cycle (or upon or before the commencement of that switching cycle), the timing control circuit 208 configures the timer circuits 214.sub.1-N using respective control signals Ctrl.sub.1-N in accordance with a switch timing profile associated with that switching cycle. The switch timing profile used to configure the timer circuits 214.sub.1-N is either generated/updated in a previous switching cycle or is retrieved (e.g., from the NVM circuit 212) by the digital configuration circuit 210.

(21) In accordance with the switch timing profile, each of the timer circuits 214.sub.1-N is configured to apply an amount of static and/or adjustable delay to received trigger signals Trig.sub.1-N to produce delayed signals T.sub.1-N. In some embodiments, each of the trigger signals Trig.sub.1-N corresponds to the signal L.sub.ON. The Output Ctrl signals transmitted from the timing control circuit 208 to the output control circuit 204 include the delayed signals T.sub.1-N. An example simplified signal timing diagram 300 in FIG. 3A shows the delayed signal T.sub.N generated by the timer circuit 214.sub.N as it relates to the trigger signal Trig.sub.N received by the timer circuit 214.sub.N. After a first untriggered duration of time (“Untriggered.sub.1”), a rising edge 302 of a trigger signal Trig.sub.N (e.g., Trig.sub.3) is sent from the timing control circuit 208 to the timer circuit 214.sub.N. After a first static delay duration (“Static Delay.sub.1”) and a first tunable delay duration (“Tunable Delay.sub.1”), a delayed rising edge 304 of delayed signal T.sub.N (e.g., T.sub.3) is transmitted from the timer circuit 214.sub.N to the timing control circuit 208. After a second untriggered duration of time (“Untriggered.sub.2”), a falling edge 306 of the trigger signal Trig.sub.N is transmitted from the timing control circuit 208 to the timer circuit 214.sub.N. After a second static delay duration (“Static Delay.sub.2”) and a second tunable delay duration (“Tunable Delay.sub.2”), a delayed falling edge 308 of T.sub.N is transmitted from the timer circuit 214.sub.N to the timing control circuit 208. The timer circuit 214.sub.N remains untriggered for a second duration of time (“Untriggered.sub.2”).

(22) The timing control circuit 208 transmits T.sub.N, as well as other delayed signals (e.g., T.sub.1, T.sub.2) to the output control circuit 204 as part of the Output Ctrl signals. The output control circuit 204 uses the received Output Ctrl signals to generate signals that control the bridged inductor driver circuit 202, thereby controlling the flow of current through the inductor L.sub.1 and to/from the gate node of the low-side FET 110. A portion of an example embodiment of the output control circuit 204 is shown in FIG. 3B.

(23) The portion of the circuit shown in FIG. 3B illustrates the logical relationship between inputs and outputs of the output control circuit 204. The output control circuit 204 converts delayed signals T.sub.1-3 received by the output control circuit 204 into signals S.sub.1-4 Out. Logic gates G.sub.1-12, coupled as shown, use delayed signals T.sub.1-3 and the trigger signal L.sub.ON to produce switch control signals S.sub.1-4 Out. The switch control signals S.sub.1-4 Out are used to control the bridged inductor driver circuit 202. In some embodiments, the signals S.sub.1-4 Out are buffered, level-shifted, amplified, or otherwise modified to control the bridged inductor driver circuit 202. In some embodiments, one or more of the switch control signals S.sub.1-4 Out control a controllable current supply circuit. Details of the logical relationship of L.sub.ON and T.sub.1-3 to S.sub.1-4 Out, given the example embodiment of the output control circuit 204 shown in FIG. 3B, are shown in the simplified signal diagram 350 of FIG. 3C.

(24) A simplified signal timing diagram 400 of an example 3-stage timing sequence for charging the gate node of the low-side FET 110 (e.g., turning the low-side FET 110 on) is shown in FIG. 4A. Based on the currently used timing profile of the current switching cycle, the timer circuits 214.sub.1-N shown in FIG. 2 are configured to produced delayed signals T.sub.1-3 which are received by the output control circuit 204 to generate switch control signals S.sub.1-4 Out. During a pre-trigger stage, while L.sub.ON is de-asserted (e.g., the low-side FET 110 is off), signal S.sub.1 Out is asserted, and signals S.sub.2-4 Out are de-asserted, thus holding the gate node of the low-side FET 110 at Vss. During the pre-trigger stage, the magnitude of current I.sub.L through the inductor L.sub.1 is zero. After the pre-trigger stage, a rising edge 402 of L.sub.ON is received at the timing control circuit 208 from the control circuit 104 which triggers subsequent transitions of signals S.sub.1-4 Out. The falling edge 404 of signal S.sub.1 Out and the rising edge 406 of signal S.sub.2 Out cause a rising magnitude of current I.sub.L to flow into the inductor L.sub.1 from Vdd. After a duration of time that includes both static and tunable delays (e.g., the static delay.sub.1 and tunable delay.sub.1 stages of FIG. 3A), the falling edge 408 of S.sub.2 Out and the rising edge 410 of S.sub.3 Out cause current sourced from Vdd and the inductor L.sub.1 to charge the low-side gate of the low-side FET 110. As the gate voltage V.sub.G rises, the magnitude of current I.sub.L falls. After another duration of time that includes both static and tunable delays (e.g., the static delay.sub.2 and tunable delay.sub.2 stages of FIG. 3A), the falling edge 412 of S.sub.3 Out and the rising edge 414 of S.sub.4 Out cause the low-side gate of the low-side FET 110 to be held at V.sub.dd (designated as the “Holding” stage). As shown, the signal processing circuit 206 only samples the gate voltage V.sub.G during the duration of time between the falling edge 412 and the rising edge 414 (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop (e.g., a “loop” formed as the effects of Output Ctrl on the gate voltage V.sub.G measured by the signal processing circuit 206 at specific times, the sampled voltages being fed back to the timing control circuit 208 to generate new Output Ctrl signals, and so on). The control loop adjusts switch timing profiles used during future cycles (e.g., tuning the tunable delay portions for use in a subsequent switching cycle). During this duration of time, current is not being provided to the gate node of the low-side FET 110 from Vdd and current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit 202 are off). Because the gate voltage V.sub.G is only sampled during this duration of time, the signal processing circuit 206 can be advantageously simplified.

(25) A simplified signal timing diagram 450 of an example 4-stage timing sequence for charging the gate node of the low-side FET 110 (e.g., turning the low-side FET 110 on) is shown in FIG. 4B. The 4-stage timing sequence adds a pre-charge stage to the 3-stage timing sequence discussed with reference to FIG. 4A. During a pre-trigger stage while L.sub.ON is de-asserted, signal S.sub.1 Out is asserted, and signals S.sub.2-4 Out are de-asserted, thus holding the gate node of the low-side FET 110 at Vss. During the pre-trigger stage, the magnitude of current I.sub.L through the inductor L.sub.1 is zero. After the pre-trigger stage, a rising edge 452 of L.sub.ON is received at the timing control circuit 208 from the control circuit 104, the reception of which triggers subsequent transitions of signals S.sub.1-4 Out. A rising edge 454 of S.sub.2 Out causes a rising magnitude of current I.sub.L to flow through the inductor L.sub.1 from Vdd to Vss. A falling edge 456 of signal S.sub.1 Out causes the current I.sub.L to cease flowing to Vss and instead begin charging the gate node of the low-side FET 110. This causes a rising gate voltage V.sub.G. After a duration of time that includes both static and tunable delays, a falling edge 458 of signal S.sub.2 Out and a rising edge 460 of signal S.sub.3 Out stops the flow of current from Vdd to the inductor L.sub.1. Current I.sub.L from the inductor L.sub.1 continues to flow to the gate node of the low-side FET 110. This causes the gate voltage V.sub.G of the FET 110 to continue rising while the magnitude of the current I.sub.L falls. After another duration of time that includes both static and tunable delays, the falling edge 462 of S.sub.3 Out and the rising edge 464 of S.sub.4 Out cause the low-side gate of the low-side FET 110 to be held at V.sub.dd (designated as the “Holding” stage). As shown, the signal processing circuit 206 only samples the gate voltage V.sub.G during the duration of time between the falling edge 462 and the rising edge 464 (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current is not being provided to the gate node of the low-side FET 110 from Vdd and current from the gate node is not being sourced to Vss.

(26) A simplified signal timing diagram 500 of an example 3-stage timing sequence for discharging the gate node of the low-side FET 110 (e.g., turning the low-side FET 110 off) is shown in FIG. 5A. Based on the currently used timing profile of the current switching cycle, the timer circuits 214.sub.1-N shown in FIG. 2 are configured to produced delayed signals T.sub.1-3 which are received by the output control circuit 204 to generate switch control signals S.sub.1-4 Out. During a pre-trigger stage while L.sub.ON is asserted (e.g., the low-side FET 110 is on), signal S.sub.4 Out is asserted, and signals S.sub.1-3 Out are de-asserted, thus holding the gate node of the low-side FET 110 at Vdd. During the pre-trigger stage, the magnitude of current I.sub.L through the inductor L.sub.1 is zero. After the pre-trigger stage, a falling edge 502 of L.sub.ON is received at the timing control circuit 208 from the control circuit 104, the reception of which triggers subsequent transitions of signals S.sub.1-4 Out. The rising edge 504 of signal S.sub.3 Out and the falling edge 506 of signal S.sub.4 Out cause a rising magnitude (e.g., away from the steady-state of zero current) of current I.sub.L to flow into the inductor L.sub.1 from the gate node of the low-side FET 110, thereby causing the gate voltage V.sub.G to decrease. After a duration of time that includes both static and tunable delays (e.g., the static delay.sub.1 and tunable delay.sub.1 stages of FIG. 3A), a rising edge 508 of S.sub.2 Out and a falling edge 510 of S.sub.3 Out causes current to flow through the inductor L.sub.1 to Vdd. As the gate voltage V.sub.G continues to decrease, the magnitude of current I.sub.L falls (e.g., returning to a steady state of zero). After another duration of time that includes both static and tunable delays (e.g., the static delay.sub.2 and tunable delay.sub.2 stages of FIG. 3A), the falling edge 512 of S.sub.2 Out and the rising edge 514 of S.sub.1 Out cause the low-side gate of the low-side FET 110 to be held at Vss (designated as the “Holding” stage). As shown, the signal processing circuit 206 only samples the gate voltage V.sub.G during the duration of time between the falling edge 512 and the rising edge 514 (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit 202 are off). Because the gate voltage V.sub.G is only sampled during this duration of time, the signal processing circuit 206 can be advantageously simplified.

(27) A simplified signal timing diagram 550 of an example 4-stage timing sequence for discharging the gate node of the low-side FET 110 (e.g., turning the low-side FET 110 off) is shown in FIG. 5B. The 4-stage timing sequence adds a Pre-charge stage to the 3-stage timing sequence discussed with reference to FIG. 5A. During a pre-trigger stage while L.sub.ON is asserted, signal S.sub.4 Out is asserted, and signals S.sub.1-3 Out are de-asserted, thus holding the gate node of the low-side FET 110 at Vdd. During the pre-trigger stage, the magnitude of current I.sub.L through the inductor L.sub.1 is zero. After the pre-trigger stage, a falling edge 552 of L.sub.ON is received at the timing control circuit 208 from the control circuit 104, the reception of which triggers subsequent transitions of signals S.sub.1-4 Out. A rising edge 554 of S.sub.3 Out causes a rising magnitude (e.g., away from the steady-state of zero current) of current I.sub.L to flow through the inductor L.sub.1 from Vdd to Vss. A falling edge 556 of signal S.sub.4 Out causes the current I.sub.L to cease flowing to Vdd and continue flowing from the gate node of the low-side FET 110 to Vss. This causes a decreasing gate voltage V.sub.G. After a duration of time that includes both static and tunable delays, a rising edge 558 of signal S.sub.2 Out and a falling edge 560 of signal S.sub.3 Out causes causes current to flow through the inductor L.sub.1 to Vdd. This causes the gate voltage V.sub.G of the FET 110 to continue falling while the magnitude of the current I.sub.L also falls (e.g., approaches the steady-state of zero current). After another duration of time that includes both static and tunable delays, the falling edge 562 of S.sub.2 Out and the rising edge 564 of S.sub.1 Out cause the low-side gate of the low-side FET 110 to be held at Vss (designated as the “Holding” stage). As shown, the signal processing circuit 206 only samples the gate voltage V.sub.G during the duration of time between the falling edge 562 of S.sub.2 Out and the rising edge 564 of S.sub.1 Out (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit 202 are off). Because the gate voltage V.sub.G is only sampled during this duration of time, the signal processing circuit 206 can be advantageously simplified.

(28) A circuit schematic of an example embodiment of a portion of the signal processing circuit 206 is shown in FIG. 6. Other embodiments of a signal processing circuit for sampling a gate voltage of a FET as are known in the art could be used in some embodiments. In some embodiments, the signal processing circuit 206 includes a digital-to-analog converter instead of, or in addition to, high-speed latching comparators. In the example embodiment shown, the signal processing circuit 206 generally includes a first high-speed latching comparator 602 and a second high-speed latching comparator 604 coupled as shown in FIG. 6. The first comparator 602 receives the gate voltage V.sub.G from the gate node of the low-side FET 110 at a non-inverting input and receives Vdd at an inverting input to compare the gate voltage Vg to the rail-voltage Vdd. The second comparator 604 receives the gate voltage V.sub.G from the gate node of the low-side FET 110 at an inverting input and receives Vss at a non-inverting input to compare the gate voltage Vg to the rail-voltage Vss. Outputs of the comparators 602, 604 (Vdd Feedback and Vss Feedback, respectively) are transmitted to the timing control circuit 208 as part of the “Smp” signals shown in FIG. 2. Additionally, the comparators 602, 604 can receive trigger signals (not shown) and/or reset signals from the timing control circuit 208 as part of the “Trig” signals shown in FIG. 2 to control the reset and subsequent sample latching of the comparators 602, 604. As was discussed with reference to FIGS. 4A-5B, the signal processing circuit 206 advantageously samples the gate voltage only during select times of the switching cycle.

(29) In some embodiments, other voltages and currents related to the low-side FET 110 are measured in addition to the gate voltage V.sub.G. Example embodiments of a portion of the signal processing section of the low-side drive circuit 112 are shown in FIGS. 7A-C. Each of the signal processing sections 700, 720 and 750 are coupled to the low-side FET 110 and generally include a respective signal processing circuit 706, 726, 756 which is similar to the signal processing circuit 206. Samples produced by the signal processing circuits 706, 726, 756 are transmitted to the timing control circuit 208 as part of the Smp signals shown in FIG. 2. Additionally, trigger signals are transmitted from the timing control circuit 208 to a respective signal processing circuit 706, 726, 756 as part of the Trig signals shown in FIG. 2. Configuration signals Cfg.sub.3 are received the signal processing circuits 706, 726, 756 from the digital configuration circuit 210. As shown in FIG. 7A, in some embodiments, a gate current I.sub.G and the gate voltage V.sub.G of the gate node of the low-side FET are sampled by the signal processing circuit 706 for zero-current-switching. As shown in FIG. 7B, in some embodiments, the gate voltage V.sub.G of the gate node and a drain current I.sub.D of a low-side drain node of the low-side FET are sampled by the signal processing circuit 726 for zero-current-switching. As shown in FIG. 7C, in some embodiments, the gate voltage V.sub.G of the gate node and a drain voltage V.sub.D of the low-side drain node of the low-side FET are sampled by the signal processing circuit 756 for zero-voltage-switching.

(30) Other example embodiments of the bridged inductor driver circuit 202 of FIG. 2 are shown in FIGS. 8A-B. As shown in the simplified circuit schematic of FIG. 8A, one or more of the switches S.sub.1-4 shown in FIG. 2 are replaced, in some embodiments, by a controllable current source I.sub.2-4 to control the flow of current through the inductor L.sub.1. As shown in the simplified circuit schematic of FIG. 8B, the switch S.sub.3 shown in FIG. 2 is replaced, in some embodiments, by a diode D.sub.1.

(31) The inductance of the inductor L.sub.1 and bridged inductor driver circuits may be distributed amongst a distributed power FET, in accordance with some embodiments. As shown in the simplified circuit schematics of FIGS. 9A-B, in some embodiments, the low-side FET 110 includes N fingers 910.sub.1-N. In such embodiments, the inductance of the inductor L.sub.1 is distributed across the N fingers 910.sub.1-N as inductors L1.sub.1-N. Similarly, the bridged inductor driver circuit 202 is distributed across the N fingers as bridged inductor driver circuits 902.sub.1-N, the distributed bridged inductor driver circuits 902.sub.1-N having, in some embodiments, switches S1.sub.1-N, S2.sub.1-N, S3.sub.1-N, and S4.sub.1-N. In some embodiments, as shown in the simplified circuit schematic 900 of FIG. 9A, the output control circuit 204 is also distributed across the N fingers as output control circuits 904.sub.1-N. As shown in the simplified circuit schematic 950 of FIG. 9B, in some embodiments, a single output control circuit 954 is coupled to each of the distributed bridged inductor driver circuits 902.sub.1-N.

(32) In some embodiments, the high-side drive circuit 108 is similar to the low-side drive circuit 112 and is used for regenerative charging of gate capacitance of the high-side FET 106. In some embodiments, the static delay portions are set at design time and are dependent on the specific switch and inductor sizes used. In some embodiments, a monolithic integration of the low-side FET 110, the bridged inductor driver circuit 202 and the circuitry of the low-side drive circuit 112 occur on a mixed signal LDMOS process node. In some embodiments, the low-side FET 110 is a large NMOS device. In some embodiments, all or a portion of the low-side drive circuit 112 includes analog circuits rather than digital circuits. In some embodiments, a single inductor is shared amongst many power FETs (e.g., a single inductor L.sub.1 coupled to respective gate nodes of multiple FETs), such as in a multi-phase design. In some embodiments, the inductor L.sub.1 is constructed with bond wires on top of a chip that includes the low-side drive circuit 112. In some embodiments, the inductor L.sub.1 is constructed as a traditional planar spiral inductor. In some embodiments, the inductor L.sub.1 is constructed using metal layers or a redistribution layer (RDL). In some embodiments, the inductor L.sub.1 is external to a chip that includes the low-side drive circuit 112 or forms a part of a multi-component hybrid. In some embodiments, the inductor L.sub.1 is constructed using bond-wires that terminate off a chip that includes the low-side drive circuit 112 such that a spiral is formed away from the chip itself. Any other suitable form of on-chip or off-chip inductor as known to one of skill in the art may be used as the inductor L.sub.1.

(33) For ease of description, example embodiments described herein relate to the low-side FET 110. One of ordinary skill in the art will understand that the same or similar methods and circuits can be used to drive the high-side FET 106 or another FET entirely. In some embodiments, the FET controlled by gate driver circuits described herein is an NMOS or PMOS device. In some embodiments, the low-side drive circuit 112 is only used for charging the gate of the low-side FET 110. In some embodiments, the low-side drive circuit 112 is only used for discharging the low-side FET 110. In some embodiments, regenerative gate charging and discharging is not used during each switching cycle but is still used during some switching cycles. In some embodiments, regenerative gate charging and discharging is used during each switching cycle. In some embodiments, the signal processing circuit 206 continuously samples the gate voltage V.sub.G. In some embodiments, the signal processing circuit 206 uses a Digital-to-Analog Converter instead of a comparator. In some embodiments, the signal processing circuit 206 uses an attained peak gate voltage rather than the final resting voltage for feedback. In some embodiments, analog components of the circuits described herein are replaced with digital inputs. In some embodiments, the Vdd and Vss supplies are separated from the low-voltage system rails, and may dynamically change over operating conditions. In some embodiments, tunable delay timings are controlled by an external system controller. In some embodiments, the configuration is provided by on-chip NVM, from an external source, or from a PWM signal. In some embodiments, the circuits and methods described herein are recursively applied to the switches of the bridged inductor driver circuit 202.

(34) Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.