High power radio frequency (RF) amplifiers

Abstract

A power amplifier having: a plurality of N amplifier modules, where N is an integer greater than one; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; a plurality of M delay lines, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the power amplifier.

Claims

1. A high power RF amplifier circuit comprising: a plurality of N power amplifier, where N is an integer greater than one, each one of the power amplifies having a predetermined phase shift; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; a plurality of M delay lines, each one of the M delay lines having a predetermined phase shift selected from minus twenty degrees to minus 50 degrees, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the high power RF amplifier circuit wherein a combination of the predetermined phase shift of each power amplifier combined with the predetermined phase shift of each one of the M delay lines provides a desirable phase shift as an output for each one of the power amplifiers.

2. The high power RF amplifier circuit recited in claim 1 wherein N is equal to 16 and M is equal to 4.

3. The high power RF amplifier circuit recited in claim 1 including a 1:M power splitter having M outputs, each one of the M outputs being coupled to an input of a corresponding one of the M delay lines.

4. The high power RF amplifier circuit recited in claim 3 wherein the M;N power splitter, the M delay lines, and the 1:M power splitter are disposed on a common printed circuit board.

5. The high power RF amplifier circuit recited in claim 1 wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N/M of the amplifiers, each one of the N/M amplifiers in a corresponding one of the M amplifier module sections having a phase shift (Δ.sub.1+/−δ) degrees through (Δ.sub.M+/−δ) degrees, respectively, and where each one of the M delay lines has a phase shift Δ.sub.1 through Δ.sub.M respectively.

6. The high power RF amplifier circuit recited in claim 5 wherein Δ.sub.1 is equal to minus 20 degrees, Δ.sub.2 is equal to minus 30 degrees, Δ.sub.3 is equal to minus 40 degrees, and Δ.sub.M is equal to minus 50 degrees, respectively.

7. The high power RF amplifier circuit recited in claim 4, wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N/M of the amplifiers, each one of the N/M amplifiers in a corresponding one of the M amplifier module sections having a phase shift (Δ.sub.1+/−δ) degrees through (Δ.sub.M+/−δ) degrees, respectively, and where each one of the M delay lines has a phase shift Δ.sub.1 through Δ.sub.M respectively.

8. A high power RF amplifier circuit comprising: a plurality of N power amplifiers, where N is an integer greater than one, each one of the power amplifiers having a predetermined phase shift wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N/M of the amplifiers, each one of the N/M amplifiers in a corresponding one of the M amplifier module sections having a phase shift (Δ.sub.1+/−δ) degrees through (Δ.sub.M+/−δ) degrees, respectively; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; a plurality of M delay lines, where each one of the M delay lines has a phase shift Δ.sub.1 through Δ.sub.M respectively, each one of the M delay lines having a predetermined phase shift selected from minus twenty degrees to minus 50 degrees, each one of the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the high power RF amplifier combined with the predetermined phase shift of each one of the M delay lines provides a desirable phase shift at an output for each one of the power amplifiers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a high power RF power amplifier according to the PRIOR ART;

(2) FIG. 2 is a is a schematic diagram of a high power RF power amplifier according to the disclosure; and

(3) FIGS. 3A-3E are plan views of an upper surface of a printed circuit board having a 1:M power splitter, M:N power splitter, M delay lines 18.sub.1-18.sub.4, and resistors for use with the the high RF power amplifier of FIG. 2 at various stages in the fabrications thereof.

(4) Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(5) Referring now to FIG. 2, a high power RF amplifier 10 is shown having; a plurality of N amplifiers 12.sub.1-12.sub.N where N is an integer greater than one, here in this example N is sixteen; an M:N power splitter 14 having M inputs 14.sub.1-14.sub.M, where M is an integer less than N, here in this example, M is four, and N outputs 16.sub.1-16.sub.M, each one of the N outputs 16.sub.1-16.sub.M being coupled to an input 14.sub.1-14.sub.M of a corresponding one of the plurality of N amplifiers 12.sub.1-12.sub.N; and, a plurality of M delay lines 18.sub.1-18.sub.M, each one the M delay lines 18.sub.1-18.sub.M having an output T2, T4, T6, and T8, respectively, coupled to a corresponding one of the M inputs 14.sub.1-14.sub.M of the plurality of the M:N power splitter 14, each one of the plurality of M delay lines 18.sub.1-18.sub.M having an input T1, T3, T5 and T7, respectively, being coupled to a common input 20 of the power amplifier 10; here though a 1:N power splitter 22. It is noted that the 1:N power splitter and the M:N power splitter 14 are of conventional design and include conventional matched termination resistors R, here 50 ohms; the microwave transmission lines used to form the power splitters 14 and 22 as well as the and the delay lines 18.sub.1-18.sub.M here being in this example, 50 ohm microstrip transmission lines. Thus, there are, in this example, sixteen channels from the input 20 to a corresponding one of the sixteen outputs OUTPUT 1-OUTPUT 16.

(6) Here, in this example, a plurality of amplifiers is fabricated and the phase shift through each one at the nominal operating frequently is measured and recorded. A predetermined tolerance +/−δ from a predetermined phase shift Δ.sub.1 through Δ.sub.M is selected for each one of the M amplifier module sections 24.sub.1-24.sub.M. Here for example, the predetermined tolerance δ is selected as five degrees and the predetermined phase shift Δ.sub.1 through Δ.sub.M are in this example selected as: Δ.sub.1=20 degrees, Δ.sub.1+10=30 degrees, Δ.sub.1+20=40 degrees and Δ.sub.1+30=50 degrees, for the M amplifier module sections 24.sub.1-24.sub.M respectively.

(7) In this example, sixteen of the fabricated amplifiers are selected having the following phase shifts, in degrees: 16, 17, 22, 24, 26, 31, 34, 35, 36, 37, 42, 44, 48, 49, 52 and 53.

(8) The selected amplifiers are arranged in the M amplifier module sections 24.sub.1-24.sub.M as follows:

(9) TABLE-US-00001 Original Measured Target Phase Delay Line for Effective phase Phase Shift Shift per Amplifier (degrees) per Amplifier (Degrees) channel Module Section output channel Amplifier 12.sub.1 22 0 Degrees Amplifier Module OUTPUT 1 = +2 Module 12.sub.2 17 Section 24.sub.1 OUTPUT 2 = −3 Section 12.sub.3 24 −20 Degrees OUTPUT 3 = +4 24.sub.1 12.sub.4 16 OUTPUT 4 = −4 Amplifier 12.sub.5 26 Amplifier Module OUTPUT 5 = −4 Module 12.sub.6 31 Section 24.sub.2 OUTPUT 6 = 1 Section 12.sub.7 34 −30 Degrees OUTPUT 7 = 4 24.sub.2 12.sub.8 35 OUTPUT 8 = 5 Amplifier 12.sub.9 36 Amplifier Module OUTPUT 9 = 4 Module .sub. 12.sub.10 44 Section 24.sub.3 OUTPUT 10 = 4 Section .sub. 12.sub.11 42 −40 Degrees OUTPUT 11 = 2 24.sub.3 .sub. 12.sub.12 37 OUTPUT 12 = −3 Amplifier .sub. 12.sub.13 48 Amplifier Module OUTPUT 13 = −2 Module .sub. 12.sub.14 53 Section 24.sub.4 OUTPUT 14 = 3 Section .sub. 12.sub.15 52 −50 Degrees OUTPUT 15 = −2 24.sub.4 .sub. 12.sub.16 49 OUTPUT 16 = −1

(10) It is noted that the N amplifiers 12.sub.1-12.sub.16 are arranged in M amplifier module sections 24.sub.1-24.sub.M, each one of the M amplifier module sections 24.sub.1-24.sub.M having N/M (here 4) of the amplifiers 12.sub.1-12.sub.N, each one of the N/M amplifiers 12.sub.1-12.sub.N in a corresponding one of the M amplifier module sections 24.sub.1-24.sub.M having a phase shift (Δ.sub.1+/−δ) degrees through (Δ.sub.M+/−δ) degrees, respectively, and where each one of the M delay lines 18.sub.1-18.sub.M has a phase shift Δ.sub.1 through Δ.sub.M respectively.

(11) It should be noted that the 1:M power splitter 22 and M:N power splitter 14 and the M delay lines 18.sub.1-18.sub.4 are disposed on a common printed circuit board 30 as microstrip microwave transmission lines and also formed on the printed circuit board 30 are the resistors R.

(12) Referring now to FIGS. 3A-3E plan views of various stages in the fabrications of the printed circuit 30 portion of the high RF power amplifier 10 are shown. Thus, shows the 1:M power splitter 22, M:N power splitter 14 and the resistors R. Here the 1:M power splitter 22 and the M:N power splitter 14 are microstrip transmission lines formed by strip conductors 31 formed on the upper surface 33 of a dielectric board 35 and a ground plane conductor, not shown, formed on the bottom surface of the dielectric board 35. One end of the resistors R is connected to the strip conductors 31, as shown, and the other end of the resistors is connected to the ground plane conductor (not shown) through conductive vias VIA, as indicated.

(13) After forming the printed circuit board 30 as in FIG. 3A, the delay lines 18.sub.1-18.sub.4 are formed as microstrip transmission lines; the ground plane being provided by the ground plane (not shown) formed on the back of the dielectric board 35. The strip conductor of the microstrip transmission line for the first delay line 18.sub.1 is printed using additive manufacturing or 3D printing as shown in FIG. 3B.

(14) Next, the strip conductor of the microstrip transmission line for the second delay line 18.sub.2 is printed using additive manufacturing or 3D printing as shown in FIG. 3C.

(15) Next the strip conductor of the microstrip transmission line for the third delay line 18.sub.3 is printed using additive manufacturing or 3D printing as shown in FIG. 3D.

(16) Finally, the strip conductor of the microstrip transmission line for the fourth delay line 18.sub.4 is printed using additive manufacturing or 3D printing as shown in FIG. 3E.

(17) It should be understood that while in the example above the strip conductors of the microstrip transmission line for delay lines 18.sub.1-18.sub.4 have been printed sequentially, they may be printed concurrently using for example a raster type motion for the 3D printing head.

(18) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.