Processing method for applying analog dynamic circuit to digital testing tool

Abstract

A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.

Claims

1. A processing method for applying an analog dynamic circuit to a digital testing tool, the processing method comprising steps of: (a) providing a transistor-level analog dynamic circuit; (b) designing plural equivalent models according to operations of plural transistors in the transistor-level analog dynamic circuit; (c) performing a substitution operation to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit, so that a gate-level substitution circuit is produced; (d) importing the gate-level substitution circuit into a digital testing tool, so that a test pattern is generated; and (e) testing the transistor-level analog dynamic circuit according to the test pattern.

2. The processing method as claimed in claim 1, wherein the digital testing tool is an automatic test pattern generation system.

3. The processing method as claimed in claim 1, wherein the plural equivalent models are stored in a database.

4. The processing method as claimed in claim 1, wherein each equivalent model is designed through a hardware description language.

5. The processing method as claimed in claim 4, wherein the hardware description language is Verilog.

6. The processing method as claimed in claim 5, wherein each equivalent model has a corresponding Verilog code.

7. The processing method as claimed in claim 1, further comprising a step of inputting the test pattern into the transistor-level analog dynamic circuit, and judging whether the generated data of plural internal nodes and at least one output terminal of the transistor-level analog dynamic circuit comply with expected data.

8. The processing method as claimed in claim 7, wherein if the generated data of plural internal nodes and at least one output terminal of the transistor-level analog dynamic circuit comply with the expected data, it is determined that the transistor-level analog dynamic circuit is normally operated, wherein if the generated data of plural internal nodes and at least one output terminal of the transistor-level analog dynamic circuit do not comply with the expected data, it is determined that the transistor-level analog dynamic circuit has design error.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

(2) FIG. 1A (prior art) is a schematic circuit diagram illustrating a static circuit;

(3) FIG. 1B (prior art) is a schematic circuit diagram illustrating a dynamic circuit;

(4) FIG. 2 is a flowchart of a processing method for applying an analog dynamic circuit to a digital testing tool;

(5) FIG. 3A schematically illustrates the circuitry structure of the dynamic XOR gate and the equivalent model;

(6) FIG. 3B schematically illustrates the circuitry structure of the dynamic AND gate and the equivalent model;

(7) FIG. 4A schematically illustrates the circuitry structure of the dynamic NAND gate and the equivalent model;

(8) FIG. 4B schematically illustrates the circuitry structure of the dynamic NOR gate and the equivalent model; and

(9) FIG. 4C schematically illustrates the circuitry structure of the dynamic AOI gate and the equivalent model.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(10) As mentioned above, the conventional analog dynamic circuit cannot be applied to the digital testing tools. For overcoming the drawbacks of the conventional technologies, the present invention provides a processing method for applying an analog dynamic circuit to a digital testing tool.

(11) In accordance with the processing method of the present invention, an equivalent model is provided to replace the dynamic logic elements in the analog dynamic circuit. Consequently, the analog dynamic circuit can be represented by the gate level. Moreover, the analog dynamic circuit can be imported into the digital testing tool to generate test patterns. During the process of testing the analog dynamic circuit, the test patterns can be applied to the analog dynamic circuit to increase the test coverage.

(12) FIG. 2 is a flowchart of a processing method for applying an analog dynamic circuit to a digital testing tool. After the analog dynamic circuit is designed, the processing method starts. Firstly, a transistor-level analog dynamic circuit is provided (Step S202).

(13) Then, equivalent models are designed according to the operations of plural transistors in the analog dynamic circuit (Step S204). Since the analog dynamic circuit uses transistors to form various dynamic logic elements, each equivalent model can be designed for each dynamic logic element. In an embodiment, a hardware description language (HDL) is used to design the equivalent models. For example, the hardware description language Verilog is used to convert the function of a dynamic logic element into a gate-level equivalent model.

(14) Then, a substitution operation is performed to substitute the equivalent models for the dynamic logic elements in the analog dynamic circuit, and a gate-level substitution circuit is produced (Step S206). That is, after the substitution operation is completed, the equivalent models are substituted for the corresponding dynamic logic elements in the analog dynamic circuit. Consequently, the analog dynamic circuit becomes a gate-level substitution circuit.

(15) Then, the gate-level substitution circuit is imported into a digital testing tool to generate test patterns (Step S208). That is, the gate-level substitution circuit is imported into the ATPG system, and the test patterns for the input terminal, the output terminal and all internal nodes of the gate-level substitution circuit are generated.

(16) After the test patterns are generated, the test patterns can be used to test the transistor-level analog dynamic circuit (Step S210). During the testing process, the test patterns are inputted into the transistor-level analog dynamic circuit, and the ATPG system judges whether the generated data of the internal nodes and the output terminal of the transistor-level analog dynamic circuit comply with the expected data. If the judging condition is satisfied, the ATPG system determines that the analog dynamic circuit is normally operated. Whereas, if the judging condition is not satisfied, the ATPG system determines that a design error of the analog dynamic circuit is generated.

(17) By using the processing method of the present invention, the transistor-level analog dynamic circuit can be converted into the gate-level substitution circuit. After the transistor-level analog dynamic circuit is converted into the gate-level substitution circuit, the gate-level substitution circuit can be smoothly imported into the ATPG system. Consequently, the test patterns generated by the ATPG system have good test coverage for the analog dynamic circuit.

(18) For example, the processing method of the present invention is applied to the dynamic circuit as shown in FIG. 1B. The dynamic circuit is a one-bit dynamic half adder. The dynamic half adder 120 is a transistor-level analog dynamic circuit. The dynamic half adder 120 comprises the transistors a1˜a8, the transistors b1˜b6 and the transistor c1. The transistors a1˜a8 and the transistor c1 are combined as a dynamic XOR gate. The transistors b1˜b6 and the transistor c1 are combined as dynamic AND gate.

(19) FIG. 3A schematically illustrates the circuitry structure of the dynamic XOR gate and the equivalent model. As shown in FIG. 3A, the function of the dynamic XOR gate is further converted into the equivalent model of the dynamic XOR gate through the Verilog code. That is, the equivalent model of the dynamic XOR gate can be expressed as:

(20) //equivalent model XOR

(21) if CLK=0

(22) S=1

(23) if CLK=1

(24) S=(not (A) and (B)) or ((A) and not (B))

(25) FIG. 3B schematically illustrates the circuitry structure of the dynamic AND gate and the equivalent model. As shown in FIG. 3B, the function of the dynamic AND gate is further converted into the equivalent model of the dynamic AND gate through the Verilog code. That is, the equivalent model of the dynamic AND gate can be expressed as:

(26) //equivalent model AND

(27) if CLK=0

(28) C=1

(29) if CLK=1

(30) C=(A and B)

(31) After the equivalent models are completed, the substitution operation is performed to substitute the equivalent model for the dynamic XOR gate and the dynamic AND gate of the one-bit dynamic half adder. Consequently, the one-bit dynamic half adder represented by the gate level is produced.

(32) Then, the gate-level one-bit dynamic half adder is imported into the ATPG system, and the test patterns for the input terminal, the output terminal and all internal nodes of the analog dynamic circuit are generated. After the test patterns are generated, the test patterns can be used to test the one-bit dynamic half adder.

(33) In addition to the dynamic XOR gate and the dynamic AND gate, the equivalent models corresponding to various dynamic logic elements can be previously stored in a database. While the substitution operation of the analog dynamic circuit is performed, the corresponding equivalent model is directly acquired from the database. Hereinafter, the equivalent models corresponding to some other dynamic logic elements will be described with reference to FIGS. 4A, 4B and 4C.

(34) FIG. 4A schematically illustrates the circuitry structure of the dynamic NAND gate and the equivalent model. As shown in FIG. 4A, the function of the dynamic NAND gate is further converted into the equivalent model of the dynamic NAND gate. That is, the equivalent model of the dynamic NAND gate can be expressed as:

(35) //equivalent model NAND

(36) if CLK=0

(37) OUT=1

(38) if CLK=1

(39) OUT=not (A and B)

(40) FIG. 4B schematically illustrates the circuitry structure of the dynamic NOR gate and the equivalent model. As shown in FIG. 4B, the function of the dynamic NOR gate is further converted into the equivalent model of the dynamic NOR gate. That is, the equivalent model of the dynamic NOR gate can be expressed as:

(41) //equivalent model NOR

(42) if CLK=0

(43) OUT=1

(44) if CLK=1

(45) OUT=not (A or B)

(46) Alternatively, the dynamic logic element is a dynamic and-or-inverter (AOI) gate. FIG. 4C schematically illustrates the circuitry structure of the dynamic AOI gate and the equivalent model. As shown in FIG. 4C, the function of the dynamic AOI gate is further converted into the equivalent model of the dynamic AOI gate. That is, the equivalent model of the dynamic AOI gate can be expressed as

(47) //equivalent model AOI

(48) if CLK=0

(49) OUT=1

(50) if CLK=1

(51) OUT=not (A and (B or C))

(52) The examples of the equivalent models corresponding to various dynamic logic elements are not restricted. That is, the equivalent models corresponding to various dynamic logic elements may be varied according to the practical requirements. Each equivalent model has the corresponding Verilog. Moreover, each equivalent model is stored in the database.

(53) From the above descriptions, the present invention provides a processing method for applying an analog dynamic circuit to a digital testing tool. By using the processing method of the present invention, the transistor-level analog dynamic circuit can be converted into the gate-level substitution circuit. After the transistor-level analog dynamic circuit is converted into the gate-level substitution circuit, the gate-level substitution circuit can be smoothly imported into the ATPG system. Consequently, the test patterns generated by the ATPG system have good test coverage for the analog dynamic circuit.

(54) While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.