BOTTOM-PINNED MAGNETIC RANDOM ACCESS MEMORY HAVING A COMPOSITE SOT STRUCTURE

Abstract

An ultra-fast magnetic random access memory (MRAM) comprises a three terminal bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element including (counting from top to bottom) a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such bCSOT-MTJ element will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

Claims

1. A bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element comprises a seed layer (SL) provided on a bottom-electrode (BE) VIA substrate; a magnetic pinning stack (MPS) provided on the top surface of said SL having magnetic anisotropy in a film plane and having an invariable magnetization direction; a tunnel barrier (TB) layer provided on the top surface of said MPS; a magnetic memory (MM) layer provided on the top surface of said TB and having magnetic anisotropy in a film plane and having a variable magnetization direction; a composite SOT (CSOT) stack comprising a spin Hall channel (SHC) layer provided on the top surface of said MM layer and a magnetic flux guiding (MFG) layer on top surface of said SHC or wrapping around said SHC;

2. The element of claim 1, wherein said MFG layer is made of a soft magnetic material having a very high magnetic permeability and comprising at least one element selected from the group of Ni, Fe, Co, and preferred to be selected from the group of NiFe, CoFe, NiCo and CoNiFe, or the group of NiFe, CoFe, Co, NiCo and CoNiFe doped with 0-30% of B, Si, Mo, Cr, Nb, Ta, Hf and having a thickness between 1.5-10 nm.

3. The element of claim 1, wherein said SHC is made of a material having a large positive spin Hall angle, preferred to comprise (Au, Pt, Ir, Ag, Pd or Cu) doped with 5-15% (Ta, W, Hf or Bi), and having an electric resistivity lower than the electric resistivity of said MFG and having a thickness between 1.5-10 nm.

4. The element of claim 1, wherein said MM is made of a soft magnetic single layer or multilayer having a magnetic anisotropy in a direction in the film surface and having a variable magnetization direction; and comprising at least one element selected from the group of Co, Fe, Ni and B, preferred to be selected from CoFeB, FeB, Fe/CoFeB, CoFe/CoFeB, CoFeB/CoFe with a total thickness between 1.5-5 nm or a multilayer CoFeB(1-2 nm)/(W or Mo)(0.2-0.6 nm)/CoFeB(0.5-3 nm).

5. The element of claim 1, wherein said TB is made of an oxide layer MgO or MgZnO with a thickness between 0.7-2 nm.

6. The element of claim 1, wherein said MPS is a multilayer stack having magnetic anisotropy in a film plane and having an invariable magnetization direction and comprising a magnetic reference layer Co/CoFeB, Co/FeB, CoFe/CoFeB or CoFe/FeB, a RKKY coupling layer Ru, Rh or Ir, a pinned layer Co or CoFe and an antiferromagnetic material layer selected from PtMn, PtPdMn, NiMn, IrMn, RhMn, RuMn; and a preferred MPS is PtMn(5-20 nm)/CoFe(2-5 nm)/Ru(0.4-0.85 nm)/CoFe(1-1.5 nm)/CoFeB(1-2 nm).

7. The element of claim 1, wherein said bCSOT-MTJ element contains a three-terminal electric circuit after connecting with a first top electrode (TE1) provided on a first side of said CSOT stack and said TE1 is connected a transistor to control spin current flow in said SHC during memory writing; a second top electrode (TE2) provided on a second side of said CSOT stack and said TE2 is connected to either a transistor or grounded; a bottom electrode (BE) provided at the bottom surface of said SL and said BE is connected to either a diode or transistor to control STT current flow from BE to TE2 during memory reading or writing.

8. The element of claim 1, wherein writing of a low resistance (parallel) state in said MM is done by passing through a spin current flowing from said TE1 to TE2, and a high resistance (anti-parallel) state in said MM layer is done by passing a spin current flowing from said TE2 to TE1 while leaving said BE open.

9. The element of claim 8, wherein writing of both low (parallel) resistance state and high (anti-parallel) resistance state in said MM is done by a spin orbit torque (SOT) and a Lorentz force generated by current-flowing-wire (CFW) in said SHC layer at both MM/SHC and SHC/MFG interfaces, and further enhanced by a close magnetic flux loop at the cross-section between said MM/SHC/MFG tri-layer.

10. The element of claim 1, wherein writing of a low (parallel) resistance state in said MM is done by passing through a spin current flowing from TE1 to TE2, and a current flowing from said BE up through the entire MTJ film stack to TE2 simultaneously, and a high resistance (anti-parallel) state in said MM layer is done by passing a spin current from TE2 to TE1 and spin current flowing from BE up through the entire MTJ stack to TE2 simultaneously.

11. The element of claim 10, wherein writing of low resistance state and high resistance state in said MM is done by three forces: SOT and Lorentz force generated by current-flow-wire (CFW) in said SHC layer at both MM/SHC and SHC/MFG interfaces, and STT generated by a current vertically up flow through the MTJ stack to said TE2, and further enhanced by a close magnetic flux loop at the cross-section between said MM/SHC/MFG tri-layer which significantly reduces magnetic impedance for said MM layer during switching.

12. The element of claim 1, wherein reading of magnetic state in said MM layer is done by passing through a current flowing from bottom electrode (BE) up through the entire MTJ stack to TE2 while leaving the transistor connecting with TE1 open, wherein control of current flow is done either by a transistor or diode connecting to said BE.

13. A method of manufacturing a bottom-pinned composite SOT magnetic tunneling junction (CSOT-MTJ) element comprising: deposit a SOT-MTJ stack including a seed layer(SL), magnetic pinning stack (MPS), a tunnel barrier (TB) layer, a magnetic memory (MM) layer, a spin Hall channel (SHC) layer; anneal said SOT-MTJ stack; pattern said SOT-MTJ stack; etch said SOT-MTJ stack; deposit SiN protection layer around etch-exposed COS-MTJ surface and refill with SiO2 dielectrics; chemical mechanical polish (CMP) to remove excess SiO2 & SiN until said SHC layer is exposed; form a composite SOT (CSOT) channel on the top surface of said patterned/etched SOT-MTJ.

14. The element of claim 13, wherein said SOT-MTJ element is annealed at a temperature between 350-400 C for 30-150 min in the presence of an in-plane magnetic field with a strength between 1-5Tesla aligning (canted) at an angle ca ranging between 10 to 90 degree in the X-Y plane, said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

15. The element of claim 13, wherein said SOT-MTJ element is photo-lithographically patterned into an oval shape with an aspect ratio of 1.5-3 for its long/short (a/b) axes, and with its long a (magnetic easy) axis pointing (canted) at an angle ca ranging between 10 to 90 degree in the X-Y plane, said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

16. The element of claim 13, wherein said patterned SOT-MTJ element is etched and stopped on said bottom seed layer (SL) either by reactive ion etch (RIE or ion-beam etch or combination of both.

17. The element of claim 13, wherein said SiN protection layer with a thickness of 30-50 nm is deposited in-situ to cover the exposed SOT-MTJ surface right after etching, then refill SiO2 dielectrics with a thickness thicker than the etched portion of said SOT-MTJ stack.

18. The element of claim 13, wherein the formation of said composite SOT (CSOT) channel comprises deposit additional SHC material on the exposed SHC surface to seamlessly merge them together form a complete spin Hall current channel and continue to deposit a said MFG layer on top of said SHC layer; pattern and etch said SHC/MFG film stack to form a composite SOT (CSOT) current flow stripe on top surface of patterned magnetic memory layer; form top electrodes (TE1 and TE2) on top of said CSOT stripe.

19. The element of claim 13, wherein the formation of said composite SOT (CSOT) channel comprises deposit additional SHC material on the exposed SHC surface to seamlessly merge them together form a complete spin Hall current channel; pattern and etch said SHC layer to form a SOT spin current flow stripe on top surface of patterned magnetic memory layer; deposit MFG film around the exposed SHC stripe (top surface two vertical edge); pattern and etch said MFG in a similar way as said patterning of said SHC layer and form a complete composite SOT (CSOT) channel with SHC/MFG bi-layer; form top electrodes (TE1 and TE2) on top surfaces of said CSOT stripe.

20. The element of claim 1, wherein said bCSOT-MTJ element will have a fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 Cross section view (in X-direction) of a finished bottom-pinned bCSOT-MTJ with two top electrodes (TE1 and TE2) and one bottom electrode (BE).

[0014] FIG. 2 Film structure of said bCSOT-MTJ stack after deposition.

[0015] FIG. 3 Canted magnetic annealing (Han) to preset the pinning direction for the MTJ stack at an angle ca in X-Y plane.

[0016] FIG. 4 Patterning of said bCSOT-MTJ element with an oval shape to preset its long axis aligning at an angle ca in X-Y plane.

[0017] FIG. 5A Cross section view of said bottom-pinned bCSOT-MTJ fabrication showing the SOT-MTJ stack is patterned and etched all through the MTJ stack.

[0018] FIG. 5B Cross section view of said bottom-pinned bCSOT-MTJ fabrication showing the SOT-MTJ stack is patterned and etched half way and stopped at MgO.

[0019] FIG. 5C Cross section view of said bottom-pinned bCSOT-MTJ fabrication showing the SiN protection layer and SiO.sub.2 dielectrics are deposited to fill the etched open area.

[0020] FIG. 5D Cross section view of said bottom-pinned bCSOT-MTJ fabrication showing a CMP is used to open the remaining SHC.

[0021] FIG. 5E Cross section view of said bottom-pinned bCSOT-MTJ fabrication showing more SHC material is added and a MFG is deposited on SHC.

[0022] FIG. 5F Cross section view of the patterned and etched SHC and MFG bi-layer in Y-direction.

[0023] FIG. 5G Cross section view of the patterned and etched SHC and MFG layers with MFG wrapping around the SHC.

[0024] FIG. 6A Illustration of magnetic flux for the memory layer with a MFG layer to cover the SHC, the magnetic flux in MM layer 16 forms a close loop without a MFG layer.

[0025] FIG. 6B Illustration of a diverging magnetic flux outside the memory layer without a MFG layer.

[0026] FIG. 7 A Illustration of magnetic memory writing when a current passing through the SHC layer flowing from TE1 to TE2 to writes the memory layer to a low resistance state.

[0027] FIG. 7B Illustration of magnetic memory writing when a current passing through the SHC layer flowing from TE2 to TE1 to writes the memory layer to a high resistance state,

[0028] FIG. 7C Illustration of magnetic memory writing when a current passing through the SHC layer showing the two forces (SOT, CFW) simultaneously acting on the memory layer for a the case shown in FIG. 7A.

[0029] FIG. 8A Illustration of magnetic memory writing with one current laterally flowing through the SHC and another current perpendicularly flowing up from the MTJ stack to write to a low resistance state.

[0030] FIG. 8B Illustration of magnetic memory writing showing three forces simultaneously acting on the memory layer to switch its magnetic state.

[0031] FIG. 9 Current flow from bottom electrode (BE) through the MTJ to TE2 during memory reading.

DETAILED DESCRIPTION OF THE INVENTION

[0032] The disclosed three terminal bottom-pinned composite SOT magnetic random access memory (bCSOT-MRAM) comprises a film element of (see FIG. 1) (counting from device bottom to top) a seed layer 10, a magnetic pinning stack (MPS) (layer 11-14), a tunnel barrier (TB) 15, a magnetic memory layer (MM) 16, a composite SOT (CSOT) stack and including a spin Hall channel (SHC) layer 17 and a magnetic flux guiding (MFG) layer 21, and said film element after patterning and etching is protected by a SiN 19 layer layer and SiO.sub.2 dielectrics 20 and electrically connected to two top electrodes TE1 and TE2 which are located respectively at first and second side of said CSOT stack and one bottom electrode (BE). The TE1 is further connected to a transistor and TE2 is normally grounded while BE is either conned to a diode or a transistor.

[0033] Above said seed layer 10 is made of a Ta, W, Zr or Hf with a thickness between 2-8 nm which in addition to provide a seed for the growth of said MPS but also act as etching stop during etching process.

[0034] Above said magnetic pinning stack (MPS) is a multilayer stack having magnetic anisotropy in a film plane and having an invariable magnetization direction and comprising a an antiferromagnetic material 11 selected from PtMn, PtPdMn, NiMn, IrMn, RhMn, RuMn, a pinned magnetic layer 12 made of Co or CoFe, a RKKY coupling layer 13 made of Ru, Rh or Ir and a reference layer 14 made of Co/CoFeB, Co/FeB, CoFe/CoFeB or CoFe/FeB, and a preferred MPS layer stack is PtMn(5-20 nm)/CoFe(2-5 nm)/Ru(0.4-0.85 nm)/CoFe(1-1.5 nm)/CoFeB(1-2 nm).

[0035] Above said tunnel barrier (TB) layer 15 is made of an oxide selected from MgO or MgZnO with a thickness between 1-2 nm. As compared with the MTJ stack used in pSTT-MTAM, in this MTJ stack, a thicker TB can be used to ensure a good device reliability because the write current does not go through the MTJ stack.

[0036] Above said magnetic memory (MM) layer 16 is made of a soft magnetic single layer or multilayer having a magnetic anisotropy in a direction in the film surface and having a variable magnetization direction; and comprising a material selected from CoFeB, FeB, Fe/CoFeB, CoFe/CoFeB, CoFeB/CoFe with a total thickness between 1.5-5 nm or a multilayer CoFeB(1-2 nm)/(W or Mo)(0.2-0.6 nm)/CoFeB(0.5-3 nm).

[0037] Above said spin Hall channel (SHC) 17 is made of a material having a large positive spin Hall angle, preferred to be selected from the group of (Au, Pt, Ir, Ag, Pd or Cu) doped with 5-15% (Ta, W, Hf or Bi), and having an electric resistivity lower than the electric resistivity of said MFG and having a thickness between 1.5-10 nm. Although beta phase Ta and W have a negative large spin Hall angle, the negative spin torque generated will be counter-balanced partially by a Lorentz force generated by the current-flowing wire (CFW) in the SHC layer which will provide a weaker spin torque for memory layer switch. Au-based alloy with Ta or W impurities has an additional advantage with a much lower resistivity (less than 85 μohm.Math.cm) than most SHC materials.

[0038] In above said MFG layer 21 is made of a soft magnetic material having a very high magnetic permeability and comprising at least one element selected from the group of Ni, Fe, Co, and preferred to be selected from the group of NiFe, CoFe, NiCo and CoNiFe, or the group of NiFe, CoFe, NiCo, Co and CoNiFe doped with 0-30% of B, Si, Mo, Cr, Nb, Ta, Hf, and having a thickness between 1.5-10 nm. For example, its magnetic permeability is about 1000 or a half of that of Permalloy (Ni81Fe19) and its magnetostriction lamda is also very small (−2.6×10.sup.−6) while the resistivity of CoNbHf thin film layer is readily larger than 125 μohm.Math.cm, which is larger than that of a SHC made of Au doped with 10% Ta. In this case, most electrical current flows inside the SHC 17, and the accumulation of one type of polarized spins near the top surface of the SHC 17 caused by SHE would also diffuse into the MFG layer 21. This would further lead to not only magnetization rotation of the MFG layer but also more accumulation of the other type of polarized spins near the bottom surface of the SHC 17, both of which would help the switching of the magnetization in the MM layer.

[0039] Fabrication of above said bCSOT-MRAM device is illustrated in a process flow chart which starts on a BE-VIA substrate, deposition of a bottom-pinned bCSOT MTJ film stack 100 as shown in FIG. 2 including seed layer 10/MPS (11-14)/TB(15)/MM(16)/SHC(17) and capped with Ta or W hard mask layer 18. After film deposition, the above said bCSOT-MTJ stack is annealed at a high temperature between 350-400 C for 30-120 minutes in the presence of a high magnetic field Han (1-5Tesla) to preset an initial aligning direction for the entire film stack. The field direction can be canted at an angle ca (10-90 degree) within the X-Y plane (see FIG. 3) which is needed to avoid using an external magnetic field during memory switching.

[0040] The wafer with a bCSOT-MTJ film stack is then photo-lithographically patterned. To avoid using an external magnetic field during memory switching, the shape of the memory cell can also be made elliptical with an aspect ratio of 1.5-3 for its long(easy)/short (hard) (a/b) axes, and with its long a (magnetic easy) axis pointing (canted) at an angle c ranging between 10 to 90 degree in the X-Y plane (see FIG. 4), said X axis is the current flowing direction and Y is perpendicular to X; a preferred canting angle is 45 degree; wherein said canted annealing is needed to avoid using an external field at beginning of switching process.

[0041] After photo-patterning the whole bCSOT-MTJ stack is etched using the cap layer 18 as a hard mask. As shown in FIG. 5A the etched SOT-MTJ cross section shows a bigger size at bottom (where the MPS is located) and small at the top (where the MM and SHC are located) which is particularly beneficial for magnetic stability because a larger MPS footprint exhibits a higher blocking temperature for the AFM material and stronger pinning for the pinned magnetic layer. The footprint of the MPS can be further increased by a two-step etch as shown in FIG. 5B in which the first etch stops at MgO and then using another mask to pattern the MPS stack.

[0042] Immediately after etching, a SiN protection layer (19) is deposited to cover the exposed SOT-MTJ surface to cover the exposed MTJ surface and subsequently refill with SiO2 (20) (see FIG. 5C). Then a chemical mechanical polishing (CMP) is used to remove the top excess SiO2, SiN cap layer and part of the SHC layer (see FIG. 5D). Then additional SHC material is added to the remaining SHC (after etch) to stitch them together to form a final current flowing channel (see FIG. 5E).

[0043] At this point, there are two options for the formation of final composite SOT channel: In option-1, the magnetic flux guiding (MFG) layer is deposited after the SHC deposition without vacuum break, and a subsequent new patterning and etching form a final sandwiched MM/SHC/MFG tri-layer CSOT stripe as shown in FIG. 5F (cross section view normal the CSOT stripe); While in option-2, the SHC layer is first patterned and etched to form a bare SHC channel, then deposit a layer of MFG material around the exposed SHC surface in all etched exposed sides to form a wrap-around MFG cladding (see FIG. 5G). The beneficial of option 2 will be seen in the following discussion.

[0044] After formation of the CSOT stripe, two top electrodes (TE1 and TE2) are formed on top of the CSOT with TE1 located at one side (22) and the TE2 at the other side (23) of CSOT stripe (see FIG. 1) in which TE1 is electrically connected to a transistor and TE2 is normally grounded to control the current flowing in the CSOT channel bi-directionally, and one bottom electrode (BE) 24 can be controlled either by a diode or a transistor.

[0045] In FIG. 1, the two magnetic layers 12 (pinned) and 14 (reference) have their magnetic moment aligned in antiparallel across the Ru RKKY coupling layer 13, and the MM 16 is in an anti-parallel state with the reference layer 14 resulting a high magnetoresistance state, while the MFG layer 21 across the SHC layer 17, due to its magnetic softness and extremely high permeability, is always trying to opposite-align with the MM layer 16 to form a close-loop (see FIG. 6A) to help magnetic switching during memory writing, especially for all-around MFG shape shown FIG. 5G. Without such a MFG layer, the magnetic flux outside the MM layer is diverging (see FIG. 6B) which will make it difficult to switch. And most importantly, with such a magnetic close loop, both the spin orbit torque and Lorentz force generated at the lower MM/SHC interface and upper SHC/MFG interface will participate in the switching of the MM layer, more than twice magnitude of torque compared with the ones generated at the upper SHC/MM interface only.

[0046] In FIG. 7A illustrate magnetic switching in a bCSOT-MTJ when a current is flowing through the SHC from TE1 (22) to TE2 (23), while FIG. 7B is for an opposite case with a current flowing from TE2 to TEL. As shown in FIG. 7C, when a current flowing from TE1 to TE2 in the SHC layer (FIG. 7A), there are 2×SOT and two current flow wire (CFW) generated Lorentz forces (2×CFW) acting on the MM layer 16 to switch its magnetic moment to an anti-parallel state with the reference layer 14. With a small magnetic impedance in the closed magnetic loop as shown in FIG. 6A, magnetic polarization of the MM layer can be easily rotated to its final anti-parallel state. Similarly with an opposite current flow in the SHC layer, the magnetic polarization of the MM will be switched to parallel state with the reference layer (see FIG. 7B).

[0047] The magnetic switching of MM layer can be further enhanced by simultaneously passing through a current from bottom electrode (24) to TE2 (see FIG. 8A) utilizing a spin transfer torque (STT) generated by the MTJ stack. Under such a write operation, there are 2SOT+2CFW+STT forces magnetically acting on the MM layer (see FIG. 8B) which make the switching even easier and faster.

[0048] As for read operation, a current will pass through the MTJ stack from bottom electrode (24) up to TE2 (23) (see FIG. 9). For the control of current flow, either a transistor or diode can be used for such operation. From the point of device miniaturization and cost of manufacturing, using a diode is more economic, thus only on transistor one diode (1T1D) is needed for each CSOT-MTJ unit.

[0049] While certain embodiments have been described above, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

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