TRANSCONDUCTANCE AMPLIFIER BASED ON SELF-BIASED CASCODE STRUCTURE

Abstract

Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor C.sub.c, an amplifier load capacitor C.sub.L, a reference current source Iref and a PMOS transistor MO that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor C.sub.c, a higher figure of merit is achieved.

Claims

1. A transconductance amplifier based on a self-biased cascode structure, comprising a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor C.sub.c, an amplifier load capacitor C.sub.L, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function, wherein: sources of the PMOS input transistors M1 and M2 are connected to a drain of the PMOS transistor M0; gates of the PMOS input transistors M1 and M3 are connected to an input signal VIN; gates of the PMOS input transistors M2 and M4 are connected to an input signal VIP; a drain of the PMOS input transistor M1 is connected to a source of the PMOS input transistor M3; a drain of the PMOS input transistor M2 is connected to a source of the PMOS input transistor M4; substrates of the PMOS input transistors M3 and M4 are connected to a bias voltage Vp; and the bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in an amplifier bias circuit; a gate and a drain of the NMOS transistor M5 are both connected to gates of the NMOS transistors M6, M7 and M8 and a drain of the PMOS input transistor M3; a drain of the NMOS transistor M6 is connected to a drain of the PMOS input transistor M4; a source of the NMOS transistor M5 is connected to a drain of the NMOS transistor M7; a source of the NMOS transistor M6 is connected to a drain of the NMOS transistor M8; sources of the NMOS transistors M7 and M8 are grounded; substrates of the NMOS transistors M5 and M6 are connected to a bias voltage Vn; and the bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in the amplifier bias circuit; sources of the PMOS transistors M10, M0 and M13 are connected to a supply voltage vdd; a gate of the PMOS transistor M10 is connected to gates of the PMOS transistors M0 and M13; a drain of the PMOS transistor M10, one end of the compensation capacitor C.sub.c, a drain of the NMOS transistor M9 and one end of the load capacitor C.sub.L are connected to form a connection node; the connection node is an output end Vout of the transconductance amplifier; the other end of the compensation capacitor C.sub.c is connected to a drain of the PMOS input transistor M2; the other end of the load capacitor C.sub.L and a source of the NMOS transistor M9 are grounded; and a gate of the NMOS transistor M9 is connected to a drain of the PMOS input transistor M4; a drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12; a gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11; sources of the NMOS transistors M11 and M12 are grounded; and the other end of the reference current source Iref is connected to the supply voltage vdd.

2. The transconductance amplifier based on the self-biased cascode structure according to claim 1, wherein a ratio of a channel length of the PMOS input transistor M1 to a channel length of the PMOS input transistor M3 is 1:4, and a ratio of a channel length of the NMOS transistor M5 to a channel length of the NMOS M7 is 1:4.

3. The transconductance amplifier based on the self-biased cascode structure according to claim 1, wherein the compensation capacitor C.sub.c has the capacitance of 2 pF to 4 pF.

4. A transconductance amplifier based on a self-biased cascode structure, comprising a self-biased cascode input-stage structure constituted by NMOS input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by PMOS transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor C.sub.c, an amplifier load capacitor C.sub.L, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function, wherein: sources of the NMOS input transistors M1 and M2 are grounded; gates of the NMOS input transistors M1 and M3 are connected to an input signal VIN; gates of the NMOS input transistors M2 and M4 are connected to an input signal VIP; a drain of the NMOS input transistor M1 is connected to a source of the NMOS input transistor M3; a drain of the NMOS input transistor M2 is connected to a source of the NMOS input transistor M4; substrates of the NMOS input transistors M3 and M4 are connected to a bias voltage Vn; and the bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in an amplifier bias circuit; a gate and a drain of the PMOS transistor M5 are both connected to gates of the PMOS transistors M6, M7 and M8 and a drain of the NMOS input transistor M3; a drain of the PMOS transistor M6 is connected to a drain of the NMOS input transistor M4; a source of the PMOS transistor M5 is connected to a drain of the PMOS transistor M7; a source of the PMOS transistor M6 is connected to a drain of the PMOS transistor M8; sources of the PMOS transistors M7 and M8 are connected to a drain of the PMOS transistor M0; substrates of the PMOS transistors M5 and M6 are connected to a bias voltage Vp; and the bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in the amplifier bias circuit; a source of the PMOS transistor M10 is connected to a supply voltage vdd; a drain of the PMOS transistor M10, one end of the compensation capacitor C.sub.c, a drain of the NMOS transistor M9 and one end of the load capacitor C.sub.L are connected to form a connection node; the connection node is an output end Vout of the transconductance amplifier; a gate of the PMOS transistor M10 is connected to a drain of the NMOS input transistor M4; the other end of the compensation capacitor C.sub.c is connected to a drain of the PMOS input transistor M2; the other end of the load capacitor C.sub.L and a source of the NMOS transistor M9 are grounded; and a gate of the NMOS transistor M9 is connected to a gate of the NMOS transistor M12; and sources of the PMOS transistors M0 and M13 are connected to the supply voltage vdd; a gate of the PMOS transistor M0 is connected to a gate and a drain of the PMOS transistor M13; a drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12; a gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11; sources of the NMOS transistors M11 and M12 are grounded; and the other end of the reference current source Iref is connected to the supply voltage vdd.

5. The transconductance amplifier based on the self-biased cascode structure according to claim 4, wherein a ratio of a channel length of the NMOS input transistor M1 to a channel length of the NMOS input transistor M3 is 1:4, and a ratio of a channel length of the PMOS transistor M5 to a channel length of the PMOS M7 is 1:4.

6. The transconductance amplifier based on the self-biased cascode structure according to claim 4, wherein the compensation capacitor C.sub.c has the capacitance of 2 pF to 4 pF.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is a schematic diagram of a traditional two-stage transconductance amplifier;

[0029] FIG. 2 is a schematic diagram of a traditional self-biased cascode transconductance amplifier;

[0030] FIG. 3 is a schematic view of a small-signal equivalent circuit of a self-biased cascode structure shown in FIG. 2;

[0031] FIG. 4 is a schematic diagram of a transconductance amplifier based on a self-biased cascode structure according to the present invention;

[0032] FIG. 5 is a small-signal equivalent circuit of the transconductance amplifier based on the self-biased cascode structure shown in FIG. 4;

[0033] FIG. 6 is a schematic view of a variation trend of AC characteristics of the transconductance amplifier based on the self-biased cascode structure along with a compensation capacitor C.sub.c;

[0034] FIG. 7 is a schematic view showing comparison of AC characteristic simulation results of the three structures in FIG. 1, FIG. 2 and FIG. 4; and

[0035] FIG. 8 is a schematic diagram of another transconductance amplifier based on a self-biased cascode structure according to the present invention.

DETAILED DESCRIPTION

[0036] In order to make technical means, creation features and objective and effect achievements of the present invention easy to understand, the present invention will be further described below with reference to specific figures.

[0037] As shown in FIG. 4, provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor C.sub.c, an amplifier load capacitor C.sub.L, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function.

[0038] The PMOS input transistors M1, M2, M3 and M4 constitute the self-biased cascode structure to keep relatively high output impedance and simultaneously to provide relatively high output impedance. The PMOS input transistors M1 and M3 are connected in series. The PMOS input transistors M2 and M4 are connected in series. Sources of the PMOS input transistors M1 and M2 are connected to a drain of the PMOS transistor M0. Gates of the PMOS input transistors M1 and M3 are connected to an input signal VIN. Gates of the PMOS input transistors M2 and M4 are connected to an input signal VIP. A drain of the PMOS input transistor M1 is connected to a source of the PMOS input transistor M3. A drain of the PMOS input transistor M2 is connected to a source of the PMOS input transistor M4. Substrates of the PMOS input transistors M3 and M4 are connected to a bias voltage Vp. The bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in an amplifier bias circuit.

[0039] The NMOS transistors M5, M6, M7 and M8 constitute the self-biased cascode structure to provide high output impedance. The NMOS transistors M5 and M7 are connected in series. The NMOS transistors M6 and M8 are connected in series. A gate and a drain of the NMOS transistor M5 are both connected to gates of the NMOS transistors M6, M7 and M8 and a drain of the PMOS input transistor M3. A drain of the NMOS transistor M6 is connected to a drain of the PMOS input transistor M4. A source of the NMOS transistor M5 is connected to a drain of the NMOS transistor M7. A source of the NMOS transistor M6 is connected to a drain of the NMOS transistor M8. Sources of the NMOS transistors M7 and M8 are grounded. Substrates of the NMOS transistors M5 and M6 are connected to a bias voltage Vn. The bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in the amplifier bias circuit.

[0040] Sources of the PMOS transistors M10, M0 and M13 are connected to a supply voltage vdd. A gate of the PMOS transistor M10 is connected to gates of the PMOS transistors M0 and M13. A drain of the PMOS transistor M10, one end of the compensation capacitor C.sub.c, a drain of the NMOS transistor M9 and one end of the load capacitor C.sub.L are connected to form a connection node. The connection node is an output end Vout of the transconductance amplifier. The other end of the compensation capacitor C.sub.c is connected to a drain of the PMOS input transistor M2. The other end of the load capacitor C.sub.L and a source of the NMOS transistor M9 are grounded. A gate of the NMOS transistor M9 is connected to a drain of the PMOS input transistor M4.

[0041] A drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12. A gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11. Sources of the NMOS transistors M11 and M12 are grounded. The other end of the reference current source Iref is connected to the supply voltage vdd.

[0042] According to the transconductance amplifier based on the self-biased cascode structure, provided in the present invention, both the input transistors and the load transistors of a first-stage amplifier adopt self-biased cascode structures. In comparison with a traditional structure, the output impedance and the DC gain of the first-stage amplifier are increased obviously. The substrate voltages of the PMOS input transistors M3 and M4 and the NMOS transistors M5 and M6 of the first-stage amplifier are provided by the amplifier bias circuit without adding a bias voltage. In addition, owing to the connection mode of the compensation capacitor C.sub.c, a transmission function of the amplifier will generate one left half plane zero which can be utilized to compensate for a first non-dominant pole of the transmission function. Thus, a unity-gain bandwidth of the amplifier is greatly increased while a relatively large phase margin is kept. Further, a higher figure of merit is achieved.

[0043] A side circuit is analyzed blow. Channel widths of the PMOS input transistors M1 and M3 in FIG. 4 are both designed to be the same as a channel width of the PMOS input transistor M1 in FIG. 1. At the same time, the sum of the channel lengths of the PMOS input transistors M1 and M3 in FIG. 4 is designed to be the same as a channel length of the PMOS input transistor M1 in FIG. 1. On the other hand, channel widths of the NMOS transistors M5 and M7 in FIG. 4 are both designed to be the same as a channel width of the NMOS transistor M3 in FIG. 1. The sum of the channel lengths of the NMOS transistors M5 and M7 in FIG. 4 is designed to be the same as a channel length of the NMOS transistor M3 in FIG. 1. In this way, an input transistor M1 and a load transistor M3 in FIG. 1 occupy the same areas as the input transistors M1 and M3 and the load transistors M5 and M7 in FIG. 4. Through analysis on the structure shown in FIG. 2, it can be known that if the channel lengths of the PMOS input transistors M1 and M3 connected in series and the NMOS transistors M5 and M7 connected in series in FIG. 4 are reasonably distributed, the DC gain of the amplifier in FIG. 4 may be represented as:

Gain.sub.[proposed]=g.sub.m1,2.Math.((g.sub.m3.Math.r.sub.o1.Math.r.sub.o3)∥(g.sub.m5.Math.r.sub.o5.Math.r.sub.o7)).Math.g.sub.m9.Math.(r.sub.o9∥r.sub.o10)  (6)

[0044] It can be known from formula (6) that the DC gain of the transconductance amplifier based on the self-biased cascode structure in FIG. 4 is obviously larger than that of the structure shown in FIG. 2. As a specific implementation mode that the channel lengths of the PMOS input transistors M1 and M3 connected in series and the NMOS transistors M5 and M7 connected in series in FIG. 4 are reasonably distributed, a ratio of the channel length of the PMOS input transistor M1 to the channel length of the PMOS input transistor M3 is 1:4, and a ratio of the channel length of the NMOS transistor M5 to the channel length of the NMOS transistor M7 is 1:4.

[0045] A compensation mode of the structure shown in FIG. 4 will be analyzed below, still analyzing the side circuit. FIG. 5 is a schematic diagram of a small-signal equivalent circuit of the structure shown in FIG. 4. A KCL node equation is formulated as below:

[00002]$\begin{array}{cc}\{\begin{array}{c}\frac{\Delta Vx}{r_{o1}}+g_{m1}.Math.\Delta \mathrm{Vin}+\frac{\Delta Vx-\Delta Vy}{r_{o3}}-g_{m3}.Math.\left(\Delta \mathrm{Vin}-\Delta \mathrm{Vx}\right)+\left(\Delta \mathrm{Vx}-\Delta \mathrm{Vo}\right).Math.\mathrm{sCc}=0\\ \frac{\Delta Vy-\Delta Vx}{r_{o3}}+\frac{\Delta Vy}{g_{m5}.Math.r_{o5}.Math.r_{o7}}+g_{m3}.Math.\left(\Delta \mathrm{Vin}-\Delta \mathrm{Vx}\right)=0\\ \left(\Delta Vo-\Delta \mathrm{Vx}\right).Math.\mathrm{sCc}+\frac{\Delta \mathrm{Vo}}{r_{o10}}+g_{m9}.Math.\Delta \mathrm{Vy}+\frac{\Delta Vo}{r_{o9}}+\Delta \mathrm{Vo}.Math.\mathrm{sCL}=0\end{array}& \left(7\right)\end{array}$

[0046] In the equation set (7), g.sub.m5.Math.r.sub.o5.Math.r.sub.o7 is small-signal equivalent output impedances of the NMOS transistors M5 and M7 connected in series in FIG. 4. By solving the equation set (7), it can be known that a transmission function of the small-signal equivalent circuit shown in FIG. 5 has one left half plane zero with the following formula:

[00003]$\begin{array}{cc}z\approx -k\frac{g_{m3}}{Cc}& \left(8\right)\end{array}$

[0047] In formula (8), k is a constant. It can be known from formula (8) that the transmission function of the circuit structure shown in the present invention has one left half plane zero that will move to a low frequency with increase of the compensation capacitor Cc. The specific variation trend of the left half plane zero is as shown in FIG. 6. It can be seen from FIG. 6 that with increase of the compensation capacitor C.sub.c, curves that represent an amplitude-frequency characteristic and a phase-frequency characteristic of the circuit structure shown in the present invention both tilt up. This shows that a simulation result conforms to the foregoing theoretical derivation. Thus, a first non-dominant pole of the transmission function can be compensated by the left half plane zero. Further, the circuit structure shown in the present invention can obtain a larger unity-gain bandwidth.

[0048] In order to further verify the above-mentioned advantages of the present invention, the foregoing three structures are carefully designed under a 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process. In addition, input/output transistors and the load transistors are the same in size. The capacitance of the compensation capacitor C.sub.c is taken as 2 pF, and the capacitance of the load capacitor is taken as 15 pF. At last, a diagram showing comparison of AC characteristic simulation results of the three structures is as shown in FIG. 7. The solid line represents the simulation result of the AC characteristic of the present invention, the broken line represents the simulation result of the AC characteristic of the structure shown in FIG. 2, and the center line represents the simulation result of the AC characteristic of the structure shown in FIG. 1. It can be seen from FIG. 7 that in comparison with the traditional structures 1 and 2, since both the first-stage input transistors and the first-stage load transistors in the present invention adopt the self-biased cascode structures, the DC gain is increased remarkably. Meanwhile, since one left half plane zero is generated by the adopted compensation mode, the unity-gain bandwidth is increased obviously. Moreover, a larger phase margin can be acquired. In other words, the compensation capacitor C.sub.c required by the present invention has a smaller area under the condition of acquiring the same unity-gain bandwidth. Thus, more area is saved.

[0049] In the meantime, comparison results of basic parameters of the three structures are as shown in Table 1. Seen from the simulation result of Table 1, with respect to the two traditional structures, the low self-biased transconductance amplifier structure provided in the present invention has the advantages that under the condition of the same power consumption, the DC gain is at least increased by 26%, the unity-gain bandwidth is at least increased by 140%, and the FOM (Figure of Merit) is at least increased by 210%.

TABLE-US-00001 TABLE 1 Structure Structure Present Parameter 1 2 invention Power supply (V) 1.8 1.8 1.8 Technology (μm) 0.18 0.18 0.18 Capacitive load (pF) 15 15 15 Unity-gain bandwidth 56 60 146 (MHz) Phase margin (°) 60 63 71 DC gain (dB) 71 76 96 Power consumption (μW) 720 720 720 FOM (dB .Math. MHz/μW) 5.5 6.3 19.5

[0050] As a preferred embodiment, the compensation capacitor C.sub.c has the capacitance of 2 pF to 4 pF. Thus, a relatively excellent compensation effect can be achieved without occupying an excessively large area of a chip.

[0051] The structure shown in FIG. 4 takes the PMOS transistors as the input transistors. Similarly, NMOS transistors may also serve as the input transistors with respect to all analysis of the present invention, of which a schematic diagram is as shown in FIG. 8. Accordingly, further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which takes NMOS transistors as input transistors. The provided transconductance amplifier includes a self-biased cascode input-stage structure constituted by NMOS input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by PMOS transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor C.sub.c, an amplifier load capacitor C.sub.L, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function.

[0052] Sources of the NMOS input transistors M1 and M2 are grounded.

[0053] Gates of the NMOS input transistors M1 and M3 are connected to an input signal VIN. Gates of the NMOS input transistors M2 and M4 are connected to an input signal VIP. A drain of the NMOS input transistor M1 is connected to a source of the NMOS input transistor M3. A drain of the NMOS input transistor M2 is connected to a source of the NMOS input transistor M4. Substrates of the NMOS input transistors M3 and M4 are connected to a bias voltage Vn. The bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in an amplifier bias circuit.

[0054] A gate and a drain of the PMOS transistor M5 are both connected to gates of the PMOS transistors M6, M7 and M8 and a drain of the NMOS input transistor M3. A drain of the PMOS transistor M6 is connected to a drain of the NMOS input transistor M4. A source of the PMOS transistor M5 is connected to a drain of the PMOS transistor M7. A source of the PMOS transistor M6 is connected to a drain of the PMOS transistor M8. Sources of the PMOS transistors M7 and M8 are connected to a drain of the PMOS transistor M0. Substrates of the PMOS transistors M5 and M6 are connected to a bias voltage Vp. The bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in the amplifier bias circuit.

[0055] A source of the PMOS transistor M10 is connected to a supply voltage vdd. A drain of the PMOS transistor M10, one end of the compensation capacitor C.sub.c, a drain of the NMOS transistor M9 and one end of the load capacitor C.sub.L are connected to form a connection node. The connection node is an output end Vout of the transconductance amplifier. A gate of the PMOS transistor M10 is connected to a drain of the NMOS input transistor M4. The other end of the compensation capacitor C.sub.c is connected to a drain of the PMOS input transistor M2. The other end of the load capacitor C.sub.L and a source of the NMOS transistor M9 are grounded. A gate of the NMOS transistor M9 is connected to a gate of the NMOS input transistor M12.

[0056] Sources of the PMOS transistors M0 and M13 are connected to the supply voltage vdd. A gate of the PMOS transistor M0 is connected to a gate and a drain of the PMOS transistor M13. A drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12. A gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11. Sources of the NMOS transistors M11 and M12 are grounded. The other end of the reference current source Iref is connected to the supply voltage vdd.

[0057] As a specific embodiment, except that the structure shown in FIG. 8 adopts the NMOS transistors as the input transistors, its corresponding circuit analysis is similar to that of the structure shown in FIG. 4, and therefore, will not be repeated herein. Similarly, as a specific implementation mode that the channel lengths of the NMOS input transistors M1 and M3 connected in series and the PMOS transistors M5 and M7 connected in series in FIG. 8 are reasonably distributed, a ratio of the channel length of the PMOS input transistor M1 to the channel length of the PMOS input transistor M3 is 1:4, and a ratio of the channel length of the NMOS transistor M5 to the channel length of the NMOS transistor M7 is 1:4. As a preferred embodiment, the compensation capacitor Cc has the capacitance of 2 pF to 4 pF. Thus, a relatively excellent compensation effect can be achieved without occupying an excessively large area of a chip.

[0058] The above descriptions are merely implementation modes of the present invention, and are not intended to limit the scope of the present invention. Equivalent structures made on the basis of the Description and the drawings of the present invention and directly or indirectly applied to other related technical fields should fall within the protection scope of the present invention in a similar way.