Methods and devices for microelectromechanical pressure sensors
11111135 · 2021-09-07
Assignee
Inventors
Cpc classification
G01L9/12
PHYSICS
B81C1/00182
PERFORMING OPERATIONS; TRANSPORTING
B81B7/007
PERFORMING OPERATIONS; TRANSPORTING
B81C1/00269
PERFORMING OPERATIONS; TRANSPORTING
G01L9/0042
PHYSICS
International classification
B81C1/00
PERFORMING OPERATIONS; TRANSPORTING
G01L9/12
PHYSICS
B81B7/00
PERFORMING OPERATIONS; TRANSPORTING
H03H3/007
ELECTRICITY
G01L9/00
PHYSICS
Abstract
MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics.
Claims
1. A method for post-fabrication of a MEMS device, the method comprising: providing the MEMS device comprising (i) a handling layer, (ii) a top layer, and (iii) a device layer located between the handling layer and the top layer, wherein the handling layer comprises a first trench on a top face of the handling layer adjacent to the device layer, wherein the top layer comprises a second trench on a bottom face of the top layer adjacent to the device layer, the second trench facing the first trench, wherein a first portion of the top layer is electrically insulated from a second portion of the top layer, wherein the first portion of the top layer extends to the second trench, wherein the device layer comprises a section of silicon positioned between the first trench and the second trench; etching a back face of the handling layer until reaching the first trench, thereby forming an opening extending through the handling layer; and etching the section of silicon of the device layer through the opening in the handling layer, thereby thinning the section of silicon of the device layer to form a flexible membrane that is (i) positioned between the opening and the second trench and (ii) capacitively coupled with the first portion of the top layer.
2. The method of claim 1, wherein etching the section of silicon of the device layer comprises dry etching the section of silicon of the device layer or wet etching the section of silicon of the device layer.
3. The method of claim 1, wherein etching the back face of the handling layer comprises wet etching the back face of the handling layer or dry etching the back face of the handling layer.
4. The method of claim 1, wherein the second trench is at a vacuum pressure.
5. The method of claim 2, wherein the MEMS device further comprises an insulating layer deposited on the top face of the handling layer adjacent to the device layer, and wherein forming the opening further comprises etching through the insulating layer.
6. The method of claim 1, further comprising securing a CMOS electronics wafer to a top face of the top layer opposite the bottom face of the top layer.
7. The method of claim 1, wherein thinning the section of silicon of the device layer to form the flexible membrane comprises (i) etching a central portion of the section of silicon of the device layer to a first thickness and (ii) etching an outer portion of the section of silicon of the device layer to a second thickness that is thinner than the first thickness.
8. The method of claim 1, wherein etching the section of silicon of the device layer through the opening in the handling layer comprises deep reactive-ion etching the section of silicon of the device layer.
9. The method of claim 1, wherein providing the MEMS device comprises (i) forming the first trench on the top face of the handling layer and (ii) bonding the device layer to the handling layer.
10. The method of claim 9, wherein providing the MEMS device further comprises (i) forming the second trench on the bottom face of the top layer and (ii) bonding the top layer to the device layer.
11. The method of claim 10, wherein the top layer is bonded to the device layer while under a vacuum pressure.
12. The method of claim 10, wherein the device layer comprises a first plurality of fingers protruding toward the top layer into the second trench, wherein the top layer comprises a second plurality of fingers protruding toward the device layer into the second trench, and wherein bonding the top layer to the device layer comprises bonding the top layer to the device layer such that the first plurality of fingers and the second plurality of fingers are interdigitated.
13. The method of claim 10, wherein bonding the top layer to the device layer comprises bonding the second portion of the top layer to the device layer.
14. The method of claim 9, wherein the top layer further comprises an annulus with finite thickness that insulates the first portion of the top layer from the second portion of the top layer.
15. The method of claim 14, wherein the first portion of the top layer is electrically connected to a first electrode of the MEMS device, wherein the second portion of the top layer is electrically connected to a second electrode of the MEMS device.
16. The method of claim 14, further comprising forming a first electrical contact on the first portion of the top layer and a second electrical contact on the second portion of the top layer.
17. The method of claim 16, further comprising bonding the first electrical contact and the second electrical contact to a CMOS circuit.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
DETAILED DESCRIPTION
(14) The present invention is directed to MEMS sensors and more particularly to absolute pressure MEMS capacitive sensors which may be manufactured directly over or in conjunction with silicon based CMOS electronics.
(15) The ensuing description provides exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It being understood that various changes may be made in the function and arrangement of elements without departing form the spirit and scope as set forth in the appended claims.
(16) A. Pressure Sensor
(17) Miniaturized pressure sensors are among the most mass-produced MEMS devices in the recent years and find its applications in different areas including automotive, and aerospace, energy and biomedical application. As discussed supra it would be beneficial to realize a capacitive sensor constituting of a high vacuum cavity without any post-fabrication sealing requirements providing an absolute pressure sensor with improved manufacturing yields whilst controlling the membrane thickness forming the mechanical test specimen. Accordingly, embodiments of the invention exploit both bulk micromachining and surface micromachining in order to provide a MEMS pressure sensor offering: Effective control of the membrane thickness and consequently a predictable response of the theoretical calculations; Good encapsulation of the cavity without any need to create holes to allow for the sealing technique; Small gap between the two electrodes, which increases the DC capacitance value, and consequently the sensor sensitivity. The small gap is precise and well controlled by means of spacer layer; and Higher vacuum in the cavity increasing hence the quality factor Q, the frequency range of the measurement for dynamic measurement and ultimately the reliability of the sensor.
(18) A1. Theoretical Analysis
(19) A1.A Static Modeling: The design of the MEMS capacitor pressure sensor 100 is based on two electrodes 102, 104 forming an electrical capacitor. As depicted in
(20) Referring to
(21)
(22) A1.B Dynamic Modeling: The dynamic modeling takes into account the dynamic measurement of the pressure in order to deduce the frequency range over which the sensor 100 can sustain its metrology specifications. In this context the objective is to identify the mechanical impedance i.e. the equivalent spring coefficient constant. k.sub.eq, equivalent mass, m.sub.eff, and damping coefficient, b.sub.eq. If we consider p(t)=p.sub.m sin(ωt)−p.sub.0.Math.{dot over (p)}=p.sub.mω cos(ωt) then the output voltage defined in Equation (6C) can be re-written as Equations (2A) and (2B).
(23)
(24) With respect to damping coefficient expression then based upon the Reynold's equation
(25)
where η is the dynamic viscosity. In cylindrical coordinates, we get Equation (3). As a result the mechanical impedance can be expressed by its basic parameters as given by Equations (4A) to (4C) respectively.
(26)
(27) A1.C Sensor Sensitivities: Based upon the expression of the capacitance in terms of the applied pressure then it is possible to deduce the expression of the electrical signal in terms of pressure as described by Equation (5).
(28)
(29) Accordingly, the capacitance of the MEMS sensor 100 is given by Equation (6) wherein if we subsequently let
(30)
we derive Equations (7). Then letting
(31)
we derive Equation (8).
(32)
(33) Accordingly, solving this we derive Equations (9A) and (9B) which yields Equations (10) and (11) and hence the sensitivity is defined by Equations (12) and (13).
(34)
(35) A2. Design.
(36) The methodology 400 adopted by the inventors was based on a common prototyping methodology for MEMS sensors, which as depicted in
(37) In order to obtain a linear relationship the inventors only use the first order expansion of Equation (10) where u.sub.0 is proportional to the applied pressure. C.sub.0 is the capacitance of the un-deformed membrane 106 and is given by
(38)
and α is the dimensionless parameter controlling the effective radius of the upper electrode 104 and its choice depends on the fabrication design rules check (DRC). Preliminary simulation results were deduced and a depicted in
(39) Within the modelling and design iteration process the ratio of u.sub.0/d<<1. This leads to Equations (14) and (15). Through the design process the inventors choose the lowest d and for each couple (R, h) chose designs that fit with the required specification of δp. In order to calculate the couple (R, h) the mechanical sensitivity is fixed by setting S.sub.mec=U.sub.max/P.sub.max, then the value of R is fixed, which in turn is dependent upon the available die area. The resulting value of h is calculated using Equation (16).
(40)
(41) Subsequently, for each set of (R, h), the ratio is checked to verify that the circular membrane 106 can be considered a membrane. Finally, it is verified that the design meets the required pressure resolution specification.
(42) A3. Fabrication
(43) A3.A Design Cross-Section.
(44)
(45) Sub-process 604 involves additional combined handling and device wafer processing.
(46) In the third sub-process 606, TSVs are implemented as required in the top layer which is then bonded to the handling and device wafer combination.
(47) In the third sub-process 606, the top layer 506 is fabricated using TSV processes, and a 2 μm trench is etched in the bottom surface of the top layer 506.
(48) The upper contacts 512, 513 are defined on the top layer 506 as depicted in
(49) A layer of polymer is disposed as the passivation layer 522 to protect the top layer 506.
(50) Following sub-process 604 and 606, the top wafer 506 is wafer-wafer bonded to the device layer 504 and handling layer 500. The trench that was previously defined in the top layer 506 in sub-process 606 defines the cavity 508. The environment at the time of bonding controls the environment within the cavity. If the bonding is performed in a vacuum, the deflection of the membrane 106 is dependent solely upon the pressure exerted upon it by the environment below the membrane, and hence the pressure sensor 100 is an absolute pressure sensor.
(51) As shown in
(52) The membrane 106 of the capacitor is formed during post-fabrication processes. The post-processing steps yield the device cross-sections depicted in
(53) Beneficially, the post-processing sequence does not require any alignment marks on the backside, thereby avoiding the requirement for a photolithography processes and there is no requirement for a hard etch mask for the deep reactive ion etching of the handling and device layers 500, 504 wherein approximately 232 μm of material is removed from the geometry. Accordingly, there are no requirements for any plasma enhanced chemical vapour deposition (PECVD) oxide/nitride deposition or low temperature oxide (LTO) deposition and its subsequent dry or wet etching. The process is suited to forming devices such as pressure sensors for a range of applications. Accordingly, the top side 520 of the device 518 is protected initially, for example, with thick PECVD silicon nitride, silicon oxide, or silicon oxynitride. There are a range of different process configurations to achieve the desired post-processing, including, for example, purely wet etching, purely dry etching, and combinations thereof. Exemplary processes for each of these are presented below.
(54) Wet Etching: The first post-processing step is a wet etching process using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) in order to etch down the handling wafer 500 until the oxide layer 524 deposited onto the handling wafer 500 within the trench is reached. Within the structure depicted in
(55) Dry Etching. In this process, dry etching of the handling wafer 500 is initially performed until reaching the oxide layer 524, requiring removal of approximately 232 μm of silicon wafer for the structure depicted in
(56) Dry and Wet Etching A: In this process, dry etching of the handling wafer 500 is initially performed until reaching the oxide layer 524, requiring removal of approximately 232 μm of silicon wafer for the structure depicted in
(57) Dry and Wet Etching B: In this process, wet etching of the handling wafer 500, using KOH or TMAH, is initially performed until reaching the oxide layer 524, requiring removal of approximately 232 μm of silicon wafer for the structure depicted in
(58) Referring to
(59) It would be evident that the MEMS pressure sensor 100 described with respect to embodiments of the invention may be formed simultaneously/concurrently with other MEMS devices exploiting the same three layer design methodology of handling layer 500 (bottom layer), device layer 504, and top layer 506 (TSV layer). By the addition of a photolithography process prior to etching the opening within the handling wafer 500 through which the MEMS pressure sensors are formed then the handling wafer thickness over the remaining regions is maintained.
(60) Accordingly, considering the process flow 600 described above in connection with
(61) It would be evident that formation of a beam resonator within a cavity and absolute pressure sensor may be made within the same device using the designs described supra wherein in the absolute pressure sensor the handling wafer 500 is processed to remove the silicon, opening the lower cavity 502 to ambient pressure, whereas in the resonator case the silicon is not removed.
(62) Referring to first and second cross-sections 1200A and 1200B in
(63) A3.B CMOS Electronics Integration
(64) Referring to
(65) A4. Simulation and Results
(66) Referring to Table 1 there are listed the design parameters for a MEMS pressure sensor 100 fabricated according to an embodiment of the invention. The calibration curve derived for this MEMS sensor 100 is depicted in
(67) TABLE-US-00001 TABLE 1 Pressure Sensor Specification Parameter Value Gap (μm) 2 Radius (μm) 180 Thickness (μm) 12 Sensitivity (pF/kPa) 4.96 × 10.sup.−4 Resolution (δC = 10 fF) kPa 20.2 Equivalent Mass m.sub.eff (kg) 1.40 × 10.sup.−9 Equivalent Spring Constant 47100 Damping Coefficient b.sub.eff (N/m) 1.13 × 10.sup.−2 Natural Frequency (kHz) 922.920
(68) Beneficially, embodiments of the invention provide a fabrication process which is designed to be fully compatible with monolithic integration above CMOS electronics, and other electronics technologies that can withstand the low processing temperatures of embodiments of the invention. Beneficially this provides: direct integration over the electronics; improved system performance through reduced parasitic effects; reduced die size; increased electronics selection freedom, allowing for use of high performance technological nodes reduced package footprint and thickness; self-aligned processing; lower sensor fabrication costs through batch processing; integral reference elements; and integral heaters and/or temperature stabilization.
(69) Referring to
(70) The foregoing disclosure of the exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above disclosure. The scope of the invention is to be defined only by the claims appended hereto, and by their equivalents.
(71) Further, in describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of step. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.