Method of manufacturing a semiconductor on insulator type structure, notably for a front side type imager

Abstract

A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

Claims

1. A method of manufacturing a semiconductor on insulator structure comprising: providing a donor substrate comprising a semiconductor material suitable for epitaxial growth of a material of an active layer thereon; providing a support substrate; bonding the donor substrate to the support substrate, an electrically insulating layer being at a bonding interface; thinning the donor substrate so as to transfer a layer of the semiconductor material onto a front side of the support substrate; depositing a silicon oxide layer on a rear side of the support substrate at a first temperature; and after depositing the oxide layer, epitaxially growing the active layer on the transferred layer of semiconductor material at a second temperature greater than the first temperature.

2. The method of claim 1, wherein the active layer comprises silicon-germanium.

3. The method of claim 2, wherein the semiconductor material of the donor substrate comprises silicon-germanium.

4. The method of claim 3, wherein the semiconductor material is formed by epitaxy on a base substrate, the semiconductor material and the base substrate together forming the donor substrate.

5. The method of claim 2, wherein the semiconductor material of the donor substrate comprises silicon.

6. The method of claim 5, wherein a thickness of the silicon layer transferred onto the support substrate is less than or equal to 400 nm.

7. The method of claim 5, wherein the silicon layer remains between the electrically insulating layer and the silicon-germanium layer after epitaxially growing the active layer comprising silicon-germanium.

8. The method of claim 5, further comprising condensation of the silicon-germanium of the active layer so as to convert the silicon layer into a silicon-germanium layer.

9. The method of claim 1, comprising forming an embrittlement zone in the donor substrate so as to delimit a layer of the semiconductor material suitable for the epitaxial growth of the material of the active layer, and wherein the thinning of the donor substrate comprises a detachment along the embrittlement zone.

10. The method of claim 9, wherein the formation of the embrittlement zone comprises an implantation of atomic species in the donor substrate.

11. The method of claim 1, wherein the second temperature is between 600 and 1100° C.

12. The method of claim 1, wherein the first temperature is between 100 and 400° C.

13. The method of claim 1, wherein a thickness of the silicon oxide layer is selected such that stress generated upon cooling the semiconductor on insulator structure after depositing the silicon oxide layer due to a difference in thermal expansion coefficient between the silicon oxide layer and the support substrate results in the semiconductor on insulator structure having a bow less than a predefined limit value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other characteristics and advantages of the present disclosure will become clear from reading the detailed description that follows, with reference to the appended drawings, in which:

(2) FIG. 1 is a sectional view of a known SOI structure for a front side imager;

(3) FIG. 2 is a sectional view of a structure according to one embodiment of the present disclosure;

(4) FIG. 3 shows the coefficient of absorption of silicon-germanium as a function of wavelength for different germanium contents;

(5) FIG. 4 shows the critical thickness of a silicon layer-germanium as a function of the germanium content thereof;

(6) FIG. 5 represents the bow of a silicon substrate with a stressed SiGe layer epitaxied on its front side; this bow is plotted as a function of the stress in the SiGe and the thickness of SiGe;

(7) FIG. 6 is a sectional view of a substrate according to an alternative embodiment of the present disclosure;

(8) FIGS. 7A to 7G illustrate the main steps of a method of manufacturing a structure according to one embodiment of the present disclosure;

(9) FIGS. 8A to 8C illustrate the steps of an alternative of the manufacturing method illustrated in FIGS. 7A to 7F;

(10) FIGS. 9A to 9E illustrate the main steps of a method of manufacturing a structure according to another embodiment of the present disclosure; and

(11) FIG. 10 is a sectional view of a pixel of a “front side” type imager comprising a structure according to one embodiment of the present disclosure.

(12) For reasons of legibility of the figures, the different layers are not necessarily drawn to scale.

DETAILED DESCRIPTION

(13) FIG. 2 is a sectional view of a semiconductor on insulator substrate according to one embodiment of the present disclosure. Such a substrate can notably be used for the manufacture of a front side type imager, but is not limited to such an application.

(14) The substrate successively comprises, from its rear side to its front side, a silicon oxide (SiO.sub.2) layer 4, a semiconductor support substrate 1, an electrically insulating layer 2 and a monocrystalline semiconductor layer 3, which is the active layer.

(15) In the remainder of the description, it will be considered that the active layer 3 is a silicon-germanium (SiGe) layer, but the present disclosure is not limited to this material, the active layer also being able to be formed of another semiconductor material, such as germanium or a III-V material, having a state of mechanical stress with respect to the support substrate.

(16) The support substrate 1 is generally obtained by cutting a monocrystalline ingot. Advantageously, the support substrate 1 is made of silicon.

(17) According to one embodiment, the electrically insulating layer is a silicon oxide layer.

(18) The thickness of the electrically insulating layer may be between 10 and 200 nm.

(19) The active layer 3 is intended to form the active layer of an electronic, optic or optoelectronic component. Thus, in application to an imager, the active layer 3 is intended to receive or include a matrix array of photodiodes (not represented) enabling the capture of images. The thickness of the active layer 3 is typically greater than or equal to 1 μm. The layer 3 may be lightly doped.

(20) As may be seen in FIG. 3, which illustrates the coefficient of absorption (in cm 1) of SiGe as a function of wavelength (in μm) for different compositions of the material, the coefficient of absorption, notably in the infrared, increases with the germanium content.

(21) However, the design of the active layer 3 does not only concern the concentration of germanium but also the thickness of the layer. Indeed, since the SiGe layer is formed by epitaxy on a silicon substrate, the lattice parameter of which is different from that of silicon-germanium, relaxation of the SiGe layer takes place beyond a certain thickness known as the “critical thickness.” This relaxation results in the formation of dislocations within the SiGe layer.

(22) Such dislocations would make the SiGe layer inappropriate for the function of the active layer 3 and, thus, must be avoided.

(23) As shown in FIG. 4, which illustrates the critical thickness (in Å) of a SiGe layer as a function of the germanium content (stoichiometric coefficient x corresponding to the composition Si.sub.1-xGe.sub.x), the critical thickness is becomes smaller with increasing germanium concentration.

(24) The thickness of the active layer 3 and the germanium concentration of the layer thus result from a compromise between: on the one hand, a sufficiently large thickness to capture a maximum of photons in the wavelengths of the near infrared region of the electromagnetic spectrum, on the other hand, a sufficient concentration of germanium to increase the capacity to absorb photons by the active layer, in particular, in the near infrared region; and a limited thickness (dependent on the concentration) to avoid silicon-germanium relaxation and the creation of crystalline defects (dislocations) that result therefrom.

(25) Typically, it is sought to maximize the thickness and the germanium concentration of the active layer 3 in order to have the best possible absorption in the infrared region.

(26) Preferably, the germanium content of the active layer is less than or equal to 10%. FIG. 4 shows that the critical thickness of a Si.sub.0.9Ge.sub.0.1 layer is on the order of a micrometer, which is suitable for the active layer of a “front side” type imager.

(27) FIG. 5 illustrates the bow z (in μm) of a silicon substrate of 300 mm diameter and having a thickness of 775 μm as a function of the thickness x (in μm) of a SiGe layer deposited by epitaxy on the substrate, and the stress y (in GPa) in the SiGe layer, the stress depending on the germanium content and the thickness of the SiGe layer.

(28) Thus, for example, a SiGe layer having a thickness of 5 μm induces a stress of 0.1 GPa, which causes a bow on the order of +300 m.

(29) The silicon oxide layer 4 arranged on the rear side of the support substrate 1 makes it possible to compensate the deformation induced by the stress of the active layer.

(30) As will be seen below in the description of embodiments of the method of manufacturing the structure, the silicon oxide layer is deposited on the support substrate before epitaxy of the SiGe layer, at a sufficiently low temperature so as not to significantly deform the structure before the epitaxy step. Thus, the structure can still be handled by conventional industrial tools throughout its method of manufacture.

(31) Examples of methods of manufacturing the structure illustrated in FIG. 2 will now be described.

(32) Generally speaking, the method of manufacturing the structure comprises the following steps.

(33) A donor substrate is supplied comprising a semiconductor material suitable for the epitaxial growth of silicon-germanium. The material may notably be SiGe (enabling homoepitaxy) or a material different from SiGe but having a lattice parameter sufficiently close to that of SiGe to enable the epitaxial growth thereof (heteroepitaxy). In this latter case, the semiconductor material may be silicon.

(34) A receiver substrate is also supplied, and the donor substrate is bonded on the receiver substrate, an electrically insulating layer being present at the bonding interface between the receiver substrate and the donor substrate.

(35) The donor substrate is then thinned so as to transfer a layer of the semiconductor material onto the receiver substrate.

(36) This thinning may be carried out by polishing or etching of the semiconductor material so as to obtain the thickness and the surface state desired for the epitaxy of SiGe.

(37) However, before the bonding step, an embrittlement zone may be formed in the semiconductor material so as to delimit a superficial layer to be transferred to the receiver substrate. After the bonding step, the thinning step involves detaching the donor substrate along the embrittlement zone, which leads to the transfer of the superficial layer onto the receiver substrate. Typically, the thickness of the transferred layer is less than or equal to 400 nm. Potentially, a finishing treatment of the free surface of the transferred layer is carried out in order to favor the implementation of the epitaxy, this treatment leading to thinning of the transferred layer.

(38) Next, a silicon oxide (SiO.sub.2) layer is deposited on the rear side of the receiver substrate. Such a deposition is implemented at a relatively low temperature, substantially less than the epitaxy temperature required to for the subsequent growth of the monocrystalline SiGe layer. Typically, the deposition temperature of the oxide layer is on the order of 300° C., more generally between 100 and 400° C. The techniques for carrying out such a deposition are known, and may be include PECVD (Plasma-Enhanced Chemical Vapor Deposition) for example.

(39) Considering that the coefficient of thermal expansion of silicon oxide is constant as a function of temperature, the stress induced by the deposition of the layer on the receiver substrate results, after returning to room temperature, in a bow of 6 μm for 1000 Å deposited at 300° C., the bow being 18 μm for 1000 Å deposited at 950° C.

(40) The thickness of the deposited silicon oxide layer is chosen so that the bow obtained after returning to room temperature is less than or equal to a limit value, for example, less than or equal to 100 μm, which makes it possible to handle and to measure the structure with standard microelectronic equipment. This thickness of the silicon oxide layer is typically between 0.5 μm and 4 μm.

(41) Finally, on the transferred layer of semiconductor material, which serves as seed layer, the epitaxial growth of a silicon-germanium layer is implemented until the desired thickness for the active layer is obtained. This epitaxy is typically carried out at a temperature on the order of 900° C., more generally between 600 and 1100° C.

(42) Since the epitaxy is carried out at a temperature close to the glass transition temperature of the silicon oxide layer situated on the rear side, the silicon oxide layer creeps during the epitaxy, which reduces the stress created by the layer. On the other hand, in so far as the layer has been taken to a temperature three times greater than that of its deposition, the stress created during its post-epitaxy cooling is also around three times greater than that created during its cooling following its deposition.

(43) Consequently, the deposition of the SiGe layer induces a double phenomenon: a positive variation of the bow, linked to the stress created by the SiGe on the front side; and a negative variation of the bow, induced by the stress created by the silicon oxide on the rear side.

(44) On returning to room temperature, the two variations offset one another, making it possible to benefit from an SOI or SiGeOI structure covered by a thick non-deformed SiGe layer.

(45) Thereafter, since the processing steps to which the structure is subjected in the manufacture of the imager or another electronic, optic or optoelectronic component are implemented at temperatures below the SiGe epitaxy temperature, the structure will become substantially flat upon returning to room temperature.

(46) It will be noted that, when the seed layer is not made of SiGe, such as when it is made of silicon, the seed layer remains under the active layer 3 at the end of the SiGe epitaxy.

(47) This situation is illustrated in FIG. 6, which corresponds to one particular embodiment of the present disclosure. The seed layer is designated by the reference numeral 42.

(48) The seed layer is sufficiently thin (of a thickness less than or equal to 300 nm) compared to the thickness of the active layer so as not to significantly affect the properties of the active SiGe layer in terms of absorption in the infrared region.

(49) However, it is possible to remove the seed layer, for example, by means of a condensation method. In a known manner, the method may comprise an oxidation of the SiGe layer, the oxidation having the effect of consuming the silicon (to form silicon oxide) and to make the germanium migrate to the face opposite to the free surface of the SiGe layer. A SiO.sub.2 layer, which can be removed by etching, is then obtained on the surface.

(50) According to a first embodiment, illustrated in FIGS. 7A to 7F, the starting point is a donor substrate 30 comprising a superficial SiGe layer 31.

(51) The SiGe layer is typically formed by epitaxy on a base substrate 32, which may be made of silicon. The SiGe layer is sufficiently thin to be stressed.

(52) In a first version of this embodiment, an embrittlement zone is formed in the SiGe layer.

(53) In a particularly advantageous manner, as illustrated in FIG. 7B, the embrittlement zone 33 is formed by implantation of atomic species (typically, hydrogen and/or helium) through the free surface of the SiGe layer 31. The embrittlement zone 33 thereby delimits a SiGe layer 34 at the surface of the donor substrate.

(54) With reference to FIG. 7C, a receiver substrate is also supplied that includes a support substrate 1 and an electrically insulating layer 2.

(55) With reference to FIG. 7D, the donor substrate is bonded to the receiver substrate, the SiGe layer 31 and the electrically insulating layer 2 being at the bonding interface.

(56) Next, as illustrated in FIG. 7E, the donor substrate is detached along the embrittlement zone. The detachment may be initiated by any known technique, such as by application of mechanical, chemical, and/or thermal stress.

(57) The SiGe layer 34 is thereby transferred onto the support substrate.

(58) With reference to FIG. 7F, a silicon oxide layer 4 is deposited at low temperature (on the order of 300° C.) on the rear side of the support substrate 1. As indicated above, the thickness of the layer 4 is chosen so as not to generate a bow greater than 100 μm upon returning to room temperature, and to compensate the bow generated by the later epitaxy of the SiGe layer. The thickness of the layer 4 is, for example, on the order of 1.4 μm.

(59) If need be, a surface treatment of the SiGe layer is carried out to remove defects linked to the implantation and to the detachment, and to make it sufficiently smooth for the subsequent epitaxy step (cf. FIG. 7H described below).

(60) In a second version of this embodiment, an embrittlement zone 33 is formed in the donor substrate 30 situated under the SiGe layer 31 (cf FIG. 8A).

(61) In a particularly advantageous manner, the embrittlement zone 33 is formed by implantation of atomic species (typically, hydrogen and/or helium) through the free surface of the donor substrate 30. The embrittlement zone 33 thus delimits a SiGe layer and a portion 38 of the base substrate 32 at the surface of the donor substrate.

(62) A receiver substrate comprising a support substrate 1 and an electrically insulating layer 2 (cf. FIG. 7C) is also provided.

(63) With reference to FIG. 8B, the donor substrate is bonded to the receiver substrate, the SiGe layer 31 and the electrically insulating layer 2 being at the bonding interface.

(64) Next, the donor substrate is detached along the embrittlement zone 33. The detachment may be initiated by any known technique, such as by application of mechanical, chemical, and/or thermal stress.

(65) The SiGe layer 31 and the portion 38 of the base substrate are thereby transferred onto the support substrate (cf. FIG. 8C).

(66) A treatment of the surface created is then carried out to remove the portion 38 of the superficial donor substrate until a surface of SiGe is revealed, thereby removing defects linked to the implantation and to the detachment, and making it sufficiently smooth for the subsequent epitaxy process.

(67) As in FIG. 7E, a portion 38 of the SiGe layer 31 on the support substrate 1 is thereby obtained.

(68) With reference to FIG. 7F, a silicon oxide layer 4 is deposited at low temperature (on the order of 300° C.) on the rear side of the support substrate 1. As indicated above, the thickness of the layer 4 is chosen so as not to generate a bow greater than 100 μm upon return to room temperature, and to compensate the bow generated by the later epitaxy of the SiGe layer. The thickness of the layer 4 is, for example, on the order of 1.4 μm.

(69) As illustrated in FIG. 7G (step common to both versions of the embodiment), epitaxy is then performed in order to make a SiGe layer 35 grow on the transferred layer 34, which fulfils the role of a seed layer, until the desired thickness for the active layer 3 is obtained, which is includes both of the two SiGe layers 34 and 35. During epitaxy, it is possible to lightly dope the layer 35, according to the desired electrical properties. The doping of the layer 35 is not necessarily identical to that of the seed layer 34.

(70) During this epitaxy, which is carried out at a temperature between, for example, 900° C. and 950° C., the oxide of the layer 4 creeps and relaxes the stress within the structure.

(71) On the other hand, during the return to room temperature after the epitaxy, the oxide layer 4 causes a stress that compensates the stress imposed by the SiGe layer deposited in the front side.

(72) The structure illustrated in FIG. 2 is thereby obtained, which may be free of bow or may have a bow that is at least sufficiently low to enable handling of the structure by conventional tools in the microelectronics industry.

(73) According to a second embodiment, illustrated in FIGS. 9A to 9D, the well-known SMARTCUT™ method is used to form an SOI substrate comprising the support substrate, the electrically insulating layer, and a silicon seed layer intended for the epitaxial growth of the SiGe layer.

(74) To this end, a donor silicon substrate 40 covered by the electrically insulating layer 2 (cf. FIG. 9A) is supplied, then an embrittlement zone 41 delimiting a silicon layer 42 to be transferred (cf. FIG. 9B) is formed by implantation of atomic species.

(75) A receiver substrate, which is typically the support substrate 1 of the final substrate, is also provided.

(76) With reference to FIG. 9C, the donor substrate 40 is bonded to the support substrate 1, the electrically insulating layer 2 being at the bonding interface.

(77) Next, the donor substrate is detached along the embrittlement zone. The detachment may be initiated by any known technique, such as by application of mechanical, chemical and/or thermal stress.

(78) The silicon layer 42 is thereby transferred onto the support substrate 1 (cf. FIG. 9D).

(79) With reference to FIG. 9E, a silicon oxide layer 4 is deposited at low temperature (on the order of 300° C.) on the rear side of the support substrate 1. As indicated above, the thickness of the layer 4 is chosen so as not to generate a bow greater than 100 μm upon return to room temperature, and to compensate the bow generated by the later epitaxy of the SiGe layer. The thickness of the layer 4 is, for example, on the order of 1.4 μm.

(80) If need be, a surface treatment of the silicon layer may be performed to remove defects linked to the implantation and to the detachment, and to make it sufficiently smooth for the subsequent epitaxy process.

(81) Finally, epitaxy of SiGe on the transferred silicon layer 42, which serves as a seed layer is then resumed, until the desired thickness for the active layer 3 is obtained. During epitaxy, it is possible to lightly dope the active layer 3, depending on the desired electrical properties.

(82) The substrate illustrated in FIG. 6 is thereby obtained.

(83) As mentioned above, the silicon seed layer may be kept for the formation of the imager. Alternatively, the silicon layer may be removed by means of the aforesaid condensation method.

(84) FIG. 10 illustrates a part of a front side type imager comprising a substrate according to one embodiment of the present disclosure corresponding to FIG. 2, but not limited thereto. Only a part of the imager corresponding to a pixel is represented in this figure, the pixel being electrically insulated from the other pixels formed in the active layer 3 by insulation trenches 7.

(85) A doped region 36 of a different type from that of the active layer 3 is formed under the surface of the front side of the active layer 3. This region 36 forms the active layer 3 of a photodiode. A region 37 formed between the region 36 and the front side of the active layer 3 advantageously has a doping level greater than that of the region 36 in order to passivate the interface. A passivation layer 6 is formed on the active layer 3 and may encapsulate elements making it possible to electrically control the pixel.

(86) Potentially, other layers, such as filters, may be formed on the passivation layer 6, but they are not represented in FIG. 10.

(87) The structure of the active components of the imager and the methods of manufacturing such components are known in the art and are thus not described in detail herein.