MEASURING CIRCUIT FOR REGISTERING AND PROCESSING SIGNALS AND MEASURING DEVICE FOR USING SAID MEASURING CIRCUIT

Abstract

A measuring circuit for registering and processing signals received from a transducer having a plurality of transducer elements includes a first signal input, a second signal input and a third signal input. The first signal input is configured to receive a first signal from a first transducer element. The second signal input is configured to receive a first signal from a second transducer element. The third signal input is configured to receive a second signal sum indicative of a sum of a second signal from each of the plurality of transducer elements, each of the second signals being an inverse of a corresponding first signal. A processor is electrically coupled to the three signal inputs and is configured to register each of the first signals individually; register the second sum signal; and generate a differential signal based on the first and second signals.

Claims

1-15. (canceled)

16. A measuring circuit for registering and processing signals received from a transducer having a plurality of transducer elements, the measuring circuit comprising: at least a first signal input, a second signal input and a third signal input, the first signal input configured to receive a first signal from a first transducer element of the plurality of transducer elements, the second signal input configured to receive a first signal from a second transducer element of the plurality of transducer elements, the third signal input configured to receive a second signal sum indicative of a sum of a second signal from each of the plurality of transducer elements, each of the second signals being an inverse of a corresponding first signal; and a processor electrically coupled to the first signal input, the second signal input and the third signal input, the processor configured to: register each of the first signals individually; register the second sum signal; and generate at least one differential signal based, at least in part, on one of the first signals and one of the second signals.

17. The measuring circuit of claim 16, wherein the processor is further configured to: add the first signals together to obtain a first signal sum; add the first signal sum and the second signal sum to obtain an interference signal.

18. The measuring circuit of claim 17, wherein the processor is further configured to: subtract a portion of the interference signal from each of the first signals to obtain a plurality of interference-corrected first signals; and subtract the portion of the interference signal from the second signal sum to obtain an interference-corrected second signal sum.

19. The measuring circuit of claim 18, wherein the processor is further configured to: generate a proportional interference signal based, at least in part, on a total number of signal inputs of the measuring circuit; and subtract the proportional interference signal from the at least one differential signal to obtain at least one interference-corrected differential signal.

20. The measuring circuit of claim 16, further comprising: a fourth signal input, the fourth signal input configured to receive a first signal from a third transducer element of the plurality of transducer elements.

21. The measuring circuit of claim 20, wherein the processor is configured to: generate a first differential signal based, at least in part, on the second signal sum and the first signal received from the first transducer element; generate a second differential signal based, at least in part, on the second signal sum and the first signal received from the second transducer element; generate a third differential signal based, at least in part, on the second signal sum and the first signal received from the third transducer element of the plurality of transducer elements; and determine an interference signal based, at least in part, on the second signal sum, the first signal received from the first transducer, the first signal received from the second transducer, and the first signal received from the third transducer.

22. The measuring circuit of claim 21, wherein the processor is further configured to: generate a proportional interference signal based, at least in part, on a total number of signal inputs of the measuring circuit; subtract the proportional interference signal from each of the first differential signal, the second differential signal and the third differential signal to obtain an interference-corrected first differential signal, an interference-corrected second differential signal, and an interference-corrected third differential signal.

23. A measuring device comprising: a transducer comprising a plurality of transducer elements, each of the transducer elements comprising a first contact and a second contact, the first contact configured to output a first signal, the second contact configured to output a second signal, the second signal being an inverse of the first signal; an adder, the adder configured to add the second signals together to obtain a second signal sum; and a measuring circuit electrically coupled to the transducer via a cable, the measuring circuit comprising: at least a first signal input, a second signal input and a third signal input, the first signal input configured to receive the first signal from a first transducer element of the plurality of transducer elements, the second signal input configured to receive the first signal from a second transducer element of the plurality of transducer elements, the third signal input configured to receive the second signal sum; and a processor electrically coupled to the first signal input, the second signal input and the third signal input, the processor configured to: register each of the first signals individually; register the second sum signal; generate at least one differential signal based, at least in part, on one of the first signals and one of the second signals; add the first signals together to obtain a first signal sum; add the first signal sum and the second signal sum to obtain an interference signal.

24. The measuring device of claim 23, wherein the adder is positioned inside the transducer.

25. The measuring device of claim 23, wherein the adder is positioned within a plug of the cable.

26. The measuring device of claim 23, wherein a magnitude of the interference signal corresponds to an input of an interference into the cable or the transducer.

27. The measuring device of claim 23, wherein each of the first signals and each of the second signals is indicative of a current, a voltage, or a charge.

28. The measuring device of claim 23, wherein the transducer is configured to detect at least one of an acceleration, a force, or a pressure.

29. The measuring device of claim 28, wherein at least one of the transducer elements is a piezoelectric transducer element.

30. A method for detecting at least two measured variable in an interference-free manner, the method comprising: obtaining, by a measuring circuit, a first signal output by each of a plurality of transducer elements of a transducer electrically coupled to the measuring circuit; obtaining, by the measuring circuit, a second signal sum from the transducer, the second signal sum indicative of a sum of a second signal output by each of the plurality of transducer elements, the second signal being an inverse of the first signal; adding, by the measuring circuit, each of the first signals together to obtain a first signal sum; determining, by the measuring circuit, an interference signal based, at least in part, on the first signal sum and the second signal sum, the interference signal indicative of an external electromagnetic interference of the first signals and the second signals or the second signal sum.

31. The method of claim 30, further comprising: subtracting, via the measuring circuit, a portion of the interference signal from each of the first signals to obtain a plurality of interference-corrected first signals; and subtracting, via the measuring circuit, the portion of the interference signal from the second signal sum to obtain an interference-corrected second signal sum.

32. The method of claim 31, further comprising: calculating, via the measuring circuit, at least one differential signal based, at least in part, on the second signal sum and the first signals, the at least one differential signal corresponding to a difference between the first signal output by a first transducer element and the second signal output by the first transducer element; and subtracting, via the measuring circuit, at least a portion of the interference signal from the at least one differential signal such that an existing interference signal is eliminated from the at least one differential signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the following, the invention will be explained by way of example referring to the figures in which

[0026] FIG. 1 shows a schematic partial view of an embodiment of the measuring circuit for a number N of first signals,

[0027] FIG. 2 shows a schematic partial view of an embodiment of a measuring device comprising the measuring circuit of FIG. 1, a cable and a transducer,

[0028] FIG. 3 shows a schematic partial view of an embodiment of the measuring circuit for 2 first signals,

[0029] FIG. 4 shows a schematic partial view of an embodiment of the measuring circuit for 3 first signals,

[0030] FIG. 5 shows a schematic partial view of an embodiment of a measuring device comprising the measuring circuit of FIG. 1, a cable and a transducer,

[0031] FIG. 6 shows a schematic partial view of an embodiment of a measuring device comprising the measuring circuit of FIG. 1, a cable and a transducer,

[0032] FIG. 7 shows a schematic partial view of an embodiment of a measuring device comprising the measuring circuit of FIG. 1, a cable and a transducer,

[0033] FIG. 8 shows a schematic representation of an example with three first signals of the first signals and of the second signal sum both overlaid with an interference signal as provided at the signal inputs,

[0034] FIG. 9 shows a schematic representation of an example with three first signals of the first signals and of the second signal sum both overlaid with an interference signal, the first signal sum as well as the detected interference signal within the measuring circuit,

[0035] FIG. 10 shows a schematic representation of an example with three first signals of the first signals and of the second signal sum both overlaid with an interference signal, the first signal sum, the detected interference signal, a differential signal, and an interference-corrected differential signal.

DETAILED DESCRIPTIONS OF EXEMPLARY EMBODIMENTS

[0036] FIG. 1 shows a schematic partial view of the measuring circuit 3 comprising a number N of signal inputs 36 and an additional signal input 36. Signal inputs 36 are configured to register and provide a number N of first signals S1.1 to S1.N and to register and provide a sum S2 of second signals S2.1 to S2.N wherein the number N is a natural number greater than one.

[00001]$S2=\underset{n=1}{\overset{N}{.Math.}}S2.n$

[0037] Regarding the first signals S1.1 to S1.N and the second signals S2.1 to S2.N, a first signal S1.1 to S1.N corresponds to the negative value of a second signal S2.1 to S2.N for each value of the signal in the case of no interference:

S1.n=−S2.n∀n∈[1,N]

[0038] A variation of the first signal S1.1 to S1.N is accompanied by an equal but opposite variation of the second signal S2.1 to S2.N.

[0039] In the case considered, the reference potential at which a first signal and a second signal are negated with respect to one another is equal to zero. In the case of a reference potential different from zero the above and the following formulas must be adapted accordingly.

[0040] The first signals S1.1 to S1.N and the sum S2 of the second signals S2.1 to S2.N are each transmitted by a conductor 21 to a signal input 36 of the measuring circuit 3.

[0041] FIG. 3 exemplarily shows a measuring circuit comprising three signal inputs and which is therefore adapted to register two first signals S1.1 and S1.2 as well as the second signal sum S2.

[0042] FIG. 4 exemplarily shows a measuring circuit comprising four signal inputs and which is therefore adapted to register three first signals S1.1 to S1.3 as well as the second signal sum S2.

[0043] In the case of an interference this interference will affect each of the provided first signals S1.1 to S1.N and the provided second signal sum S2 to an equal amount, said interference being in phase. Therefore and as schematically shown in FIG. 8, at each signal input 36 of the measuring circuit 3 a proportion of an interference signal St caused by the interference will be additively overlaid on a first signal S1.1 to S2.N or the second signal sum S2, respectively. The proportion 1/(N+1) of the overlaid interference signal St is given by the number of signal inputs 36 of the measuring circuit 3.

[0044] The first signals S1.1 to S1.N with the overlaid proportional interference signal St/(N+1) are added up within the measuring circuit 3 and the result is provided as the first signal sum S1, as shown in FIG. 9.

[00002]$S1=\underset{n=1}{\overset{N}{.Math.}}\left(S1.n+\frac{\mathrm{St}}{N+1}\right)$

[0045] The interference signal St may be determined by adding up the first signal sum S1 and the second signal sum S2 wherein the second signal sum S2 is additionally overlaid by the proportional interference signal St/(N+1). Therefore, the second signal sum S2 is given by the ideal interference-free second signal sum S2′ and the interference signal St/(N+1).

[00003]$S2=S{2}^{\prime }+\frac{St}{N+1}$

[0046] Thus, the interference signal St is determined by:

[00004]$\left(S1\right)+\left(S2\right)=\left(\underset{n=1}{\overset{N}{.Math.}}\left(S1.n+\frac{St}{N+1}\right)\right)+\left(\left(\underset{n=1}{\overset{N}{.Math.}}S2.n\right)+\frac{St}{N+1}\right)==\left(N*\frac{St}{N+1}+\underset{n=1}{\overset{N}{.Math.}}\left(S1.n\right)\right)+\left(\left(\underset{n=1}{\overset{N}{.Math.}}S2.n\right)+\frac{St}{N+1}\right)==N*\frac{St}{N+1}+\frac{St}{N+1}+\underset{n=1}{\overset{N}{.Math.}}\left(S1.n+S2.n\right)=N*\frac{St}{N+1}+\frac{St}{N+1}=St$

[0047] The total interference signal St may, thus, be determined from the first signals S1.1 to S1.N and the second signal sum S2 provided at the signal inputs 36 together with the respective overlaid proportional interference signal St/(N+1). The interference signal is exemplarily shown in FIG. 9.

[0048] When the interference signal is known, the respective proportion of the interference signal may simply be subtracted from the first signals S1.1 to S1.N and the second signal sum S2 provided at the signal inputs 36 in an arithmetic element. The resulting interference-corrected first signals Sb1.1 to Sb1.N and interference-corrected second signal sum Sb2 are shown in FIGS. 1 to 7.

[0049] Adding up the first signals S1.1 to S1.N to obtain a first signal sum S1 is done by means of an adder 31. The adder 31 is arranged in the measuring circuit 3. Similarly, adding up the first signal sum S1 and the second signal sum S2 is also done by means of an adder 31. Components which add two or more signals are known to persons skilled in the art in the field of electrical engineering. Thus, adding up digital signals is for example performed by means of microprocessors. The adding up of analog signals is performed in the simplest case, for example for charges or currents, by means of a conductive connection between two conductors.

[0050] A differential signal D.1 to D.N of a first signal S1.1 to S1.N and a second signal S2.1 to S2.N is calculated from the provided first signals S1.1 to S1.N and the second signal sum S2. For this purpose, all first signals except the first signal S1.k, k being in the range from 1 to N including the limits, for which the differential signal D.1 to D.N is to be calculated are added to the second signal sum S2. Moreover, overlaid on the first signals S1.1 to S1.N and the second signal sum S2, respectively, is still the proportional interference signal St/(N+1).

[00005]$\left(S2\right)+\left(\underset{n=1⩓n\ne k}{\overset{N}{.Math.}}\left(S1.n+\frac{St}{N+1}\right)\right)==\left(\left(\underset{n=1}{\overset{N}{.Math.}}S2.n\right)+\frac{St}{N+1}\right)+\left(\left(N-1\right)*\frac{St}{N+1}+\left(\underset{n=1⩓n\ne k}{\overset{N}{.Math.}}S1.n\right)\right)==\frac{St}{N+1}+\left(N-1\right)*\frac{St}{N+1}+\left(\underset{n=1}{\overset{N}{.Math.}}S2.n\right)+\left(\underset{n=1⩓n\ne k}{\overset{N}{.Math.}}S1.n\right)==\frac{St}{N+1}+\left(N-1\right)*\frac{St}{N+1}+\left(\underset{n=1}{\overset{N}{.Math.}}S2.n\right)+\left(\underset{n=1⩓n\ne k}{\overset{N}{.Math.}}S1.n\right)=N*\frac{St}{N+1}S2.k$

[0051] After which the difference from the first signal S1.k, k1 from 1 to N, is calculated.

[00006]$\left(N*\frac{St}{N+1}S2.k\right)-\left(S1.k+\frac{St}{N+1}\right)=\frac{N-1}{N+1}*St*\left(S2.k-\mathrm{S1}.k\right)=D.k$

[0052] A known proportion (N−1)/(N+1) of the differential signal D.1 to D.N consists of the interference signal St. This proportion is known and the interference signal St has already been determined so that the differential signal D.1 to D.N may be corrected by eliminating the proportion of the interference St from the differential signal D.1 to D.N.

[00007]$D.k-\frac{N-1}{N+1}St=Db.k,$

k being in the range from 1 to N including the limits

[0053] The interference-corrected differential signal Db.1 to Db.N is free from the interference signal St that affected the signals. Afterwards, interference-corrected differential signals Db.1 to Db.N may be determined for all first signals S1.1 to S1.N. The differential signal D.1 to D.N and the interference-corrected differential signal Db.1 to Db.N are exemplarily shown in FIG. 10.

[0054] In one embodiment, measuring circuit 3 includes analog-to-digital converters which digitize each first signal S1.1 to S1.N as well as the sum S2 of the second signals. The term first signal S1.1 to S1.N or second signal S2.1 to S2.N is independent of whether a signal exists in the measuring circuit 3 in analog or digital form. Operations within measuring circuit 3 may either be performed by digital signal processing or analog signal processing. Thus, the adder 31 adapted to add two signals is realized either by a microprocessor or by a suitable analog circuit. Likewise, the arithmetic element 33 which relates a plurality of signals to each other by means of addition, subtraction, division or multiplication is realized either by a microprocessor or by a suitable analog circuit.

[0055] In one embodiment, each signal input 36 is connected in an electrically conductive manner to a respective amplifier 32, said amplifier 32 being arranged within the measuring circuit 3 as shown in FIGS. 1 to 4. An amplifier 32 comprises at least two signal inputs of which a first one is connected in an electrically conductive manner to the signal input 36 of the measuring circuit 3. A second signal input of the amplifier 32 is connected to a reference potential 34. In one embodiment, the amplifier 32 may also include an analog-to-digital converter. An arrangement of the amplifier 32 in the proximity of a signal input 36 is advantageous for further signal processing within the measuring circuit 3 which for an amplified signal is less susceptible to interference.

[0056] In one embodiment, amplifier 32 converts the physical variable of a first signal S1.1 to S1.N and the second signal sum S2 into another physical variable. For a first signal S1.1 to S1.N and the second signal sum S2 that are a charge, for example, the amplifier thus preferably converts said charge into a voltage or current. This voltage or current is still called the first signal S1.1 to S1.N or second signal sum S2, respectively, regardless of the physical variable. The term first signal S1.1 to S1.N or second signal sum S2 is independent of the physical variable by which the first signal or the second signal sum is represented or into which physical variable the first signal S1.1 to S1.N or second signal sum S2 may be converted within the measuring circuit 3.

[0057] In one embodiment, no amplifier 32 is required in the measuring circuit 3 due to the nature of the first signals S1.1 to S1.N and the second signal sum S2, as shown in FIGS. 5 to 7.

[0058] Advantageously, measuring circuit 3 is used together with a suitable transducer 1 as well as a cable 2 that connects the transducer 1 and measuring circuit 3. Such an arrangement of transducer 1, cable 2 and measuring circuit 3 is referred to as a measuring device 123. A measuring device 123 is exemplarily shown in FIG. 2.

[0059] A transducer 1 registers at least one physical variable. For this purpose, at least one transducer element 10 is arranged in transducer 1 which registers the physical variable and carries a first contact 12 and a second contact 13. Transducer element 10 provides a first signal S1. to S1.N at the first contact 12 and a second signal S2.1 to S2.N at the second contact 13. A signal is for example a voltage or a current or a charge. A physical variable is, for example, a force, a pressure, an acceleration, a torque, a voltage, a current, a charge, a temperature, a magnetic flux density, photometric variables or any other physical variable.

[0060] In one embodiment, the transducer 1 is a multi-axis piezoelectric force transducer or a multi-axis piezoelectric acceleration transducer.

[0061] According to the invention, the second signals S2.1 to S2. N of the transducer elements 10 are added up by means of adders 11 to obtain a second sum S2. The structure of an adder 11 is dependent on the physical variable of the second signals S2.1 to S2.N. Thus, an adder 11 for a current or a charge may be an electrically conductive connection. However, more complex circuits that enable the addition of the second signals S2.1 to S2.N are also conceivable.

[0062] In one embodiment, the adders 11 are disposed within a transducer 1 as shown in FIGS. 2, 5 and 6. This has the advantage that a cable 2 connecting said transducer 1 to the measuring circuit 3 in an electrically conductive manner requires less conductors than in a case where all first and second signals are transmitted separately through the cable.

[0063] In one embodiment, the adders 11 are arranged within the plug of the cable 2 on the side of the transducer, as shown in FIG. 7. The plug of the cable 2 on the side of the transducer is the plug which connects the cable 2 to the transducer 1. This has the advantage that also transducers 1 that do not meet the requirements of combining the second signals may be used in a measuring device 123 with the measuring circuit 3. The adders 11 must be located close to the transducer, in particular in the plug on the side of the transducer, so that in the case of an interference an equal proportion of this interference will impact the provided first signals S1.1 to S1.N and the provided second signal sum S2, respectively, wherein said interference is in phase. When the connection between the cable 2 and the transducer 1 is made without a plug, then the adders 11 are to be incorporated into the cable 2 in very close proximity to the transducer 1 to ensure that an equal proportion of the interference impacts the provided first signals S1.1 to S1.N and the provided second signal sum S2, respectively, wherein said interference is in phase. In close proximity refers to a distance of less than 10% of the total length of the cable 2 between the transducer 1 and the measuring circuit 3.

[0064] In one embodiment, the adders 11 comprise an amplifier or an analog-to-digital converter, or both.

[0065] In one embodiment, conductors 21 of the cable 2 and contacts 12, 13 of the transducer 1 are connected in an electrically conductive manner by plug contacts 16, as shown in FIG. 5.

[0066] A plug contact consists of a plug and a socket of which one is present on the cable 2 and the respective other on the transducer and it serves to connect a conductor 21 of the cable 2 and a contact of the transducer 1 to one another in an electrically conductive manner.

[0067] In one embodiment, the cable 2 is non-detachably connected to the transducer 1, and the first contacts 12 and second contacts 13 are connected to the conductors 21 of the cable 2 by a material bond or a force-locked connection, as shown in FIGS. 2 and 6.

[0068] In one embodiment, the signal inputs 36 of the measuring circuit 3 are designed as plug contacts which connect the conductors 21 of the cable 2 to the measuring circuit 3 in an electrically conductive manner, as shown in FIGS. 1 to 5.

[0069] In one embodiment, the signal inputs 36 of the measuring circuit 3 are designed in a way that the cable 2 is non-detachably connected to the measuring circuit 3 and the conductors 21 of the cable 2 are connected to the signal inputs 36 of the measuring circuit 3 via a material bond or a force-locked connection, as shown in FIGS. 6 and 7.

[0070] In one embodiment (not shown) a plurality of transducers 1 are connected to the measuring circuit 3 in a way that the second signals S2.1 to S2.N of the transducer elements 10 located in different transducers 1 are combined in an additive manner. This may for example be an arrangement of a plurality of pressure transducers in a fluid system. These pressure transducers may be connectable to a cable 2 by a common plug contact, for example, and the second signals S2.1 to S2.N may be combined in the cable 2 in an additive manner. These pressure transducers may be piezoelectric or piezoresistive pressure transducers or ionization vacuum gauges or thermal conductivity vacuum gauges. Other applications in which transducer elements 10 are arranged in different transducers 1 are also conceivable.

[0071] An embodiment is also possible which combines various features of the embodiments disclosed in this document, provided this is feasible.

LIST OF REFERENCE NUMERALS

[0072] 1 transducer [0073] 2 cable [0074] 3 measuring circuit [0075] 10 transducer element [0076] 11 adder [0077] 12 first contact [0078] 13 second contact [0079] 16 signal output [0080] 21 conductor [0081] 31 adder [0082] 32 amplifier [0083] 33 arithmetic element [0084] 34 reference potential [0085] 36 signal input [0086] 123 measuring device [0087] St interference signal [0088] N number of transducer elements [0089] S1.1 to S1.N first signal of a transducer element [0090] S2.1 to S2.N second signal of a transducer element [0091] S1 first signal sum [0092] S2 second signal sum [0093] S2′ interference-free second signal sum [0094] Sb2 interference-corrected second signal sum [0095] Sb1.1 to Sb1.N interference-corrected first signal [0096] D.1 to D.N differential signal of a transducer element [0097] Db.1 to Db.N interference-corrected differential signal of a transducer element