Nitride semiconductor substrate, manufacturing method therefor, and semiconductor device

Abstract

Provided is a technique for manufacturing a nitride semiconductor substrate with which it is possible to manufacture a nitride semiconductor substrate having sufficiently reduced dislocation density with a large area even if manufactured on an inexpensive substrate made of sapphire, etc. A nitride semiconductor substrate in which a nitride semiconductor layer formed on a substrate is formed by laminating an undoped nitride layer and a rare earth element-added nitride layer to which a rare earth element is added as a doping material, and the dislocation density is of the order of 106 cm−2 or less. A method for manufacturing a nitride semiconductor substrate in which a step for growing GaN, InN, AlN, or a mixed crystal of two or more thereof on a substrate to form an undoped nitride layer, and a step for forming a rare earth element-added nitride layer to which a rare earth element is added so as to be substituted for Ga, In, or Al are performed via a series of formation steps using an organic metal vapor epitaxial technique at a temperature of 900 to 1200° C. without extraction from a reaction vessel.

Claims

1. A nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, wherein an undoped nitride layer having the thickness of 0.1 to 50 nm to which doping material is not doped and a rare earth element-doped nitride layer having the thickness of 0.1 to 2000 nm to which a rare earth element is doped as a doping material are stacked once to form the nitride semiconductor layer, and the threading dislocation density on the surface of the nitride semiconductor layer is at the order of 10.sup.6 cm.sup.−2 or less.

2. The nitride semiconductor substrate according to claim 1, wherein the nitride in the nitride semiconductor layer is GaN, InN, AlN or a mixed crystal of any two or more of them.

3. The nitride semiconductor substrate according to claim 1, wherein the rare earth element is Eu.

4. The nitride semiconductor substrate according to claim 3, wherein the doped amount of the Eu is 0.01 to 2 atomic %.

5. The nitride semiconductor substrate according to claim 1, wherein the total thickness is 3 μm or less.

6. The nitride semiconductor substrate according to claim 1, wherein the base material is any one of sapphire, SiC, Si and GaN.

7. A semiconductor device which is produced using the nitride semiconductor substrate according to claim 1.

8. The semiconductor device according to claim 7, which is any one of a light emitting device, a high frequency device, and a high power device.

9. A nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, wherein an undoped nitride layer having the thickness of 0.1 to 50 nm to which doping material is not doped and a rare earth element-doped nitride layer having the thickness of 0.1 to 200 nm to which a rare earth element is doped as a doping material are stacked a plurality of times to form the nitride semiconductor layer with a super lattice structure, and the threading dislocation density on the surface of the nitride semiconductor layer is at the order of 10.sup.6 cm.sup.−2 or less.

10. The nitride semiconductor substrate according to claim 9, wherein the number of times of stacking is 2 to 300 times.

11. A nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, wherein the nitride semiconductor layer has a structure where an undoped nitride layer having the thickness of 0.1 to 50 nm and a rare earth element-doped nitride layer having the thickness of 0.1 to 2000 nm, which are different in local strain, are stacked once alternately, and the threading dislocation density on the surface of the nitride semiconductor layer is not more than 10.sup.6 cm.sup.−2 orders.

12. The nitride semiconductor substrate according to claim 11, wherein at least a part of the dislocations from the base material side is bent in the alternately stacked structure of the nitride semiconductor layers and disappears before reaching the surface.

13. The nitride semiconductor substrate according to claim 11, wherein the nitride semiconductor layer is removed from the base material and is formed as a nitride semiconductor bulk substrate.

14. A nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, wherein the nitride semiconductor layer has a super lattice structure where an undoped nitride layer having the thickness of 0.1 to 50 nm and a rare earth element-doped nitride layer having the thickness of 0.1 to 200 nm, which are different in local strain, are stacked alternately a plurality of times, and the threading dislocation density on the surface of the nitride semiconductor layer is not more than 10.sup.6 cm.sup.−2 orders.

15. A manufacturing method for a nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, having a step of forming an undoped nitride layer having the thickness of 0.1 to 50 nm to which the doping material is not doped by growing a crystal of GaN, InN or AlN or a mixed crystal of any two or more of them on the base material, and a step of forming a rare earth element-doped nitride layer having the thickness of 0.1 to 2000 nm on the undoped nitride layer by growing a crystal of GaN, InN or AlN, or a mixed crystal of any two or more of them, and doping a rare earth element as a doping material so as to substitute Ga, In or Al; wherein the two steps are conducted in a series of forming steps without taking it out of the reaction vessel under a temperature condition of 900 to 1200° C. by an organometallic vapor phase epitaxy.

16. The manufacturing method for a nitride semiconductor substrate according to claim 15, wherein Eu is used as the rare earth element.

17. The manufacturing method for a nitride semiconductor substrate according to claim 16, wherein Eu is provided from any one selected from Eu{N[Si(CH.sub.3).sub.3].sub.2}.sub.3, Eu(C.sub.11H.sub.19O.sub.2).sub.3 and Eu[C.sub.5(CH.sub.3).sub.4(C.sub.3H.sub.7)].sub.2.

18. The manufacturing method for a nitride semiconductor substrate according to claim 15, wherein any one of sapphire, SiC, Si and GaN is used as the base material.

19. The manufacturing method for a nitride semiconductor substrate according to claim 15 which further comprises a step of removing the nitride semiconductor layer formed on the base material from the base material to obtain a nitride semiconductor bulk substrate.

20. A manufacturing method for a nitride semiconductor substrate in which a nitride semiconductor layer is formed on a base material, having a step of forming an undoped nitride layer to which the doping material is not doped by growing a crystal of GaN, InN or AlN or a mixed crystal of any two or more of them on the base material, and a step of forming a rare earth element-doped nitride layer having the thickness of 0.1 to 200 nm on the undoped nitride layer by growing a crystal of GaN, InN or AlN or a mixed crystal of any two or more of them, and doping a rare earth element as a doping material so as to substitute Ga, In or Al; wherein the two steps are conducted in a series of forming steps without taking it out of the reaction vessel under a temperature condition of 900 to 1200° C. by an organometallic vapor phase epitaxy and are alternately repeated plural times.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 A schematic diagram showing the configuration of the nitride semiconductor substrate according to an embodiment of the present invention.

(2) FIG. 2 A TEM image of the nitride semiconductor substrate according to an embodiment of the present invention.

(3) FIG. 3 AFM images of the surface of the nitride semiconductor substrate according to an embodiment of the present invention.

(4) FIG. 4 AFM images of the surface of the Eu-doped GaN layer in the nitride semiconductor substrate according to an embodiment of the present invention.

(5) FIG. 5 A TEM image observing the cross section of the nitride semiconductor substrate from a specific direction according to an embodiment of the present invention.

(6) FIG. 6 A schematic diagram showing the configuration of the nitride semiconductor substrate according to another embodiment of the present invention.

(7) FIG. 7 An AFM image of the surface of the nitride semiconductor substrate according to another embodiment of the present invention.

(8) FIG. 8 A figure showing the relationship of the number of times of stacking and the threading dislocation density in the nitride semiconductor substrate according to another embodiment of the present invention.

(9) FIG. 9 A TEM image of the nitride semiconductor substrate according to another embodiment of the present invention.

EMBODIMENT FOR CARRYING OUT THE INVENTION

(10) Hereinafter, the present invention will be described based on the embodiments. In the following description, sapphire is used as the base material, GaN layer is used as the nitride semiconductor layer, and Eu is used as the rare earth element to be doped. However, as described above, the present invention is not limited to these.

[1] First Embodiment

(11) The present embodiment is a nitride semiconductor substrate, wherein an undoped nitride layer (ud-GaN layer) and a rare earth element-doped nitride layer (Eu-doped GaN layer) in which Eu is doped as a rare earth element are stacked one by one on a sapphire base material to form a nitride semiconductor layer. The nitride semiconductor substrate of the present embodiment will be described below.

(12) 1. Basic Configuration of the Nitride Semiconductor Substrate

(13) First, the basic configuration of the nitride semiconductor substrate according to the present embodiment will be described. FIG. 1 is a schematic view showing a configuration of a nitride semiconductor substrate according to the present embodiment. In FIG. 1, reference numeral 1 denotes a nitride semiconductor substrate, 10 denotes a sapphire base material, and 20 denotes a nitride semiconductor layer where the ud-GaN layer 21 and the Eu-doped GaN layer 22 are stacked once as a pair.

(14) The nitride semiconductor substrate according to the present embodiment may be used as a template for the production of a semiconductor device while forming the nitride semiconductor layer on a sapphire base material, in which the nitride semiconductor layer functions as a buffer layer. Hence, the nitride semiconductor layer may be expressed as a buffer layer in some case.

(15) Then, in the present embodiment, as shown in FIG. 1, between the sapphire base material 10 and the nitride semiconductor layer 20,

(16) LT-GaN layer 30 grown at a low temperature of about 475° C. in order to prevent the occurrence of cracks due to the difference of the lattice constant (lattice mismatch) between the sapphire base material 10 and GaN, and ud-GaN layer 40 for suppressing the influence of dislocations, by increasing the distance between the sapphire base material 10 and the nitride semiconductor layer (buffer layer) 20 are formed in advance.
2. Method of Manufacturing Nitride Semiconductor Substrate

(17) Next, the method of manufacturing a nitride semiconductor substrate according to the present embodiment will be described specifically with an example of producing a nitride semiconductor substrate 1 by stacking an ud-GaN layer 21 with a thickness of 10 nm and an Eu-doped GaN layer 22 with a thickness of 300 nm.

(18) First, by metalorganic vapor phase epitaxy (OMVPE), an LT-GaN layer 30 with a thickness of about 30 nm is grown on sapphire base material 10 under conditions of a growth temperature of 475° C. and a pressure of 100 kPa at a growth rate of 1.3 μm/h, and then an ud-GaN layer 40 with a thickness of about 2 μm was formed on the LT-GaN layer 30 under conditions of a growth temperature of 1150° C. and a pressure of 100 kPa at a growth rate of 0.8 μm/h.

(19) Next, by the OMVPE similarly, Eu-doped GaN layer 22 with a thickness of 300 nm was formed on the ud-GaN layer 40 under conditions of a growth temperature of 960° C. and a pressure of 100 kPa at a growth rate of 0.8 μm/h.

(20) Next, by OMVPE similarly, an ud-GaN layer 21 with a thickness of 10 nm was formed on the Eu-doped GaN layer 22 under conditions of a growth temperature of 960° C. and a pressure of 100 kPa at a growth rate of 0.8 μm/h.

(21) Thus, the nitride semiconductor layer 20 was formed by stacking the Eu-doped GaN layer 22 and the ud-GaN layer 21 one by one, and the manufacture of the nitride semiconductor substrate 1 was completed.

(22) In the above, trimethylgallium (TMGa) was used as the Ga source material, and the supply amount was 0.55 sccm. Then, ammonia (NH.sub.3) was used as the N source material, and the supply amount was 4.0 slm. In addition, Eu[C.sub.5(CH.sub.3).sub.4 (C.sub.3H.sub.7)].sub.2 bubbled with a carrier gas (hydrogen gas: H.sub.2) was used as the Eu organic raw material, and the supply amount was 1.5 slm (supply temperature: 115° C.).

(23) At this time, by changing the piping valve etc. of the OMVPE apparatus from the one with normal specification (heat resistant temperature 80 to 100° C.) to the one with high temperature special specification, the temperature for supplying Eu raw material was kept at a sufficiently high temperature of 115 to 135° C. in order to supply a sufficient amount of Eu to the reaction tube.

(24) In the present embodiment, the formation of each layer was performed in a series of steps so as not to interrupt the growth without taking the sample out of the reaction tube halfway.

(25) 3. Evaluation of Threading Dislocation Density

(26) (1) Evaluation Based on TEM Image

(27) Regarding the threading dislocation density on the surface of the nitride semiconductor substrate obtained above, first, the cross section is observed by a transmission electron microscope (TEM) to evaluate the effect of threading dislocation density reduction.

(28) FIG. 2 is a TEM image of a nitride semiconductor substrate. From FIG. 2, it can be seen that in this nitride semiconductor substrate, dislocations generated in the ud-GaN layer formed on the sapphire base material at the lower-most are propagated toward the surface. However, among these dislocations, although the dislocations reach the surface in the portion encircled by the dark dashed dotted line on the right side, the dislocations disappear, in the portion encircled by the light dashed dot line on the left, before reaching the surface in the stacked nitride semiconductor layer (buffer layer) in which an ud-GaN layer and an Eu-doped GaN layer are stacked. From this result, it can be confirmed that the threading dislocation density can be reduced in the nitride semiconductor substrate according to the present embodiment.

(29) (2) Evaluation Based on AFM Image

(30) Next, the state of dislocations appearing on the surface before and after the formation of the nitride semiconductor layer (buffer layer) was observed with an atomic force microscope (AFM) to evaluate the effect of the threading dislocation density reduction. The observation was conducted at the same position of 1 μm square.

(31) FIG. 3 is AFM images of the surface of the nitride semiconductor substrate, where (a) is the surface of the ud-GaN layer before the formation of the nitride semiconductor layer (buffer layer), (b) is the surface of the nitride semiconductor layer (buffer layer) after the formation of the nitride semiconductor layer (buffer layer).

(32) As shown in FIG. 3 (a), on the surface of the ud-GaN layer, dislocation-based pits are present at many places surrounded by circles, and the diameters of the pits are large. On the other hand, on the surface of the nitride semiconductor layer (buffer layer), as shown in FIG. 3 (b), only a few pits exist in a wide part surrounded by circles of alternate long and short dash line and the diameters of the pits are smaller.

(33) From this result, it can be confirmed that the threading dislocation density can be reduced in the nitride semiconductor substrate according to the present embodiment, similar to the result as described above. The reason why the diameter of the pits becomes has smaller is considered that the diameter of the pits formed in the GaN layer is related to the growth temperature, and the growth of the Eu-doped GaN layer to be the upper layer was performed at a low temperature of 960° C., thereby the diameter of the pits has become smaller. When the diameter of the pits becomes smaller and the pits are closed, the threading dislocation density is further reduced.

(34) Specifically, when the threading dislocation density was measured, it was 10.sup.8 to 10.sup.9 order in FIG. 3 (a), but it was reduced to 10.sup.6 order in FIG. 3 (b).

(35) (3) Relationship between Thickness of Eu-Doped GaN Layer and Threading Dislocation Density

(36) Further, in order to evaluate the relationship between thickness of Eu-doped GaN layer and threading dislocation density, on an ud-GaN layer with a thickness of 10 nm, an Eu-doped GaN layer was grown to a thickness of 900 nm according to the same manner as above, and how the thickness affected the threading dislocation density was evaluated.

(37) Specifically, when the thickness of the Eu-doped GaN layer reached 100 nm, 300 nm, and 900 nm, the appearance of dislocations appearing on the surface was observed by AFM according to the same manner as described above.

(38) FIG. 4 is AFM images of the surface of the Eu-doped GaN layer of each thickness, where (a) corresponds to thickness of 100 nm, (b) corresponds to thickness of 300 nm, and (c) corresponds to thickness of 900 nm.

(39) It can be seen from FIG. 4 that as the thickness of the Eu-doped GaN layer increases, the pits decrease as shown by encircled by a circle of alternate long and short dash line, and disappear almost at a thickness of 900 nm.

(40) Specifically, when the threading dislocation density is measured, it is 10.sup.8 order in FIG. 4 (a), it is 10.sup.7 order in FIG. 4 (b), and it is 10.sup.6 order in FIG. 4 (c). It has been confirmed from the result that the threading dislocation density is reduced dramatically as the thickness increases.

(41) (4) Propagation of Threading Dislocation Density in the Present Embodiment

(42) Here, propagation of the threading dislocation density in the present embodiment will be described with reference to FIG. 5. FIG. 5 is TEM images obtained by observing the cross section of the nitride semiconductor substrate manufactured above from a specific direction, specifically, upward g=[002] and g=[110]. Each is shown arranged up and down.

(43) In FIG. 5, the direction of g=[002] is a direction for determining screw dislocation, and the direction of g=[110] is a direction for determining edge dislocation. However, as can be seen from FIG. 5, in addition to these dislocations, several dislocations appear as mixed dislocations in both the direction of g=[002] and the direction of g=[110]. The growth and disappear of the mixed dislocations are controlled by the nitride semiconductor layer (buffer layer).

(44) Specifically, in FIG. 5, when the mixed dislocations propagate to the Eu-doped GaN layer of the nitride semiconductor layer (buffer layer), first, the screw dislocations converge and disappear, and then the vector of edge dislocations (edge vector) is converged, thereby the two mixed dislocations disappear without reaching the surface at the portion surrounded by the white oval of alternate long and short dash line.

(45) 4. Effect of the Present Embodiment

(46) As described above, in the present embodiment, a nitride semiconductor substrate having a sufficiently low threading dislocation density of 10.sup.6 cm.sup.−2 or less can be obtained, by a simple method of stacking the ud-GaN layer and the Eu-doped GaN layer once with appropriate thicknesses on an inexpensive sapphire base material. Therefore, the present embodiment is able to suitably meet the recent demand for inexpensively providing high-performance, long-life semiconductor devices.

[2] Second Embodiment

(47) In the above-described first embodiment, the threading dislocation density can be reduced according to the increase in the thickness of the Eu-doped GaN layer stacked on the ud-GaN layer. However, if the Eu-doped GaN layer is too thick, there is a risk that warpage occurs at the interface between the sapphire and the nitride semiconductor layer, due to a difference in thermal expansion coefficient between the sapphire as the base material and the GaN of the nitride semiconductor layer, thereby the product cannot be used as a nitride semiconductor substrate.

(48) Therefore, in the present embodiment, stacking the ud-GaN layer and the Eu-doped GaN layer alternately is repeated a plurality of times to form multiple pairs of the ud-GaN layer and the Eu-doped GaN layer on the sapphire base material and to form a nitride semiconductor layer having a superlattice structure, thereby a thin nitride semiconductor substrate with sufficiently reduced threading dislocation density can be manufactured.

(49) 1. Basic Configuration of Nitride Semiconductor Substrate

(50) First, the basic configuration of the nitride semiconductor substrate according to the present embodiment will be described. FIG. 6 is a schematic view showing the configuration of the nitride semiconductor substrate according to the present embodiment. The reference numerals in FIG. 6 are the same as in FIG. 1 except that the number of nitride semiconductor substrates is 2. As can be seen from FIG. 6, in the present embodiment, the configuration is the same as that of the nitride semiconductor substrate according to the first embodiment except that the nitride semiconductor layer 20 is formed by alternately stacking an Eu-doped GaN layer 22 and an ud-GaN layer 21 a plurality of times and the ud-GaN layer 21 is formed on the outermost layer from the viewpoint of suppressing oxidation.

(51) 2. Manufacturing Method for Nitride Semiconductor Substrate

(52) Also the manufacturing method for a nitride semiconductor substrate 2 according to the present embodiment is the same as the nitride semiconductor substrate manufacturing method according to the first embodiment, except that an ud-GaN layer 21 and an Eu-doped GaN layer 22 are repeatedly formed and the plurality of pairs of the ud-GaN layer 21 and the Eu-doped GaN layer 22 are stacked. In the present embodiment, the formation of each layer was performed in a series of steps so as not to interrupt the growth without taking the sample out of the reaction tube halfway.

(53) 3. Evaluation of Threading Dislocation Density

(54) (1) Evaluation Based on AFM Image

(55) By the manufacturing method for a nitride semiconductor substrate described above, the ud-GaN layer 21 with a thickness of 10 nm and the Eu-doped GaN layer 22 with a thickness of 1 nm are alternately stacked 40 times (40 pairs) to fabricate a nitride semiconductor substrate 2. Effect of the threading dislocation density reduction for the nitride semiconductor substrate 2 was evaluated based on the AFM image, as in the first embodiment.

(56) FIG. 7 is an AFM image of the surface of the nitride semiconductor substrate. Comparing this FIG. 7 with FIG. 4 (c) which is an AFM image of the surface of a nitride semiconductor substrate in which an Eu-doped GaN layer with a thickness of 900 nm is stacked once, it can be seen that the threading dislocation density is reduced further, although the total thickness (including the outermost ud-GaN layer) is 480 nm which is about half the thickness compared with FIG. 4 (c).

(57) From this result, it has been confirmed that, according to the present embodiment, the threading dislocation density can be reduced dramatically, even though the total thickness is thin, by stacking a plurality of times to form a nitride semiconductor layer having a superlattice structure, thereby the dislocations being bent in each Eu-doped GaN layer.

(58) (2) Influence of Number of Pairs (Number of Stackings) on Reduction of Threading Dislocation Density

(59) Next, in order to investigate the influence of number of pairs (number of stackings) on reduction of threading dislocation density, by the above-described manufacturing method for a nitride semiconductor substrate, an ud-GaN layer 21 with a thickness of 10 nm and Eu-doped GaN layer 22 with a thickness of 3 nm were stacked alternately and fabricates three kinds of nitride semiconductor substrates 2, in each of which a nitride semiconductor layers was formed, while the number of pairs (the number of stacking) was changed to 13 (experiment A), 40 (experiment B) and 70 (experiment C). Threading Dislocation density in Each of the nitride semiconductor substrates 2 thus fabricated was measured.

(60) The measurement results are shown in Table 1 and in FIG. 8. In FIG. 8, the horizontal axis represents the number of pairs, and the vertical axis represents threading dislocation density (×10.sup.6 cm.sup.−2). Further, a cross-sectional TEM image of a nitride semiconductor substrate manufactured by stacking the 40 pairs in Experiment B is shown in FIG. 9.

(61) TABLE-US-00001 Nitride Semiconductor Layer (MLS) Threading Thickness of Number Dislocation Eu-doped GaN Thickness of of Density Layer ud-Gan Layer Pairs (cm.sup.−2) Experiment A 3 nm 10 nm 13 5 × 10.sup.6 Experiment B 3 nm 10 nm 40 4 × 10.sup.6 Experiment C 3 nm 10 nm 70 2.4 × 10.sup.6  

(62) From Table 1 and FIG. 7, it is understood that the threading dislocation density is on the order of 10.sup.6 cm.sup.−2 even with the smallest number of pairs of 13 pairs, and the threading dislocation density is reduced as the number of pairs increases.

(63) Two dislocations, Dislocation 1 and Dislocation 2, exist in FIG. 9, Dislocations 1 are converged and disappeared after entering the nitride semiconductor layer (buffer layer). On the other hand, Dislocations 2 do not disappear, but the size of dislocations decreases as it passes through the pair. From this result in Table 1 and FIG. 7, it can be understood also that the threading dislocation density is further reduced in Experiment C in which the number of pairs is further increased to 70 pairs.

(64) Further, the above results satisfy the threading dislocation density (10.sup.6 cm.sup.−2 order) required in the case of producing a pickup with blue laser or a vertical power transistor using Si, SiC or the like. Therefore, it can be seen that the nitride semiconductor substrate according to the present embodiment can be used for manufacturing a blue laser for pickup used in Blu-Ray and a vertical power transistor, although it is formed on a sapphire base material.

(65) In addition, since the threading dislocation density is reduced as the number of pairs is increased, it is expected that 10.sup.4 cm.sup.−2 order required for the blue laser for writing used in Blu-Ray can be achieved by further increasing the number of pairs to further reduce the threading dislocation density.

(66) As described above, according to the present invention, as shown in the first embodiment and the second embodiment, a nitride semiconductor substrate can be provided which enables production of a high quality nitride semiconductor using an inexpensive sapphire base material or the like. In addition, since the nitride layer can be formed on the entire surface of the base material, the area can be increased and the practicability is excellent.

(67) And since a nitride semiconductor bulk substrate can be obtained by removing the base material from the above-described nitride semiconductor substrate, utilization may spread further as a nitride semiconductor substrate for semiconductor devices.

(68) As described above, although the present invention was explained based on the embodiments, the present invention is not limited to the above-described embodiments. Various modifications can be made to the above embodiments within the same and equivalent scope of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

(69) 1, 2 Nitride semiconductor substrate

(70) 10 Sapphire base material

(71) 20 Nitride semiconductor layer (buffer layer)

(72) 21 ud-GaN layer

(73) 22 Eu-doped GaN layer

(74) 30 LT-GaN layer

(75) 40 ud-GaN layer