Voltage-to-time converter and method for reducing parasitic capacitance and power supply influences

Abstract

The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

Claims

1. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply, comprising: a main sampling network, to sample a main input signal and a main reference level; a compensation sampling network, to sample a compensation input signal and a compensation reference level; the main sampling network comprises a main sampling capacitor and a main sampling common-mode level, the main sampling common-mode level samples and converts a difference between an input voltage and a reference voltage; the compensation sampling network comprises a compensation sampling capacitor and a compensation sampling common-mode level, the compensation sampling common-mode level samples and converts the difference between the input voltage and a reference level, and compensates the input voltage; a discharge network, to discharge the main sampling capacitor and the compensation sampling capacitor; an over-threshold detection unit, to detect whether the output level of the discharge network exceeds the threshold and convert an input level into time.

2. The voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 1, wherein in a sampling stage, the main sampling network and the compensation sampling network simultaneously sample the input voltage; in a conversion stage, the compensation sampling network is connected to the main sampling network, and performs voltage-time domain conversion simultaneously with the main sampling network.

3. The voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 2, wherein in the conversion phase, a relationship between a voltage of an input end of the over-threshold detection unit and the input voltage is: $V_{TCD}=\frac{C_{CMSP}\left(C_S+C_P\right)+V_{\mathrm{CC}}{C}_C}{C_C+C_S+C_P}+\left(V_{\mathrm{REF}}-V_{IN}\right)\frac{C_S+C_C}{C_C+C_S+C_P}$ V.sub.TCD is the voltage of the input end of the over-threshold detection unit, V.sub.CMSP is a main sampling common-mode level, V.sub.IN is the input voltage, V.sub.REF is a reference voltage, V.sub.CC is a compensation sampling common-mode level, C.sub.S is a main sampling capacitance, C.sub.C is a compensation sampling capacitance, CP is a parasitic capacitance at the input end of the over-threshold detection unit.

4. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 3, wherein a relationship between the compensation sampling common-mode level V.sub.CC and a power supply voltage V.sub.DD, and a relationship between a voltage threshold V.sub.TH of the over-threshold detection unit and the power supply voltage V.sub.DD are: $\{\begin{array}{c}{V}_{\mathrm{CC}}=\frac{C_C+C_S+C_P}{C_C}{V}_{TH}=\frac{C_C+C_S+C_P}{C_C}{\mathrm{KV}}_{DD}\\ V_{TH}={\mathrm{KV}}_{DD}\end{array}$ K is a proportionality coefficient between the voltage threshold of the over-threshold detection unit and the power supply voltage, V.sub.TH is the voltage threshold of the over-threshold detection unit, and V.sub.DD is the power supply voltage.

5. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 2, wherein the main sampling network further comprises a main input sampling switch, a main reference level sampling switch and a main common-mode sampling switch; the compensation sampling network further comprises a compensation input sampling switch, a compensation reference level sampling switch and a compensation common-mode sampling switch; the discharge network comprises a first discharge switch, a second discharge switch, and a constant current source; two ends of the main input sampling switch are respectively connected with the input voltage and one end of the main sampling capacitor, two ends of the main reference level sampling switch are respectively connected with the reference voltage and one end of the main sampling capacitor, and the other end of the main sampling capacitor is connected with the main sampling common-mode level through the main common-mode sampling switch; two ends of the compensation input sampling switch are respectively connected with the input voltage and one end of the compensation sampling capacitor, two ends of the compensation reference level sampling switch are respectively connected with the reference voltage and one end of the compensation sampling capacitor, and the other end of the compensation sampling capacitor is connected with the compensation sampling common-mode level through the compensation common-mode sampling switch; one end of the first discharge switch is connected with the other end of the compensation sampling capacitor; the other end of the first discharge switch is connected with one end of the second discharge switch and the input end of the over-threshold detection unit; the other end of the second discharge switch is grounded via the constant current source; the input end of the over-threshold detection unit is grounded via the parasitic capacitance at the input end of the over-threshold detection unit.

6. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 5, wherein the switches and capacitors of the main sampling network have structures same as that of the switches and capacitors of the compensation sampling network; size parameters of corresponding devices between the switches and capacitors of the main sampling network and the switches and capacitors of the compensation sampling network are proportional, and an RC time constant of the main sampling network is the same as that of the compensation sampling network.

7. A voltage-to-time conversion method for reducing influences of parasitic capacitance and power supply, comprising: providing a main sampling network to sample a main input signal and a main reference level, and providing a compensation sampling network to sample a compensation input signal and a compensation reference level; the main sampling network comprises a main sampling capacitor and a main sampling common-mode level, the main sampling common-mode level samples and converts a difference between an input voltage and a reference voltage; the compensation sampling network comprises a compensation sampling capacitor and a compensation sampling common-mode level, the compensation sampling common-mode level samples and converts a difference between the input voltage and a reference level, and compensates the input voltage; in a sampling stage, sampling the input voltage simultaneously by the main sampling network and the compensation sampling network; in a conversion phase, merging the compensation sampling network with the main sampling network, accessing to a conversion network to detect whether an output level of a discharge network exceeds a threshold, and converting an input level into time.

8. The voltage-to-time conversion method for reducing influences of parasitic capacitance and power supply according to claim 7, wherein in the conversion phase, a relationship between a voltage of an input end of an over-threshold detection unit and the input voltage is: $V_{TCD}=\frac{V_{CMSP}\left(C_S+C_P\right)+V_{\mathrm{CC}}{C}_C}{C_C+C_S+C_P}+\left(V_{\mathrm{REF}}-V_{IN}\right)\frac{C_S+C_C}{C_C+C_S+C_P}$ V.sub.TCD is the voltage of the input end of the over-threshold detection unit, V.sub.CMSP is a main sampling common-mode level, V.sub.IN is the input voltage, V.sub.REF is a reference voltage, V.sub.CC is a compensation sampling common-mode level, C.sub.S is a main sampling capacitance, C.sub.C is a compensation sampling capacitance, C.sub.P is a parasitic capacitance at the input end of the over-threshold detector.

9. The voltage-to-time conversion method for reducing influences of parasitic capacitance and power supply according to claim 7, wherein a relationship between the compensation sampling common-mode level V.sub.CC and a power supply voltage V.sub.DD, and a relationship between a voltage threshold V.sub.TH of the over-threshold detection unit and the power supply voltage V.sub.DD are: $\{\begin{array}{c}{V}_{\mathrm{CC}}=\frac{C_C+C_S+C_P}{C_C}{V}_{TH}=\frac{C_C+C_S+C_P}{C_C}{\mathrm{KV}}_{DD}\\ V_{TH}={\mathrm{KV}}_{DD}\end{array}$ K is the proportionality coefficient between the voltage threshold of the over-threshold detection unit and the power supply voltage, V.sub.TH is the voltage threshold of the over-threshold detection unit, and V.sub.DD is the power supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic principle diagram of the present disclosure.

(2) FIG. 2 is a circuit schematic diagram of a voltage-to-time converter for reducing the influences of parasitic capacitance and power supply in an Embodiment of the present disclosure.

(3) FIG. 3 is a timing relationship diagram of a voltage-to-time conversion method for reducing the influences of parasitic capacitance and power supply in an Embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) The embodiments of the present disclosure will be described below. Those skilled in the art can easily understand other advantages and effects of the present disclosure according to contents disclosed by the specification. The present disclosure can also be implemented or applied through other different exemplary embodiments. Various modifications or changes can also be made to all details in the specification based on different points of view and applications without departing from the spirit of the present disclosure. It needs to be stated that the following embodiments and the features in the embodiments can be combined with one another under the situation of no conflict.

(5) It needs to be stated that the drawings provided in the following embodiments are just used for schematically describing the basic concept of the present disclosure, thus only illustrating components only related to the present disclosure and are not drawn according to the numbers, shapes and sizes of components during actual implementation, the configuration, number and scale of each component during the actual implementation thereof may be freely changed, and the component layout configuration thereof may be more complicated.

(6) In this Embodiment, the voltage-to-time converter for reducing the influence of parasitic capacitance and power supply includes:

(7) a main sampling network, to sample a main input signal and a main reference level;

(8) a compensation sampling network, to sample a compensation input signal and a compensation reference level;

(9) the main sampling network includes a main sampling capacitor, and a main sampling common-mode level for sampling and converting the difference between the input voltage and the reference voltage; the compensation sampling network includes a compensation sampling capacitor and a compensation sampling common-mode level, the compensation sampling common-mode level samples and converts the difference between the input voltage and the reference level, and compensates the input voltage;

(10) a discharge network, to discharge the main sampling capacitor and the compensation sampling capacitor;

(11) an over-threshold detection unit, to detect whether the output level of the discharge network exceeds the threshold and convert the input level into time.

(12) As shown in FIG. 1, in this Embodiment, the main sampling network mainly includes a main input sampling switch SW.sub.SM, a main reference level sampling switch SW.sub.RM, a main common-mode sampling switch SW.sub.SPM, and a main sampling capacitor C.sub.S. The main sampling common-mode level is V.sub.CMSP, which is mainly used to sample and convert the difference between the input signal V.sub.IN and the reference voltage V.sub.REF. The compensation sampling network mainly includes a compensation input sampling switch SW.sub.SC, a compensation reference level sampling switch SW.sub.RC, a compensation common-mode sampling switch SW.sub.SPC, and a compensation sampling capacitor C.sub.C. The compensation sampling common-mode level is V.sub.CC, to sample and convert the difference between the input signal V.sub.IN and the reference level V.sub.REF, and compensate the influence of the power supply voltage on the threshold through V.sub.CC. The discharge network mainly includes discharge switch SW.sub.VTC1, discharge switch SW.sub.VTC2 and current source I.sub.DIS. The discharge network is mainly used to discharge the input signals sampled by the main sampling capacitor C.sub.S and the compensation sampling capacitor C.sub.C. The current source I.sub.DIS is a constant current source, the value of the current source I.sub.DIS is determined by the discharge clock pulse width, TCD threshold level, TCD input end common-mode and the swing amplitude of the input signal V.sub.REF−V.sub.IN. In this embodiment, the over-threshold detection unit is an over-threshold detector TCD, to detect whether the output level of the discharge network exceeds the threshold. If the threshold is exceeded, the output of the TCD is inverted. Specifically, the TCD detects the discharge at the input end. When the level at the input end is lower than the threshold level, the output of the TCD is inverted, to complete the conversion of input level to time. In this embodiment, by using a compensation sampling network and a compensating voltage, the influence of power supply voltage fluctuation on parasitic capacitance and the TCD threshold of the traditional VTC are eliminated respectively.

(13) In this embodiment, the compensation sampling network and the main sampling network sample the input signal simultaneously at the sampling stage, accesses the conversion network at the conversion stage, and performs voltage-to-time conversion simultaneously with the main sampling network. At this time, the relationship between the voltage of the input end of over-threshold detection detector TCD and the input voltage turns into:

(14) $\begin{array}{cc}{V}_{TCD}=\frac{V_{CMSP}\left(C_S+C_P\right)+V_{\mathrm{CC}}{C}_C}{C_C+C_S+C_P}+\left(V_{\mathrm{REF}}-V_{\mathrm{IN}}\right)\frac{C_S+C_C}{C_C+C_S+C_P}& \left(\mathrm{Formula}1\right)\end{array}$

(15) V.sub.TCD is the voltage of the input end of the over-threshold detection unit, V.sub.CMSP is the main sampling common-mode level, V.sub.IN is the input voltage, V.sub.REF is the reference voltage, V.sub.CC is the compensation sampling common-mode level, C.sub.S is the main sampling capacitance, C.sub.C is the compensation sampling capacitance, C.sub.P is the parasitic capacitance at the input end of the over-threshold detection unit. Assuming that the sampling common-mode level V.sub.CC of the compensation sampling network is equal to 0 V, the larger the compensation capacitance, the less the VTC output swing amplitude is influenced by the parasitic capacitance.

(16) A compensation design is made for the sampling common-mode level V.sub.CC of the sampling network, such that the relationship between V.sub.CC and the power supply voltage is:

(17) $\begin{array}{cc}{V}_{\mathrm{CC}}=\frac{C_C+C_S+C_P}{C_C}{\mathrm{KV}}_{\mathrm{DD}}& \left(\mathrm{Formula}2\right)\end{array}$

(18) The voltage common-mode level V.sub.TCD of the VTC input end is related to the power supply voltage V.sub.DD, thereby reducing the conversion error caused by the influence of the power supply voltage V.sub.DD on the threshold.

(19) As shown in FIG. 2, the two ends of the main input sampling switch SW.sub.SC are respectively connected with the input voltage V.sub.IN and one end of the main sampling capacitor C.sub.S. The two ends of the main reference level sampling switch SW.sub.RM are respectively connected with the reference voltage V.sub.REF and one end of the main sampling capacitor C.sub.S. The other end of the main sampling capacitor C.sub.S is connected with the main sampling common-mode level V.sub.CMSP through the main common-mode sampling switch SW.sub.SPM. The two ends of the compensation input sampling switch SW.sub.SC are respectively connected with the input voltage V.sub.IN and one end of the compensation sampling capacitor C.sub.C. The two ends of the compensation reference level sampling switch SW.sub.RC are respectively connected with the reference voltage V.sub.REF and one end of the compensation sampling capacitor C.sub.C. The other end of the compensation sampling capacitor C.sub.C is connected with the compensation sampling common-mode level V.sub.CC through the compensation common-mode sampling switch SW.sub.SPC.

(20) One end of the first discharge switch SW.sub.VTC1 is connected with the other end of the compensation sampling capacitor C.sub.C. The other end of the first discharge switch SW.sub.VTC1 is connected with one end of the second discharge switch SW.sub.VTC2 and the input end of the over-threshold detection unit. The other end of the second discharge switch SW.sub.VTC2 is grounded via the constant current source I.sub.DIS. One end of the parasitic capacitance C.sub.P at the input end of the over-threshold detection unit is connected with the input end of the over-threshold detection unit, and the other end of the parasitic capacitance C.sub.P is grounded.

(21) In this embodiment, the size of the main sampling capacitor is limited by other design specifications of the circuit. When the value is small, the larger the value of the compensation capacitor, the smaller the influence on the parasitic capacitance. In addition, the switches and capacitors of the main sampling network have structures same as that of the switches and capacitors of the compensation sampling network. Size parameters of corresponding devices between the switches and capacitors of the main sampling network and the switches and capacitors of the compensation sampling network are proportional, to ensure that the RC time constant of the main sampling network is the same as that of the compensation sampling network. The compensation sampling common-mode level V.sub.CC may be designed in any level generation manner, as long as the voltage relationship in the above (Formula 2) is satisfied.

(22) Correspondingly, this embodiment also provides a voltage-to-time conversion method for reducing the influence of parasitic capacitance and power supply, including:

(23) providing a main sampling network to sample a main input signal and a main reference level, and providing a compensation sampling network to sample a compensation input signal and a compensation reference level;

(24) the main sampling network includes a main sampling capacitor and a main sampling common-mode level, and the main sampling common-mode level samples and converts the difference between the input voltage and the reference voltage; the compensation sampling network includes a compensation sampling capacitor and a compensation sampling common-mode level, and the compensation sampling common-mode level samples and converts the difference between the input voltage and the reference level, and compensates the input voltage;

(25) in the sampling stage, sampling the input voltage simultaneously by the main sampling network and the compensation sampling network;

(26) in the conversion stage, connecting the compensation sampling network to a conversion network, performing the voltage-time conversion simultaneously with the main sampling network, detecting, by the over-threshold detection unit, whether the output level of the discharge network exceeds the threshold, and converting the input level into time.

(27) As shown in FIG. 3, in this embodiment, when the sampling clocks Φ.sub.S and Φ.sub.SP are at high levels, as shown in the circuit diagram of FIG. 2, the switches SW.sub.SM, SW.sub.SC, SW.sub.SPM and SW.sub.SPC are turned on, the remaining switches SW.sub.RM, SW.sub.RC, SW.sub.VTC1 and SW.sub.VTC2 are disconnected, the VTC enters the sampling stage, and the main sampling capacitor C.sub.S and the compensation sampling capacitor C.sub.C track and maintain the input signal V.sub.IN. When the falling edge of the lower plate sampling clock Φ.sub.SP arrives, the switches SW.sub.SPM and SW.sub.SPC are disconnected, and the main sampling capacitor C.sub.S and the compensation sampling capacitor C.sub.C maintain the input signal V.sub.IN.

(28) When the conversion clock Φ.sub.VTC is at high level, the switches SW.sub.RM, SW.sub.RC, SW.sub.VTC1 and SW.sub.VTC2 are turned on, the remaining SW.sub.SM, SW.sub.SC, SW.sub.SPM and SW.sub.SPC are disconnected, and VTC enters the conversion phase.

(29) The initial value of TCD input voltage is:

(30) $V_{TCD}=\frac{V_{CMSP}\left(C_S+C_P\right)+V_{\mathrm{CC}}{C}_C}{C_C+C_S+C_P}+\left(V_{\mathrm{REF}}-V_{IN}\right)\frac{C_S+C_C}{C_C+C_S+C_P}$

(31) The compensation sampling common-mode level V.sub.CC is related to the threshold voltage of the over-threshold detector TCD:

(32) $V_{\mathrm{CC}}=\frac{C_C+C_S+C_P}{C_C}{V}_{\mathrm{TH}}=\frac{C_C+C_S+C_P}{C_C}{\mathrm{KV}}_{DD}$

(33) K is the proportionality coefficient between the voltage threshold V.sub.TH of the over-threshold detector TCD and the power supply voltage V.sub.DD, V.sub.TH represents the TCD inversion threshold. The compensation sampling level V.sub.CC may be designed in any level generation manner, as long as the voltage relationship in the above formula is satisfied. Substituting the V.sub.CC expression into the V.sub.TCD expression to get:

(34) $V_{TCD}=\frac{V_{CMSP}\left(C_S+C_P\right)}{C_C+C_S+C_P}+V_{\mathrm{TH}}+\left(V_{\mathrm{REF}}-V_{IN}\right)\frac{C_S+C_C}{C_C+C_S+C_P}$

(35) The discharge relationship of TCD input voltage is:

(36) 0$V_{\mathrm{TCD\_DIS}}=V_{TCD}-\frac{I_{DIS}.Math.t}{C_C+C_S+C_P}$

(37) The over-threshold detector detects whether the discharge level V.sub.TCD_DIS is lower than the threshold V.sub.TH, that is, the conversion output time corresponding to the input signal V.sub.IN is:

(38) $t=\frac{\left(V_{\mathrm{TCD\_DIS}}-V_{TH}\right)\left(C_C+C_S+C_P\right)}{I_{DIS}}$

(39) By substituting the V.sub.TCD expression into the above formula, the influence of the threshold voltage V.sub.TH on the output time can be eliminated, that is, the influence of V.sub.TH on the overall performance of the system caused by the power supply voltage fluctuations is eliminated.

(40) When VTC discharges to time to, V.sub.TCD_DISS−V.sub.TH<0, then the output of the over-threshold detector TCD is inverted, and the output time to corresponding to V.sub.REF−V.sub.IN is recorded. VTC conversion ends.

(41) The above-mentioned embodiments are merely illustrative of the principle and effects of the present disclosure instead of limiting the present disclosure. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, all equivalent modifications or changes made by those who have common knowledge in the art without departing from the spirit and technical concept disclosed by the present disclosure shall be still covered by the claims of the present disclosure.